1/* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _vega20_ip_offset_HEADER 22#define _vega20_ip_offset_HEADER 23 24#define MAX_INSTANCE 6 25#define MAX_SEGMENT 6 26 27 28struct IP_BASE_INSTANCE { 29 unsigned int segment[MAX_SEGMENT]; 30}; 31 32struct IP_BASE { 33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 34} __maybe_unused; 35 36 37static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0, 0 } }, 38 { { 0, 0, 0, 0, 0, 0 } }, 39 { { 0, 0, 0, 0, 0, 0 } }, 40 { { 0, 0, 0, 0, 0, 0 } }, 41 { { 0, 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0, 0 } } } }; 43static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } }, 44 { { 0, 0, 0, 0, 0, 0 } }, 45 { { 0, 0, 0, 0, 0, 0 } }, 46 { { 0, 0, 0, 0, 0, 0 } }, 47 { { 0, 0, 0, 0, 0, 0 } }, 48 { { 0, 0, 0, 0, 0, 0 } } } }; 49static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0, 0 } }, 51 { { 0, 0, 0, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0, 0 } } } }; 55static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0, 0 } } } }; 61static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0, 0 } }, 65 { { 0, 0, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0, 0 } } } }; 67static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0, 0 } } } }; 73static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0, 0 } } } }; 79static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0, 0 } } } }; 85static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0, 0 } } } }; 91static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0, 0 } } } }; 97static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, 98 { { 0, 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0, 0 } } } }; 103static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0, 0 } } } }; 109static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } } } }; 115static const struct IP_BASE SDMA1_BASE = { { { { 0x00001860, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0, 0 } } } }; 121static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0 } } } }; 127static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0 } } } }; 133static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0, 0 } } } }; 139static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } }, 140 { { 0, 0x00009000, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0, 0 } } } }; 145/* Adjust VCE_BASE to make vce_4_1 use vce_4_0 offset header files*/ 146static const struct IP_BASE VCE_BASE = { { { { 0x00007E00/* 0x00008800 */, 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0, 0 } }, 149 { { 0, 0, 0, 0, 0, 0 } }, 150 { { 0, 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0, 0 } } } }; 152static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0, 0 } } } }; 158static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0, 0 } }, 160 { { 0, 0, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0, 0 } } } }; 164 165 166#define ATHUB_BASE__INST0_SEG0 0x00000C20 167#define ATHUB_BASE__INST0_SEG1 0 168#define ATHUB_BASE__INST0_SEG2 0 169#define ATHUB_BASE__INST0_SEG3 0 170#define ATHUB_BASE__INST0_SEG4 0 171#define ATHUB_BASE__INST0_SEG5 0 172 173#define ATHUB_BASE__INST1_SEG0 0 174#define ATHUB_BASE__INST1_SEG1 0 175#define ATHUB_BASE__INST1_SEG2 0 176#define ATHUB_BASE__INST1_SEG3 0 177#define ATHUB_BASE__INST1_SEG4 0 178#define ATHUB_BASE__INST1_SEG5 0 179 180#define ATHUB_BASE__INST2_SEG0 0 181#define ATHUB_BASE__INST2_SEG1 0 182#define ATHUB_BASE__INST2_SEG2 0 183#define ATHUB_BASE__INST2_SEG3 0 184#define ATHUB_BASE__INST2_SEG4 0 185#define ATHUB_BASE__INST2_SEG5 0 186 187#define ATHUB_BASE__INST3_SEG0 0 188#define ATHUB_BASE__INST3_SEG1 0 189#define ATHUB_BASE__INST3_SEG2 0 190#define ATHUB_BASE__INST3_SEG3 0 191#define ATHUB_BASE__INST3_SEG4 0 192#define ATHUB_BASE__INST3_SEG5 0 193 194#define ATHUB_BASE__INST4_SEG0 0 195#define ATHUB_BASE__INST4_SEG1 0 196#define ATHUB_BASE__INST4_SEG2 0 197#define ATHUB_BASE__INST4_SEG3 0 198#define ATHUB_BASE__INST4_SEG4 0 199#define ATHUB_BASE__INST4_SEG5 0 200 201#define ATHUB_BASE__INST5_SEG0 0 202#define ATHUB_BASE__INST5_SEG1 0 203#define ATHUB_BASE__INST5_SEG2 0 204#define ATHUB_BASE__INST5_SEG3 0 205#define ATHUB_BASE__INST5_SEG4 0 206#define ATHUB_BASE__INST5_SEG5 0 207 208#define CLK_BASE__INST0_SEG0 0x00016C00 209#define CLK_BASE__INST0_SEG1 0x00016E00 210#define CLK_BASE__INST0_SEG2 0x00017000 211#define CLK_BASE__INST0_SEG3 0x00017200 212#define CLK_BASE__INST0_SEG4 0x0001B000 213#define CLK_BASE__INST0_SEG5 0x0001B200 214 215#define CLK_BASE__INST1_SEG0 0 216#define CLK_BASE__INST1_SEG1 0 217#define CLK_BASE__INST1_SEG2 0 218#define CLK_BASE__INST1_SEG3 0 219#define CLK_BASE__INST1_SEG4 0 220#define CLK_BASE__INST1_SEG5 0 221 222#define CLK_BASE__INST2_SEG0 0 223#define CLK_BASE__INST2_SEG1 0 224#define CLK_BASE__INST2_SEG2 0 225#define CLK_BASE__INST2_SEG3 0 226#define CLK_BASE__INST2_SEG4 0 227#define CLK_BASE__INST2_SEG5 0 228 229#define CLK_BASE__INST3_SEG0 0 230#define CLK_BASE__INST3_SEG1 0 231#define CLK_BASE__INST3_SEG2 0 232#define CLK_BASE__INST3_SEG3 0 233#define CLK_BASE__INST3_SEG4 0 234#define CLK_BASE__INST3_SEG5 0 235 236#define CLK_BASE__INST4_SEG0 0 237#define CLK_BASE__INST4_SEG1 0 238#define CLK_BASE__INST4_SEG2 0 239#define CLK_BASE__INST4_SEG3 0 240#define CLK_BASE__INST4_SEG4 0 241#define CLK_BASE__INST4_SEG5 0 242 243#define CLK_BASE__INST5_SEG0 0 244#define CLK_BASE__INST5_SEG1 0 245#define CLK_BASE__INST5_SEG2 0 246#define CLK_BASE__INST5_SEG3 0 247#define CLK_BASE__INST5_SEG4 0 248#define CLK_BASE__INST5_SEG5 0 249 250#define DCE_BASE__INST0_SEG0 0x00000012 251#define DCE_BASE__INST0_SEG1 0x000000C0 252#define DCE_BASE__INST0_SEG2 0x000034C0 253#define DCE_BASE__INST0_SEG3 0 254#define DCE_BASE__INST0_SEG4 0 255#define DCE_BASE__INST0_SEG5 0 256 257#define DCE_BASE__INST1_SEG0 0 258#define DCE_BASE__INST1_SEG1 0 259#define DCE_BASE__INST1_SEG2 0 260#define DCE_BASE__INST1_SEG3 0 261#define DCE_BASE__INST1_SEG4 0 262#define DCE_BASE__INST1_SEG5 0 263 264#define DCE_BASE__INST2_SEG0 0 265#define DCE_BASE__INST2_SEG1 0 266#define DCE_BASE__INST2_SEG2 0 267#define DCE_BASE__INST2_SEG3 0 268#define DCE_BASE__INST2_SEG4 0 269#define DCE_BASE__INST2_SEG5 0 270 271#define DCE_BASE__INST3_SEG0 0 272#define DCE_BASE__INST3_SEG1 0 273#define DCE_BASE__INST3_SEG2 0 274#define DCE_BASE__INST3_SEG3 0 275#define DCE_BASE__INST3_SEG4 0 276#define DCE_BASE__INST3_SEG5 0 277 278#define DCE_BASE__INST4_SEG0 0 279#define DCE_BASE__INST4_SEG1 0 280#define DCE_BASE__INST4_SEG2 0 281#define DCE_BASE__INST4_SEG3 0 282#define DCE_BASE__INST4_SEG4 0 283#define DCE_BASE__INST4_SEG5 0 284 285#define DCE_BASE__INST5_SEG0 0 286#define DCE_BASE__INST5_SEG1 0 287#define DCE_BASE__INST5_SEG2 0 288#define DCE_BASE__INST5_SEG3 0 289#define DCE_BASE__INST5_SEG4 0 290#define DCE_BASE__INST5_SEG5 0 291 292#define DF_BASE__INST0_SEG0 0x00007000 293#define DF_BASE__INST0_SEG1 0 294#define DF_BASE__INST0_SEG2 0 295#define DF_BASE__INST0_SEG3 0 296#define DF_BASE__INST0_SEG4 0 297#define DF_BASE__INST0_SEG5 0 298 299#define DF_BASE__INST1_SEG0 0 300#define DF_BASE__INST1_SEG1 0 301#define DF_BASE__INST1_SEG2 0 302#define DF_BASE__INST1_SEG3 0 303#define DF_BASE__INST1_SEG4 0 304#define DF_BASE__INST1_SEG5 0 305 306#define DF_BASE__INST2_SEG0 0 307#define DF_BASE__INST2_SEG1 0 308#define DF_BASE__INST2_SEG2 0 309#define DF_BASE__INST2_SEG3 0 310#define DF_BASE__INST2_SEG4 0 311#define DF_BASE__INST2_SEG5 0 312 313#define DF_BASE__INST3_SEG0 0 314#define DF_BASE__INST3_SEG1 0 315#define DF_BASE__INST3_SEG2 0 316#define DF_BASE__INST3_SEG3 0 317#define DF_BASE__INST3_SEG4 0 318#define DF_BASE__INST3_SEG5 0 319 320#define DF_BASE__INST4_SEG0 0 321#define DF_BASE__INST4_SEG1 0 322#define DF_BASE__INST4_SEG2 0 323#define DF_BASE__INST4_SEG3 0 324#define DF_BASE__INST4_SEG4 0 325#define DF_BASE__INST4_SEG5 0 326 327#define DF_BASE__INST5_SEG0 0 328#define DF_BASE__INST5_SEG1 0 329#define DF_BASE__INST5_SEG2 0 330#define DF_BASE__INST5_SEG3 0 331#define DF_BASE__INST5_SEG4 0 332#define DF_BASE__INST5_SEG5 0 333 334#define FUSE_BASE__INST0_SEG0 0x00017400 335#define FUSE_BASE__INST0_SEG1 0 336#define FUSE_BASE__INST0_SEG2 0 337#define FUSE_BASE__INST0_SEG3 0 338#define FUSE_BASE__INST0_SEG4 0 339#define FUSE_BASE__INST0_SEG5 0 340 341#define FUSE_BASE__INST1_SEG0 0 342#define FUSE_BASE__INST1_SEG1 0 343#define FUSE_BASE__INST1_SEG2 0 344#define FUSE_BASE__INST1_SEG3 0 345#define FUSE_BASE__INST1_SEG4 0 346#define FUSE_BASE__INST1_SEG5 0 347 348#define FUSE_BASE__INST2_SEG0 0 349#define FUSE_BASE__INST2_SEG1 0 350#define FUSE_BASE__INST2_SEG2 0 351#define FUSE_BASE__INST2_SEG3 0 352#define FUSE_BASE__INST2_SEG4 0 353#define FUSE_BASE__INST2_SEG5 0 354 355#define FUSE_BASE__INST3_SEG0 0 356#define FUSE_BASE__INST3_SEG1 0 357#define FUSE_BASE__INST3_SEG2 0 358#define FUSE_BASE__INST3_SEG3 0 359#define FUSE_BASE__INST3_SEG4 0 360#define FUSE_BASE__INST3_SEG5 0 361 362#define FUSE_BASE__INST4_SEG0 0 363#define FUSE_BASE__INST4_SEG1 0 364#define FUSE_BASE__INST4_SEG2 0 365#define FUSE_BASE__INST4_SEG3 0 366#define FUSE_BASE__INST4_SEG4 0 367#define FUSE_BASE__INST4_SEG5 0 368 369#define FUSE_BASE__INST5_SEG0 0 370#define FUSE_BASE__INST5_SEG1 0 371#define FUSE_BASE__INST5_SEG2 0 372#define FUSE_BASE__INST5_SEG3 0 373#define FUSE_BASE__INST5_SEG4 0 374#define FUSE_BASE__INST5_SEG5 0 375 376#define GC_BASE__INST0_SEG0 0x00002000 377#define GC_BASE__INST0_SEG1 0x0000A000 378#define GC_BASE__INST0_SEG2 0 379#define GC_BASE__INST0_SEG3 0 380#define GC_BASE__INST0_SEG4 0 381#define GC_BASE__INST0_SEG5 0 382 383#define GC_BASE__INST1_SEG0 0 384#define GC_BASE__INST1_SEG1 0 385#define GC_BASE__INST1_SEG2 0 386#define GC_BASE__INST1_SEG3 0 387#define GC_BASE__INST1_SEG4 0 388#define GC_BASE__INST1_SEG5 0 389 390#define GC_BASE__INST2_SEG0 0 391#define GC_BASE__INST2_SEG1 0 392#define GC_BASE__INST2_SEG2 0 393#define GC_BASE__INST2_SEG3 0 394#define GC_BASE__INST2_SEG4 0 395#define GC_BASE__INST2_SEG5 0 396 397#define GC_BASE__INST3_SEG0 0 398#define GC_BASE__INST3_SEG1 0 399#define GC_BASE__INST3_SEG2 0 400#define GC_BASE__INST3_SEG3 0 401#define GC_BASE__INST3_SEG4 0 402#define GC_BASE__INST3_SEG5 0 403 404#define GC_BASE__INST4_SEG0 0 405#define GC_BASE__INST4_SEG1 0 406#define GC_BASE__INST4_SEG2 0 407#define GC_BASE__INST4_SEG3 0 408#define GC_BASE__INST4_SEG4 0 409#define GC_BASE__INST4_SEG5 0 410 411#define GC_BASE__INST5_SEG0 0 412#define GC_BASE__INST5_SEG1 0 413#define GC_BASE__INST5_SEG2 0 414#define GC_BASE__INST5_SEG3 0 415#define GC_BASE__INST5_SEG4 0 416#define GC_BASE__INST5_SEG5 0 417 418#define HDP_BASE__INST0_SEG0 0x00000F20 419#define HDP_BASE__INST0_SEG1 0 420#define HDP_BASE__INST0_SEG2 0 421#define HDP_BASE__INST0_SEG3 0 422#define HDP_BASE__INST0_SEG4 0 423#define HDP_BASE__INST0_SEG5 0 424 425#define HDP_BASE__INST1_SEG0 0 426#define HDP_BASE__INST1_SEG1 0 427#define HDP_BASE__INST1_SEG2 0 428#define HDP_BASE__INST1_SEG3 0 429#define HDP_BASE__INST1_SEG4 0 430#define HDP_BASE__INST1_SEG5 0 431 432#define HDP_BASE__INST2_SEG0 0 433#define HDP_BASE__INST2_SEG1 0 434#define HDP_BASE__INST2_SEG2 0 435#define HDP_BASE__INST2_SEG3 0 436#define HDP_BASE__INST2_SEG4 0 437#define HDP_BASE__INST2_SEG5 0 438 439#define HDP_BASE__INST3_SEG0 0 440#define HDP_BASE__INST3_SEG1 0 441#define HDP_BASE__INST3_SEG2 0 442#define HDP_BASE__INST3_SEG3 0 443#define HDP_BASE__INST3_SEG4 0 444#define HDP_BASE__INST3_SEG5 0 445 446#define HDP_BASE__INST4_SEG0 0 447#define HDP_BASE__INST4_SEG1 0 448#define HDP_BASE__INST4_SEG2 0 449#define HDP_BASE__INST4_SEG3 0 450#define HDP_BASE__INST4_SEG4 0 451#define HDP_BASE__INST4_SEG5 0 452 453#define HDP_BASE__INST5_SEG0 0 454#define HDP_BASE__INST5_SEG1 0 455#define HDP_BASE__INST5_SEG2 0 456#define HDP_BASE__INST5_SEG3 0 457#define HDP_BASE__INST5_SEG4 0 458#define HDP_BASE__INST5_SEG5 0 459 460#define MMHUB_BASE__INST0_SEG0 0x0001A000 461#define MMHUB_BASE__INST0_SEG1 0 462#define MMHUB_BASE__INST0_SEG2 0 463#define MMHUB_BASE__INST0_SEG3 0 464#define MMHUB_BASE__INST0_SEG4 0 465#define MMHUB_BASE__INST0_SEG5 0 466 467#define MMHUB_BASE__INST1_SEG0 0 468#define MMHUB_BASE__INST1_SEG1 0 469#define MMHUB_BASE__INST1_SEG2 0 470#define MMHUB_BASE__INST1_SEG3 0 471#define MMHUB_BASE__INST1_SEG4 0 472#define MMHUB_BASE__INST1_SEG5 0 473 474#define MMHUB_BASE__INST2_SEG0 0 475#define MMHUB_BASE__INST2_SEG1 0 476#define MMHUB_BASE__INST2_SEG2 0 477#define MMHUB_BASE__INST2_SEG3 0 478#define MMHUB_BASE__INST2_SEG4 0 479#define MMHUB_BASE__INST2_SEG5 0 480 481#define MMHUB_BASE__INST3_SEG0 0 482#define MMHUB_BASE__INST3_SEG1 0 483#define MMHUB_BASE__INST3_SEG2 0 484#define MMHUB_BASE__INST3_SEG3 0 485#define MMHUB_BASE__INST3_SEG4 0 486#define MMHUB_BASE__INST3_SEG5 0 487 488#define MMHUB_BASE__INST4_SEG0 0 489#define MMHUB_BASE__INST4_SEG1 0 490#define MMHUB_BASE__INST4_SEG2 0 491#define MMHUB_BASE__INST4_SEG3 0 492#define MMHUB_BASE__INST4_SEG4 0 493#define MMHUB_BASE__INST4_SEG5 0 494 495#define MMHUB_BASE__INST5_SEG0 0 496#define MMHUB_BASE__INST5_SEG1 0 497#define MMHUB_BASE__INST5_SEG2 0 498#define MMHUB_BASE__INST5_SEG3 0 499#define MMHUB_BASE__INST5_SEG4 0 500#define MMHUB_BASE__INST5_SEG5 0 501 502#define MP0_BASE__INST0_SEG0 0x00016000 503#define MP0_BASE__INST0_SEG1 0 504#define MP0_BASE__INST0_SEG2 0 505#define MP0_BASE__INST0_SEG3 0 506#define MP0_BASE__INST0_SEG4 0 507#define MP0_BASE__INST0_SEG5 0 508 509#define MP0_BASE__INST1_SEG0 0 510#define MP0_BASE__INST1_SEG1 0 511#define MP0_BASE__INST1_SEG2 0 512#define MP0_BASE__INST1_SEG3 0 513#define MP0_BASE__INST1_SEG4 0 514#define MP0_BASE__INST1_SEG5 0 515 516#define MP0_BASE__INST2_SEG0 0 517#define MP0_BASE__INST2_SEG1 0 518#define MP0_BASE__INST2_SEG2 0 519#define MP0_BASE__INST2_SEG3 0 520#define MP0_BASE__INST2_SEG4 0 521#define MP0_BASE__INST2_SEG5 0 522 523#define MP0_BASE__INST3_SEG0 0 524#define MP0_BASE__INST3_SEG1 0 525#define MP0_BASE__INST3_SEG2 0 526#define MP0_BASE__INST3_SEG3 0 527#define MP0_BASE__INST3_SEG4 0 528#define MP0_BASE__INST3_SEG5 0 529 530#define MP0_BASE__INST4_SEG0 0 531#define MP0_BASE__INST4_SEG1 0 532#define MP0_BASE__INST4_SEG2 0 533#define MP0_BASE__INST4_SEG3 0 534#define MP0_BASE__INST4_SEG4 0 535#define MP0_BASE__INST4_SEG5 0 536 537#define MP0_BASE__INST5_SEG0 0 538#define MP0_BASE__INST5_SEG1 0 539#define MP0_BASE__INST5_SEG2 0 540#define MP0_BASE__INST5_SEG3 0 541#define MP0_BASE__INST5_SEG4 0 542#define MP0_BASE__INST5_SEG5 0 543 544#define MP1_BASE__INST0_SEG0 0x00016000 545#define MP1_BASE__INST0_SEG1 0 546#define MP1_BASE__INST0_SEG2 0 547#define MP1_BASE__INST0_SEG3 0 548#define MP1_BASE__INST0_SEG4 0 549#define MP1_BASE__INST0_SEG5 0 550 551#define MP1_BASE__INST1_SEG0 0 552#define MP1_BASE__INST1_SEG1 0 553#define MP1_BASE__INST1_SEG2 0 554#define MP1_BASE__INST1_SEG3 0 555#define MP1_BASE__INST1_SEG4 0 556#define MP1_BASE__INST1_SEG5 0 557 558#define MP1_BASE__INST2_SEG0 0 559#define MP1_BASE__INST2_SEG1 0 560#define MP1_BASE__INST2_SEG2 0 561#define MP1_BASE__INST2_SEG3 0 562#define MP1_BASE__INST2_SEG4 0 563#define MP1_BASE__INST2_SEG5 0 564 565#define MP1_BASE__INST3_SEG0 0 566#define MP1_BASE__INST3_SEG1 0 567#define MP1_BASE__INST3_SEG2 0 568#define MP1_BASE__INST3_SEG3 0 569#define MP1_BASE__INST3_SEG4 0 570#define MP1_BASE__INST3_SEG5 0 571 572#define MP1_BASE__INST4_SEG0 0 573#define MP1_BASE__INST4_SEG1 0 574#define MP1_BASE__INST4_SEG2 0 575#define MP1_BASE__INST4_SEG3 0 576#define MP1_BASE__INST4_SEG4 0 577#define MP1_BASE__INST4_SEG5 0 578 579#define MP1_BASE__INST5_SEG0 0 580#define MP1_BASE__INST5_SEG1 0 581#define MP1_BASE__INST5_SEG2 0 582#define MP1_BASE__INST5_SEG3 0 583#define MP1_BASE__INST5_SEG4 0 584#define MP1_BASE__INST5_SEG5 0 585 586#define NBIO_BASE__INST0_SEG0 0x00000000 587#define NBIO_BASE__INST0_SEG1 0x00000014 588#define NBIO_BASE__INST0_SEG2 0x00000D20 589#define NBIO_BASE__INST0_SEG3 0x00010400 590#define NBIO_BASE__INST0_SEG4 0 591#define NBIO_BASE__INST0_SEG5 0 592 593#define NBIO_BASE__INST1_SEG0 0 594#define NBIO_BASE__INST1_SEG1 0 595#define NBIO_BASE__INST1_SEG2 0 596#define NBIO_BASE__INST1_SEG3 0 597#define NBIO_BASE__INST1_SEG4 0 598#define NBIO_BASE__INST1_SEG5 0 599 600#define NBIO_BASE__INST2_SEG0 0 601#define NBIO_BASE__INST2_SEG1 0 602#define NBIO_BASE__INST2_SEG2 0 603#define NBIO_BASE__INST2_SEG3 0 604#define NBIO_BASE__INST2_SEG4 0 605#define NBIO_BASE__INST2_SEG5 0 606 607#define NBIO_BASE__INST3_SEG0 0 608#define NBIO_BASE__INST3_SEG1 0 609#define NBIO_BASE__INST3_SEG2 0 610#define NBIO_BASE__INST3_SEG3 0 611#define NBIO_BASE__INST3_SEG4 0 612#define NBIO_BASE__INST3_SEG5 0 613 614#define NBIO_BASE__INST4_SEG0 0 615#define NBIO_BASE__INST4_SEG1 0 616#define NBIO_BASE__INST4_SEG2 0 617#define NBIO_BASE__INST4_SEG3 0 618#define NBIO_BASE__INST4_SEG4 0 619#define NBIO_BASE__INST4_SEG5 0 620 621#define NBIO_BASE__INST5_SEG0 0 622#define NBIO_BASE__INST5_SEG1 0 623#define NBIO_BASE__INST5_SEG2 0 624#define NBIO_BASE__INST5_SEG3 0 625#define NBIO_BASE__INST5_SEG4 0 626#define NBIO_BASE__INST5_SEG5 0 627 628#define OSSSYS_BASE__INST0_SEG0 0x000010A0 629#define OSSSYS_BASE__INST0_SEG1 0 630#define OSSSYS_BASE__INST0_SEG2 0 631#define OSSSYS_BASE__INST0_SEG3 0 632#define OSSSYS_BASE__INST0_SEG4 0 633#define OSSSYS_BASE__INST0_SEG5 0 634 635#define OSSSYS_BASE__INST1_SEG0 0 636#define OSSSYS_BASE__INST1_SEG1 0 637#define OSSSYS_BASE__INST1_SEG2 0 638#define OSSSYS_BASE__INST1_SEG3 0 639#define OSSSYS_BASE__INST1_SEG4 0 640#define OSSSYS_BASE__INST1_SEG5 0 641 642#define OSSSYS_BASE__INST2_SEG0 0 643#define OSSSYS_BASE__INST2_SEG1 0 644#define OSSSYS_BASE__INST2_SEG2 0 645#define OSSSYS_BASE__INST2_SEG3 0 646#define OSSSYS_BASE__INST2_SEG4 0 647#define OSSSYS_BASE__INST2_SEG5 0 648 649#define OSSSYS_BASE__INST3_SEG0 0 650#define OSSSYS_BASE__INST3_SEG1 0 651#define OSSSYS_BASE__INST3_SEG2 0 652#define OSSSYS_BASE__INST3_SEG3 0 653#define OSSSYS_BASE__INST3_SEG4 0 654#define OSSSYS_BASE__INST3_SEG5 0 655 656#define OSSSYS_BASE__INST4_SEG0 0 657#define OSSSYS_BASE__INST4_SEG1 0 658#define OSSSYS_BASE__INST4_SEG2 0 659#define OSSSYS_BASE__INST4_SEG3 0 660#define OSSSYS_BASE__INST4_SEG4 0 661#define OSSSYS_BASE__INST4_SEG5 0 662 663#define OSSSYS_BASE__INST5_SEG0 0 664#define OSSSYS_BASE__INST5_SEG1 0 665#define OSSSYS_BASE__INST5_SEG2 0 666#define OSSSYS_BASE__INST5_SEG3 0 667#define OSSSYS_BASE__INST5_SEG4 0 668#define OSSSYS_BASE__INST5_SEG5 0 669 670#define SDMA0_BASE__INST0_SEG0 0x00001260 671#define SDMA0_BASE__INST0_SEG1 0 672#define SDMA0_BASE__INST0_SEG2 0 673#define SDMA0_BASE__INST0_SEG3 0 674#define SDMA0_BASE__INST0_SEG4 0 675#define SDMA0_BASE__INST0_SEG5 0 676 677#define SDMA0_BASE__INST1_SEG0 0 678#define SDMA0_BASE__INST1_SEG1 0 679#define SDMA0_BASE__INST1_SEG2 0 680#define SDMA0_BASE__INST1_SEG3 0 681#define SDMA0_BASE__INST1_SEG4 0 682#define SDMA0_BASE__INST1_SEG5 0 683 684#define SDMA0_BASE__INST2_SEG0 0 685#define SDMA0_BASE__INST2_SEG1 0 686#define SDMA0_BASE__INST2_SEG2 0 687#define SDMA0_BASE__INST2_SEG3 0 688#define SDMA0_BASE__INST2_SEG4 0 689#define SDMA0_BASE__INST2_SEG5 0 690 691#define SDMA0_BASE__INST3_SEG0 0 692#define SDMA0_BASE__INST3_SEG1 0 693#define SDMA0_BASE__INST3_SEG2 0 694#define SDMA0_BASE__INST3_SEG3 0 695#define SDMA0_BASE__INST3_SEG4 0 696#define SDMA0_BASE__INST3_SEG5 0 697 698#define SDMA0_BASE__INST4_SEG0 0 699#define SDMA0_BASE__INST4_SEG1 0 700#define SDMA0_BASE__INST4_SEG2 0 701#define SDMA0_BASE__INST4_SEG3 0 702#define SDMA0_BASE__INST4_SEG4 0 703#define SDMA0_BASE__INST4_SEG5 0 704 705#define SDMA0_BASE__INST5_SEG0 0 706#define SDMA0_BASE__INST5_SEG1 0 707#define SDMA0_BASE__INST5_SEG2 0 708#define SDMA0_BASE__INST5_SEG3 0 709#define SDMA0_BASE__INST5_SEG4 0 710#define SDMA0_BASE__INST5_SEG5 0 711 712#define SDMA1_BASE__INST0_SEG0 0x00001860 713#define SDMA1_BASE__INST0_SEG1 0 714#define SDMA1_BASE__INST0_SEG2 0 715#define SDMA1_BASE__INST0_SEG3 0 716#define SDMA1_BASE__INST0_SEG4 0 717#define SDMA1_BASE__INST0_SEG5 0 718 719#define SDMA1_BASE__INST1_SEG0 0 720#define SDMA1_BASE__INST1_SEG1 0 721#define SDMA1_BASE__INST1_SEG2 0 722#define SDMA1_BASE__INST1_SEG3 0 723#define SDMA1_BASE__INST1_SEG4 0 724#define SDMA1_BASE__INST1_SEG5 0 725 726#define SDMA1_BASE__INST2_SEG0 0 727#define SDMA1_BASE__INST2_SEG1 0 728#define SDMA1_BASE__INST2_SEG2 0 729#define SDMA1_BASE__INST2_SEG3 0 730#define SDMA1_BASE__INST2_SEG4 0 731#define SDMA1_BASE__INST2_SEG5 0 732 733#define SDMA1_BASE__INST3_SEG0 0 734#define SDMA1_BASE__INST3_SEG1 0 735#define SDMA1_BASE__INST3_SEG2 0 736#define SDMA1_BASE__INST3_SEG3 0 737#define SDMA1_BASE__INST3_SEG4 0 738#define SDMA1_BASE__INST3_SEG5 0 739 740#define SDMA1_BASE__INST4_SEG0 0 741#define SDMA1_BASE__INST4_SEG1 0 742#define SDMA1_BASE__INST4_SEG2 0 743#define SDMA1_BASE__INST4_SEG3 0 744#define SDMA1_BASE__INST4_SEG4 0 745#define SDMA1_BASE__INST4_SEG5 0 746 747#define SDMA1_BASE__INST5_SEG0 0 748#define SDMA1_BASE__INST5_SEG1 0 749#define SDMA1_BASE__INST5_SEG2 0 750#define SDMA1_BASE__INST5_SEG3 0 751#define SDMA1_BASE__INST5_SEG4 0 752#define SDMA1_BASE__INST5_SEG5 0 753 754#define SMUIO_BASE__INST0_SEG0 0x00016800 755#define SMUIO_BASE__INST0_SEG1 0x00016A00 756#define SMUIO_BASE__INST0_SEG2 0 757#define SMUIO_BASE__INST0_SEG3 0 758#define SMUIO_BASE__INST0_SEG4 0 759#define SMUIO_BASE__INST0_SEG5 0 760 761#define SMUIO_BASE__INST1_SEG0 0 762#define SMUIO_BASE__INST1_SEG1 0 763#define SMUIO_BASE__INST1_SEG2 0 764#define SMUIO_BASE__INST1_SEG3 0 765#define SMUIO_BASE__INST1_SEG4 0 766#define SMUIO_BASE__INST1_SEG5 0 767 768#define SMUIO_BASE__INST2_SEG0 0 769#define SMUIO_BASE__INST2_SEG1 0 770#define SMUIO_BASE__INST2_SEG2 0 771#define SMUIO_BASE__INST2_SEG3 0 772#define SMUIO_BASE__INST2_SEG4 0 773#define SMUIO_BASE__INST2_SEG5 0 774 775#define SMUIO_BASE__INST3_SEG0 0 776#define SMUIO_BASE__INST3_SEG1 0 777#define SMUIO_BASE__INST3_SEG2 0 778#define SMUIO_BASE__INST3_SEG3 0 779#define SMUIO_BASE__INST3_SEG4 0 780#define SMUIO_BASE__INST3_SEG5 0 781 782#define SMUIO_BASE__INST4_SEG0 0 783#define SMUIO_BASE__INST4_SEG1 0 784#define SMUIO_BASE__INST4_SEG2 0 785#define SMUIO_BASE__INST4_SEG3 0 786#define SMUIO_BASE__INST4_SEG4 0 787#define SMUIO_BASE__INST4_SEG5 0 788 789#define SMUIO_BASE__INST5_SEG0 0 790#define SMUIO_BASE__INST5_SEG1 0 791#define SMUIO_BASE__INST5_SEG2 0 792#define SMUIO_BASE__INST5_SEG3 0 793#define SMUIO_BASE__INST5_SEG4 0 794#define SMUIO_BASE__INST5_SEG5 0 795 796#define THM_BASE__INST0_SEG0 0x00016600 797#define THM_BASE__INST0_SEG1 0 798#define THM_BASE__INST0_SEG2 0 799#define THM_BASE__INST0_SEG3 0 800#define THM_BASE__INST0_SEG4 0 801#define THM_BASE__INST0_SEG5 0 802 803#define THM_BASE__INST1_SEG0 0 804#define THM_BASE__INST1_SEG1 0 805#define THM_BASE__INST1_SEG2 0 806#define THM_BASE__INST1_SEG3 0 807#define THM_BASE__INST1_SEG4 0 808#define THM_BASE__INST1_SEG5 0 809 810#define THM_BASE__INST2_SEG0 0 811#define THM_BASE__INST2_SEG1 0 812#define THM_BASE__INST2_SEG2 0 813#define THM_BASE__INST2_SEG3 0 814#define THM_BASE__INST2_SEG4 0 815#define THM_BASE__INST2_SEG5 0 816 817#define THM_BASE__INST3_SEG0 0 818#define THM_BASE__INST3_SEG1 0 819#define THM_BASE__INST3_SEG2 0 820#define THM_BASE__INST3_SEG3 0 821#define THM_BASE__INST3_SEG4 0 822#define THM_BASE__INST3_SEG5 0 823 824#define THM_BASE__INST4_SEG0 0 825#define THM_BASE__INST4_SEG1 0 826#define THM_BASE__INST4_SEG2 0 827#define THM_BASE__INST4_SEG3 0 828#define THM_BASE__INST4_SEG4 0 829#define THM_BASE__INST4_SEG5 0 830 831#define THM_BASE__INST5_SEG0 0 832#define THM_BASE__INST5_SEG1 0 833#define THM_BASE__INST5_SEG2 0 834#define THM_BASE__INST5_SEG3 0 835#define THM_BASE__INST5_SEG4 0 836#define THM_BASE__INST5_SEG5 0 837 838#define UMC_BASE__INST0_SEG0 0x00014000 839#define UMC_BASE__INST0_SEG1 0 840#define UMC_BASE__INST0_SEG2 0 841#define UMC_BASE__INST0_SEG3 0 842#define UMC_BASE__INST0_SEG4 0 843#define UMC_BASE__INST0_SEG5 0 844 845#define UMC_BASE__INST1_SEG0 0 846#define UMC_BASE__INST1_SEG1 0 847#define UMC_BASE__INST1_SEG2 0 848#define UMC_BASE__INST1_SEG3 0 849#define UMC_BASE__INST1_SEG4 0 850#define UMC_BASE__INST1_SEG5 0 851 852#define UMC_BASE__INST2_SEG0 0 853#define UMC_BASE__INST2_SEG1 0 854#define UMC_BASE__INST2_SEG2 0 855#define UMC_BASE__INST2_SEG3 0 856#define UMC_BASE__INST2_SEG4 0 857#define UMC_BASE__INST2_SEG5 0 858 859#define UMC_BASE__INST3_SEG0 0 860#define UMC_BASE__INST3_SEG1 0 861#define UMC_BASE__INST3_SEG2 0 862#define UMC_BASE__INST3_SEG3 0 863#define UMC_BASE__INST3_SEG4 0 864#define UMC_BASE__INST3_SEG5 0 865 866#define UMC_BASE__INST4_SEG0 0 867#define UMC_BASE__INST4_SEG1 0 868#define UMC_BASE__INST4_SEG2 0 869#define UMC_BASE__INST4_SEG3 0 870#define UMC_BASE__INST4_SEG4 0 871#define UMC_BASE__INST4_SEG5 0 872 873#define UMC_BASE__INST5_SEG0 0 874#define UMC_BASE__INST5_SEG1 0 875#define UMC_BASE__INST5_SEG2 0 876#define UMC_BASE__INST5_SEG3 0 877#define UMC_BASE__INST5_SEG4 0 878#define UMC_BASE__INST5_SEG5 0 879 880#define UVD_BASE__INST0_SEG0 0x00007800 881#define UVD_BASE__INST0_SEG1 0x00007E00 882#define UVD_BASE__INST0_SEG2 0 883#define UVD_BASE__INST0_SEG3 0 884#define UVD_BASE__INST0_SEG4 0 885#define UVD_BASE__INST0_SEG5 0 886 887#define UVD_BASE__INST1_SEG0 0 888#define UVD_BASE__INST1_SEG1 0x00009000 889#define UVD_BASE__INST1_SEG2 0 890#define UVD_BASE__INST1_SEG3 0 891#define UVD_BASE__INST1_SEG4 0 892#define UVD_BASE__INST1_SEG5 0 893 894#define UVD_BASE__INST2_SEG0 0 895#define UVD_BASE__INST2_SEG1 0 896#define UVD_BASE__INST2_SEG2 0 897#define UVD_BASE__INST2_SEG3 0 898#define UVD_BASE__INST2_SEG4 0 899#define UVD_BASE__INST2_SEG5 0 900 901#define UVD_BASE__INST3_SEG0 0 902#define UVD_BASE__INST3_SEG1 0 903#define UVD_BASE__INST3_SEG2 0 904#define UVD_BASE__INST3_SEG3 0 905#define UVD_BASE__INST3_SEG4 0 906#define UVD_BASE__INST3_SEG5 0 907 908#define UVD_BASE__INST4_SEG0 0 909#define UVD_BASE__INST4_SEG1 0 910#define UVD_BASE__INST4_SEG2 0 911#define UVD_BASE__INST4_SEG3 0 912#define UVD_BASE__INST4_SEG4 0 913#define UVD_BASE__INST4_SEG5 0 914 915#define UVD_BASE__INST5_SEG0 0 916#define UVD_BASE__INST5_SEG1 0 917#define UVD_BASE__INST5_SEG2 0 918#define UVD_BASE__INST5_SEG3 0 919#define UVD_BASE__INST5_SEG4 0 920#define UVD_BASE__INST5_SEG5 0 921 922#define VCE_BASE__INST0_SEG0 0x00008800 923#define VCE_BASE__INST0_SEG1 0 924#define VCE_BASE__INST0_SEG2 0 925#define VCE_BASE__INST0_SEG3 0 926#define VCE_BASE__INST0_SEG4 0 927#define VCE_BASE__INST0_SEG5 0 928 929#define VCE_BASE__INST1_SEG0 0 930#define VCE_BASE__INST1_SEG1 0 931#define VCE_BASE__INST1_SEG2 0 932#define VCE_BASE__INST1_SEG3 0 933#define VCE_BASE__INST1_SEG4 0 934#define VCE_BASE__INST1_SEG5 0 935 936#define VCE_BASE__INST2_SEG0 0 937#define VCE_BASE__INST2_SEG1 0 938#define VCE_BASE__INST2_SEG2 0 939#define VCE_BASE__INST2_SEG3 0 940#define VCE_BASE__INST2_SEG4 0 941#define VCE_BASE__INST2_SEG5 0 942 943#define VCE_BASE__INST3_SEG0 0 944#define VCE_BASE__INST3_SEG1 0 945#define VCE_BASE__INST3_SEG2 0 946#define VCE_BASE__INST3_SEG3 0 947#define VCE_BASE__INST3_SEG4 0 948#define VCE_BASE__INST3_SEG5 0 949 950#define VCE_BASE__INST4_SEG0 0 951#define VCE_BASE__INST4_SEG1 0 952#define VCE_BASE__INST4_SEG2 0 953#define VCE_BASE__INST4_SEG3 0 954#define VCE_BASE__INST4_SEG4 0 955#define VCE_BASE__INST4_SEG5 0 956 957#define VCE_BASE__INST5_SEG0 0 958#define VCE_BASE__INST5_SEG1 0 959#define VCE_BASE__INST5_SEG2 0 960#define VCE_BASE__INST5_SEG3 0 961#define VCE_BASE__INST5_SEG4 0 962#define VCE_BASE__INST5_SEG5 0 963 964#define XDMA_BASE__INST0_SEG0 0x00003400 965#define XDMA_BASE__INST0_SEG1 0 966#define XDMA_BASE__INST0_SEG2 0 967#define XDMA_BASE__INST0_SEG3 0 968#define XDMA_BASE__INST0_SEG4 0 969#define XDMA_BASE__INST0_SEG5 0 970 971#define XDMA_BASE__INST1_SEG0 0 972#define XDMA_BASE__INST1_SEG1 0 973#define XDMA_BASE__INST1_SEG2 0 974#define XDMA_BASE__INST1_SEG3 0 975#define XDMA_BASE__INST1_SEG4 0 976#define XDMA_BASE__INST1_SEG5 0 977 978#define XDMA_BASE__INST2_SEG0 0 979#define XDMA_BASE__INST2_SEG1 0 980#define XDMA_BASE__INST2_SEG2 0 981#define XDMA_BASE__INST2_SEG3 0 982#define XDMA_BASE__INST2_SEG4 0 983#define XDMA_BASE__INST2_SEG5 0 984 985#define XDMA_BASE__INST3_SEG0 0 986#define XDMA_BASE__INST3_SEG1 0 987#define XDMA_BASE__INST3_SEG2 0 988#define XDMA_BASE__INST3_SEG3 0 989#define XDMA_BASE__INST3_SEG4 0 990#define XDMA_BASE__INST3_SEG5 0 991 992#define XDMA_BASE__INST4_SEG0 0 993#define XDMA_BASE__INST4_SEG1 0 994#define XDMA_BASE__INST4_SEG2 0 995#define XDMA_BASE__INST4_SEG3 0 996#define XDMA_BASE__INST4_SEG4 0 997#define XDMA_BASE__INST4_SEG5 0 998 999#define XDMA_BASE__INST5_SEG0 0 1000#define XDMA_BASE__INST5_SEG1 0 1001#define XDMA_BASE__INST5_SEG2 0 1002#define XDMA_BASE__INST5_SEG3 0 1003#define XDMA_BASE__INST5_SEG4 0 1004#define XDMA_BASE__INST5_SEG5 0 1005 1006#define RSMU_BASE__INST0_SEG0 0x00012000 1007#define RSMU_BASE__INST0_SEG1 0 1008#define RSMU_BASE__INST0_SEG2 0 1009#define RSMU_BASE__INST0_SEG3 0 1010#define RSMU_BASE__INST0_SEG4 0 1011#define RSMU_BASE__INST0_SEG5 0 1012 1013#define RSMU_BASE__INST1_SEG0 0 1014#define RSMU_BASE__INST1_SEG1 0 1015#define RSMU_BASE__INST1_SEG2 0 1016#define RSMU_BASE__INST1_SEG3 0 1017#define RSMU_BASE__INST1_SEG4 0 1018#define RSMU_BASE__INST1_SEG5 0 1019 1020#define RSMU_BASE__INST2_SEG0 0 1021#define RSMU_BASE__INST2_SEG1 0 1022#define RSMU_BASE__INST2_SEG2 0 1023#define RSMU_BASE__INST2_SEG3 0 1024#define RSMU_BASE__INST2_SEG4 0 1025#define RSMU_BASE__INST2_SEG5 0 1026 1027#define RSMU_BASE__INST3_SEG0 0 1028#define RSMU_BASE__INST3_SEG1 0 1029#define RSMU_BASE__INST3_SEG2 0 1030#define RSMU_BASE__INST3_SEG3 0 1031#define RSMU_BASE__INST3_SEG4 0 1032#define RSMU_BASE__INST3_SEG5 0 1033 1034#define RSMU_BASE__INST4_SEG0 0 1035#define RSMU_BASE__INST4_SEG1 0 1036#define RSMU_BASE__INST4_SEG2 0 1037#define RSMU_BASE__INST4_SEG3 0 1038#define RSMU_BASE__INST4_SEG4 0 1039#define RSMU_BASE__INST4_SEG5 0 1040 1041#define RSMU_BASE__INST5_SEG0 0 1042#define RSMU_BASE__INST5_SEG1 0 1043#define RSMU_BASE__INST5_SEG2 0 1044#define RSMU_BASE__INST5_SEG3 0 1045#define RSMU_BASE__INST5_SEG4 0 1046#define RSMU_BASE__INST5_SEG5 0 1047 1048#endif 1049 1050