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1456482b |
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21-Sep-2019 |
Yong Zhao <Yong.Zhao@amd.com> |
drm/amdgpu: Delete useless header file reference Those header file includes are not needed. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0c6b391d |
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15-Jul-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable Doorbell support for Renoir (v2) Add VCN range aperture to NBIO 7.0 v2: rebase (Alex) Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e02c80d6 |
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19-Feb-2019 |
Yong Zhao <Yong.Zhao@amd.com> |
Revert "drm/amdgpu: Delete user queue doorbell variables" This reverts commit 9006c6bd9059cb9807fa863bafc1d776222cb61b. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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828845b7 |
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13-Feb-2019 |
Yong Zhao <Yong.Zhao@amd.com> |
drm/amdgpu: Add first_non_cp and last_non_cp in amdgpu_doorbell_index They will be used to inform KFD the doorbell range not usable for CP. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c0d9271e |
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01-Feb-2019 |
Yong Zhao <Yong.Zhao@amd.com> |
drm/amdgpu: Delete user queue doorbell variables They are no longer used, so delete them to avoid confusion. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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fd485540 |
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17-Dec-2018 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Add per device sdma_doorbell_range field Different ASIC has different sdma doorbell range. Add a per device sdma_doorbell_range field and initialize it. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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898e0d9d |
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17-Dec-2018 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Use sdma_engine array Use sdma_engine[8] array instead of sdma_engine0~7 so it is easier to program. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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062f3807 |
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19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Vega10 doorbell index initialization v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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73b19174 |
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05-Jul-2018 |
Rex Zhu <rex.zhu@amd.com> |
drm/amdgpu: Add CLK IP base offset so we can read/write the registers in CLK domain through RREG32/WREG32_SOC15 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e6636ae1 |
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09-Apr-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: add MP1 and THM hw ip base reg offset Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1b59fb03 |
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09-Apr-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: add MP1 and THM hw ip base reg offset Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f797dd51 |
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15-Jan-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: include new ip and ip offset headers Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4522824c |
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27-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Dynamic initialize IP base offset The base offsets of the IP blocks may change across asics even though the relative register offsets are the same for an IP. Handle this dynamically. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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