1/* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _sienna_cichlid_ip_offset_HEADER 22#define _sienna_cichlid_ip_offset_HEADER 23 24#define MAX_INSTANCE 7 25#define MAX_SEGMENT 5 26 27 28struct IP_BASE_INSTANCE { 29 unsigned int segment[MAX_SEGMENT]; 30}; 31 32struct IP_BASE { 33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 34} __maybe_unused; 35 36 37static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, 38 { { 0, 0, 0, 0, 0 } }, 39 { { 0, 0, 0, 0, 0 } }, 40 { { 0, 0, 0, 0, 0 } }, 41 { { 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0 } } } }; 44static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, 45 { { 0x00016E00, 0x02401C00, 0, 0, 0 } }, 46 { { 0x00017000, 0x02402000, 0, 0, 0 } }, 47 { { 0x00017200, 0x02402400, 0, 0, 0 } }, 48 { { 0x0001B000, 0x0242D800, 0, 0, 0 } }, 49 { { 0x0001B200, 0x0242DC00, 0, 0, 0 } }, 50 { { 0x0001B400, 0x0242E000, 0, 0, 0 } } } }; 51static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0 } }, 55 { { 0, 0, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0 } } } }; 58static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0 } } } }; 65static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, 66 { { 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0 } } } }; 72static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, 73 { { 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0 } } } }; 79static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0 } } } }; 86static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } }, 87 { { 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0 } } } }; 93static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0 } }, 97 { { 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0 } } } }; 100static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0 } } } }; 107static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0 } } } }; 114static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, 115 { { 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0 } } } }; 121static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, 122 { { 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0 } } } }; 128static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, 129 { { 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0 } } } }; 135static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0 } } } }; 142static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, 143 { { 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0 } }, 146 { { 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0 } } } }; 149static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } }, 150 { { 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0 } } } }; 156static const struct IP_BASE SDMA1_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } }, 157 { { 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0 } }, 160 { { 0, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0 } } } }; 163static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, 164 { { 0, 0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0 } }, 167 { { 0, 0, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0 } }, 169 { { 0, 0, 0, 0, 0 } } } }; 170static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, 171 { { 0, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0 } }, 173 { { 0, 0, 0, 0, 0 } }, 174 { { 0, 0, 0, 0, 0 } }, 175 { { 0, 0, 0, 0, 0 } }, 176 { { 0, 0, 0, 0, 0 } } } }; 177static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0 } }, 178 { { 0x00054000, 0x02425C00, 0, 0, 0 } }, 179 { { 0x00094000, 0x02426000, 0, 0, 0 } }, 180 { { 0x000D4000, 0x02426400, 0, 0, 0 } }, 181 { { 0x00114000, 0x02426800, 0, 0, 0 } }, 182 { { 0x00154000, 0x02426C00, 0, 0, 0 } }, 183 { { 0x00194000, 0x02427000, 0, 0, 0 } } } }; 184static const struct IP_BASE USB0_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, 185 { { 0, 0, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0 } }, 188 { { 0, 0, 0, 0, 0 } }, 189 { { 0, 0, 0, 0, 0 } }, 190 { { 0, 0, 0, 0, 0 } } } }; 191static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, 192 { { 0x00007B00, 0x00012000, 0x02445000, 0, 0 } }, 193 { { 0, 0, 0, 0, 0 } }, 194 { { 0, 0, 0, 0, 0 } }, 195 { { 0, 0, 0, 0, 0 } }, 196 { { 0, 0, 0, 0, 0 } }, 197 { { 0, 0, 0, 0, 0 } } } }; 198 199 200#define ATHUB_BASE__INST0_SEG0 0x00000C00 201#define ATHUB_BASE__INST0_SEG1 0x02408C00 202#define ATHUB_BASE__INST0_SEG2 0 203#define ATHUB_BASE__INST0_SEG3 0 204#define ATHUB_BASE__INST0_SEG4 0 205 206#define ATHUB_BASE__INST1_SEG0 0 207#define ATHUB_BASE__INST1_SEG1 0 208#define ATHUB_BASE__INST1_SEG2 0 209#define ATHUB_BASE__INST1_SEG3 0 210#define ATHUB_BASE__INST1_SEG4 0 211 212#define ATHUB_BASE__INST2_SEG0 0 213#define ATHUB_BASE__INST2_SEG1 0 214#define ATHUB_BASE__INST2_SEG2 0 215#define ATHUB_BASE__INST2_SEG3 0 216#define ATHUB_BASE__INST2_SEG4 0 217 218#define ATHUB_BASE__INST3_SEG0 0 219#define ATHUB_BASE__INST3_SEG1 0 220#define ATHUB_BASE__INST3_SEG2 0 221#define ATHUB_BASE__INST3_SEG3 0 222#define ATHUB_BASE__INST3_SEG4 0 223 224#define ATHUB_BASE__INST4_SEG0 0 225#define ATHUB_BASE__INST4_SEG1 0 226#define ATHUB_BASE__INST4_SEG2 0 227#define ATHUB_BASE__INST4_SEG3 0 228#define ATHUB_BASE__INST4_SEG4 0 229 230#define ATHUB_BASE__INST5_SEG0 0 231#define ATHUB_BASE__INST5_SEG1 0 232#define ATHUB_BASE__INST5_SEG2 0 233#define ATHUB_BASE__INST5_SEG3 0 234#define ATHUB_BASE__INST5_SEG4 0 235 236#define ATHUB_BASE__INST6_SEG0 0 237#define ATHUB_BASE__INST6_SEG1 0 238#define ATHUB_BASE__INST6_SEG2 0 239#define ATHUB_BASE__INST6_SEG3 0 240#define ATHUB_BASE__INST6_SEG4 0 241 242#define CLK_BASE__INST0_SEG0 0x00016C00 243#define CLK_BASE__INST0_SEG1 0x02401800 244#define CLK_BASE__INST0_SEG2 0 245#define CLK_BASE__INST0_SEG3 0 246#define CLK_BASE__INST0_SEG4 0 247 248#define CLK_BASE__INST1_SEG0 0x00016E00 249#define CLK_BASE__INST1_SEG1 0x02401C00 250#define CLK_BASE__INST1_SEG2 0 251#define CLK_BASE__INST1_SEG3 0 252#define CLK_BASE__INST1_SEG4 0 253 254#define CLK_BASE__INST2_SEG0 0x00017000 255#define CLK_BASE__INST2_SEG1 0x02402000 256#define CLK_BASE__INST2_SEG2 0 257#define CLK_BASE__INST2_SEG3 0 258#define CLK_BASE__INST2_SEG4 0 259 260#define CLK_BASE__INST3_SEG0 0x00017200 261#define CLK_BASE__INST3_SEG1 0x02402400 262#define CLK_BASE__INST3_SEG2 0 263#define CLK_BASE__INST3_SEG3 0 264#define CLK_BASE__INST3_SEG4 0 265 266#define CLK_BASE__INST4_SEG0 0x0001B000 267#define CLK_BASE__INST4_SEG1 0x0242D800 268#define CLK_BASE__INST4_SEG2 0 269#define CLK_BASE__INST4_SEG3 0 270#define CLK_BASE__INST4_SEG4 0 271 272#define CLK_BASE__INST5_SEG0 0x0001B200 273#define CLK_BASE__INST5_SEG1 0x0242DC00 274#define CLK_BASE__INST5_SEG2 0 275#define CLK_BASE__INST5_SEG3 0 276#define CLK_BASE__INST5_SEG4 0 277 278#define CLK_BASE__INST6_SEG0 0x0001B400 279#define CLK_BASE__INST6_SEG1 0x0242E000 280#define CLK_BASE__INST6_SEG2 0 281#define CLK_BASE__INST6_SEG3 0 282#define CLK_BASE__INST6_SEG4 0 283 284#define DF_BASE__INST0_SEG0 0x00007000 285#define DF_BASE__INST0_SEG1 0x0240B800 286#define DF_BASE__INST0_SEG2 0 287#define DF_BASE__INST0_SEG3 0 288#define DF_BASE__INST0_SEG4 0 289 290#define DF_BASE__INST1_SEG0 0 291#define DF_BASE__INST1_SEG1 0 292#define DF_BASE__INST1_SEG2 0 293#define DF_BASE__INST1_SEG3 0 294#define DF_BASE__INST1_SEG4 0 295 296#define DF_BASE__INST2_SEG0 0 297#define DF_BASE__INST2_SEG1 0 298#define DF_BASE__INST2_SEG2 0 299#define DF_BASE__INST2_SEG3 0 300#define DF_BASE__INST2_SEG4 0 301 302#define DF_BASE__INST3_SEG0 0 303#define DF_BASE__INST3_SEG1 0 304#define DF_BASE__INST3_SEG2 0 305#define DF_BASE__INST3_SEG3 0 306#define DF_BASE__INST3_SEG4 0 307 308#define DF_BASE__INST4_SEG0 0 309#define DF_BASE__INST4_SEG1 0 310#define DF_BASE__INST4_SEG2 0 311#define DF_BASE__INST4_SEG3 0 312#define DF_BASE__INST4_SEG4 0 313 314#define DF_BASE__INST5_SEG0 0 315#define DF_BASE__INST5_SEG1 0 316#define DF_BASE__INST5_SEG2 0 317#define DF_BASE__INST5_SEG3 0 318#define DF_BASE__INST5_SEG4 0 319 320#define DF_BASE__INST6_SEG0 0 321#define DF_BASE__INST6_SEG1 0 322#define DF_BASE__INST6_SEG2 0 323#define DF_BASE__INST6_SEG3 0 324#define DF_BASE__INST6_SEG4 0 325 326#define DIO_BASE__INST0_SEG0 0x02404000 327#define DIO_BASE__INST0_SEG1 0 328#define DIO_BASE__INST0_SEG2 0 329#define DIO_BASE__INST0_SEG3 0 330#define DIO_BASE__INST0_SEG4 0 331 332#define DIO_BASE__INST1_SEG0 0 333#define DIO_BASE__INST1_SEG1 0 334#define DIO_BASE__INST1_SEG2 0 335#define DIO_BASE__INST1_SEG3 0 336#define DIO_BASE__INST1_SEG4 0 337 338#define DIO_BASE__INST2_SEG0 0 339#define DIO_BASE__INST2_SEG1 0 340#define DIO_BASE__INST2_SEG2 0 341#define DIO_BASE__INST2_SEG3 0 342#define DIO_BASE__INST2_SEG4 0 343 344#define DIO_BASE__INST3_SEG0 0 345#define DIO_BASE__INST3_SEG1 0 346#define DIO_BASE__INST3_SEG2 0 347#define DIO_BASE__INST3_SEG3 0 348#define DIO_BASE__INST3_SEG4 0 349 350#define DIO_BASE__INST4_SEG0 0 351#define DIO_BASE__INST4_SEG1 0 352#define DIO_BASE__INST4_SEG2 0 353#define DIO_BASE__INST4_SEG3 0 354#define DIO_BASE__INST4_SEG4 0 355 356#define DIO_BASE__INST5_SEG0 0 357#define DIO_BASE__INST5_SEG1 0 358#define DIO_BASE__INST5_SEG2 0 359#define DIO_BASE__INST5_SEG3 0 360#define DIO_BASE__INST5_SEG4 0 361 362#define DIO_BASE__INST6_SEG0 0 363#define DIO_BASE__INST6_SEG1 0 364#define DIO_BASE__INST6_SEG2 0 365#define DIO_BASE__INST6_SEG3 0 366#define DIO_BASE__INST6_SEG4 0 367 368#define DCN_BASE__INST0_SEG0 0x00000012 369#define DCN_BASE__INST0_SEG1 0x000000C0 370#define DCN_BASE__INST0_SEG2 0x000034C0 371#define DCN_BASE__INST0_SEG3 0x00009000 372#define DCN_BASE__INST0_SEG4 0x02403C00 373 374#define DCN_BASE__INST1_SEG0 0 375#define DCN_BASE__INST1_SEG1 0 376#define DCN_BASE__INST1_SEG2 0 377#define DCN_BASE__INST1_SEG3 0 378#define DCN_BASE__INST1_SEG4 0 379 380#define DCN_BASE__INST2_SEG0 0 381#define DCN_BASE__INST2_SEG1 0 382#define DCN_BASE__INST2_SEG2 0 383#define DCN_BASE__INST2_SEG3 0 384#define DCN_BASE__INST2_SEG4 0 385 386#define DCN_BASE__INST3_SEG0 0 387#define DCN_BASE__INST3_SEG1 0 388#define DCN_BASE__INST3_SEG2 0 389#define DCN_BASE__INST3_SEG3 0 390#define DCN_BASE__INST3_SEG4 0 391 392#define DCN_BASE__INST4_SEG0 0 393#define DCN_BASE__INST4_SEG1 0 394#define DCN_BASE__INST4_SEG2 0 395#define DCN_BASE__INST4_SEG3 0 396#define DCN_BASE__INST4_SEG4 0 397 398#define DCN_BASE__INST5_SEG0 0 399#define DCN_BASE__INST5_SEG1 0 400#define DCN_BASE__INST5_SEG2 0 401#define DCN_BASE__INST5_SEG3 0 402#define DCN_BASE__INST5_SEG4 0 403 404#define DCN_BASE__INST6_SEG0 0 405#define DCN_BASE__INST6_SEG1 0 406#define DCN_BASE__INST6_SEG2 0 407#define DCN_BASE__INST6_SEG3 0 408#define DCN_BASE__INST6_SEG4 0 409 410#define DPCS_BASE__INST0_SEG0 0x00000012 411#define DPCS_BASE__INST0_SEG1 0x000000C0 412#define DPCS_BASE__INST0_SEG2 0x000034C0 413#define DPCS_BASE__INST0_SEG3 0x00009000 414#define DPCS_BASE__INST0_SEG4 0x02403C00 415 416#define DPCS_BASE__INST1_SEG0 0 417#define DPCS_BASE__INST1_SEG1 0 418#define DPCS_BASE__INST1_SEG2 0 419#define DPCS_BASE__INST1_SEG3 0 420#define DPCS_BASE__INST1_SEG4 0 421 422#define DPCS_BASE__INST2_SEG0 0 423#define DPCS_BASE__INST2_SEG1 0 424#define DPCS_BASE__INST2_SEG2 0 425#define DPCS_BASE__INST2_SEG3 0 426#define DPCS_BASE__INST2_SEG4 0 427 428#define DPCS_BASE__INST3_SEG0 0 429#define DPCS_BASE__INST3_SEG1 0 430#define DPCS_BASE__INST3_SEG2 0 431#define DPCS_BASE__INST3_SEG3 0 432#define DPCS_BASE__INST3_SEG4 0 433 434#define DPCS_BASE__INST4_SEG0 0 435#define DPCS_BASE__INST4_SEG1 0 436#define DPCS_BASE__INST4_SEG2 0 437#define DPCS_BASE__INST4_SEG3 0 438#define DPCS_BASE__INST4_SEG4 0 439 440#define DPCS_BASE__INST5_SEG0 0 441#define DPCS_BASE__INST5_SEG1 0 442#define DPCS_BASE__INST5_SEG2 0 443#define DPCS_BASE__INST5_SEG3 0 444#define DPCS_BASE__INST5_SEG4 0 445 446#define DPCS_BASE__INST6_SEG0 0 447#define DPCS_BASE__INST6_SEG1 0 448#define DPCS_BASE__INST6_SEG2 0 449#define DPCS_BASE__INST6_SEG3 0 450#define DPCS_BASE__INST6_SEG4 0 451 452#define FUSE_BASE__INST0_SEG0 0x00017400 453#define FUSE_BASE__INST0_SEG1 0x02401400 454#define FUSE_BASE__INST0_SEG2 0 455#define FUSE_BASE__INST0_SEG3 0 456#define FUSE_BASE__INST0_SEG4 0 457 458#define FUSE_BASE__INST1_SEG0 0 459#define FUSE_BASE__INST1_SEG1 0 460#define FUSE_BASE__INST1_SEG2 0 461#define FUSE_BASE__INST1_SEG3 0 462#define FUSE_BASE__INST1_SEG4 0 463 464#define FUSE_BASE__INST2_SEG0 0 465#define FUSE_BASE__INST2_SEG1 0 466#define FUSE_BASE__INST2_SEG2 0 467#define FUSE_BASE__INST2_SEG3 0 468#define FUSE_BASE__INST2_SEG4 0 469 470#define FUSE_BASE__INST3_SEG0 0 471#define FUSE_BASE__INST3_SEG1 0 472#define FUSE_BASE__INST3_SEG2 0 473#define FUSE_BASE__INST3_SEG3 0 474#define FUSE_BASE__INST3_SEG4 0 475 476#define FUSE_BASE__INST4_SEG0 0 477#define FUSE_BASE__INST4_SEG1 0 478#define FUSE_BASE__INST4_SEG2 0 479#define FUSE_BASE__INST4_SEG3 0 480#define FUSE_BASE__INST4_SEG4 0 481 482#define FUSE_BASE__INST5_SEG0 0 483#define FUSE_BASE__INST5_SEG1 0 484#define FUSE_BASE__INST5_SEG2 0 485#define FUSE_BASE__INST5_SEG3 0 486#define FUSE_BASE__INST5_SEG4 0 487 488#define FUSE_BASE__INST6_SEG0 0 489#define FUSE_BASE__INST6_SEG1 0 490#define FUSE_BASE__INST6_SEG2 0 491#define FUSE_BASE__INST6_SEG3 0 492#define FUSE_BASE__INST6_SEG4 0 493 494#define GC_BASE__INST0_SEG0 0x00001260 495#define GC_BASE__INST0_SEG1 0x0000A000 496#define GC_BASE__INST0_SEG2 0x0001C000 497#define GC_BASE__INST0_SEG3 0x02402C00 498#define GC_BASE__INST0_SEG4 0 499 500#define GC_BASE__INST1_SEG0 0 501#define GC_BASE__INST1_SEG1 0 502#define GC_BASE__INST1_SEG2 0 503#define GC_BASE__INST1_SEG3 0 504#define GC_BASE__INST1_SEG4 0 505 506#define GC_BASE__INST2_SEG0 0 507#define GC_BASE__INST2_SEG1 0 508#define GC_BASE__INST2_SEG2 0 509#define GC_BASE__INST2_SEG3 0 510#define GC_BASE__INST2_SEG4 0 511 512#define GC_BASE__INST3_SEG0 0 513#define GC_BASE__INST3_SEG1 0 514#define GC_BASE__INST3_SEG2 0 515#define GC_BASE__INST3_SEG3 0 516#define GC_BASE__INST3_SEG4 0 517 518#define GC_BASE__INST4_SEG0 0 519#define GC_BASE__INST4_SEG1 0 520#define GC_BASE__INST4_SEG2 0 521#define GC_BASE__INST4_SEG3 0 522#define GC_BASE__INST4_SEG4 0 523 524#define GC_BASE__INST5_SEG0 0 525#define GC_BASE__INST5_SEG1 0 526#define GC_BASE__INST5_SEG2 0 527#define GC_BASE__INST5_SEG3 0 528#define GC_BASE__INST5_SEG4 0 529 530#define GC_BASE__INST6_SEG0 0 531#define GC_BASE__INST6_SEG1 0 532#define GC_BASE__INST6_SEG2 0 533#define GC_BASE__INST6_SEG3 0 534#define GC_BASE__INST6_SEG4 0 535 536#define HDA_BASE__INST0_SEG0 0x004C0000 537#define HDA_BASE__INST0_SEG1 0x02404800 538#define HDA_BASE__INST0_SEG2 0 539#define HDA_BASE__INST0_SEG3 0 540#define HDA_BASE__INST0_SEG4 0 541 542#define HDA_BASE__INST1_SEG0 0 543#define HDA_BASE__INST1_SEG1 0 544#define HDA_BASE__INST1_SEG2 0 545#define HDA_BASE__INST1_SEG3 0 546#define HDA_BASE__INST1_SEG4 0 547 548#define HDA_BASE__INST2_SEG0 0 549#define HDA_BASE__INST2_SEG1 0 550#define HDA_BASE__INST2_SEG2 0 551#define HDA_BASE__INST2_SEG3 0 552#define HDA_BASE__INST2_SEG4 0 553 554#define HDA_BASE__INST3_SEG0 0 555#define HDA_BASE__INST3_SEG1 0 556#define HDA_BASE__INST3_SEG2 0 557#define HDA_BASE__INST3_SEG3 0 558#define HDA_BASE__INST3_SEG4 0 559 560#define HDA_BASE__INST4_SEG0 0 561#define HDA_BASE__INST4_SEG1 0 562#define HDA_BASE__INST4_SEG2 0 563#define HDA_BASE__INST4_SEG3 0 564#define HDA_BASE__INST4_SEG4 0 565 566#define HDA_BASE__INST5_SEG0 0 567#define HDA_BASE__INST5_SEG1 0 568#define HDA_BASE__INST5_SEG2 0 569#define HDA_BASE__INST5_SEG3 0 570#define HDA_BASE__INST5_SEG4 0 571 572#define HDA_BASE__INST6_SEG0 0 573#define HDA_BASE__INST6_SEG1 0 574#define HDA_BASE__INST6_SEG2 0 575#define HDA_BASE__INST6_SEG3 0 576#define HDA_BASE__INST6_SEG4 0 577 578#define HDP_BASE__INST0_SEG0 0x00000F20 579#define HDP_BASE__INST0_SEG1 0x0240A400 580#define HDP_BASE__INST0_SEG2 0 581#define HDP_BASE__INST0_SEG3 0 582#define HDP_BASE__INST0_SEG4 0 583 584#define HDP_BASE__INST1_SEG0 0 585#define HDP_BASE__INST1_SEG1 0 586#define HDP_BASE__INST1_SEG2 0 587#define HDP_BASE__INST1_SEG3 0 588#define HDP_BASE__INST1_SEG4 0 589 590#define HDP_BASE__INST2_SEG0 0 591#define HDP_BASE__INST2_SEG1 0 592#define HDP_BASE__INST2_SEG2 0 593#define HDP_BASE__INST2_SEG3 0 594#define HDP_BASE__INST2_SEG4 0 595 596#define HDP_BASE__INST3_SEG0 0 597#define HDP_BASE__INST3_SEG1 0 598#define HDP_BASE__INST3_SEG2 0 599#define HDP_BASE__INST3_SEG3 0 600#define HDP_BASE__INST3_SEG4 0 601 602#define HDP_BASE__INST4_SEG0 0 603#define HDP_BASE__INST4_SEG1 0 604#define HDP_BASE__INST4_SEG2 0 605#define HDP_BASE__INST4_SEG3 0 606#define HDP_BASE__INST4_SEG4 0 607 608#define HDP_BASE__INST5_SEG0 0 609#define HDP_BASE__INST5_SEG1 0 610#define HDP_BASE__INST5_SEG2 0 611#define HDP_BASE__INST5_SEG3 0 612#define HDP_BASE__INST5_SEG4 0 613 614#define HDP_BASE__INST6_SEG0 0 615#define HDP_BASE__INST6_SEG1 0 616#define HDP_BASE__INST6_SEG2 0 617#define HDP_BASE__INST6_SEG3 0 618#define HDP_BASE__INST6_SEG4 0 619 620#define MMHUB_BASE__INST0_SEG0 0x0001A000 621#define MMHUB_BASE__INST0_SEG1 0x02408800 622#define MMHUB_BASE__INST0_SEG2 0 623#define MMHUB_BASE__INST0_SEG3 0 624#define MMHUB_BASE__INST0_SEG4 0 625 626#define MMHUB_BASE__INST1_SEG0 0 627#define MMHUB_BASE__INST1_SEG1 0 628#define MMHUB_BASE__INST1_SEG2 0 629#define MMHUB_BASE__INST1_SEG3 0 630#define MMHUB_BASE__INST1_SEG4 0 631 632#define MMHUB_BASE__INST2_SEG0 0 633#define MMHUB_BASE__INST2_SEG1 0 634#define MMHUB_BASE__INST2_SEG2 0 635#define MMHUB_BASE__INST2_SEG3 0 636#define MMHUB_BASE__INST2_SEG4 0 637 638#define MMHUB_BASE__INST3_SEG0 0 639#define MMHUB_BASE__INST3_SEG1 0 640#define MMHUB_BASE__INST3_SEG2 0 641#define MMHUB_BASE__INST3_SEG3 0 642#define MMHUB_BASE__INST3_SEG4 0 643 644#define MMHUB_BASE__INST4_SEG0 0 645#define MMHUB_BASE__INST4_SEG1 0 646#define MMHUB_BASE__INST4_SEG2 0 647#define MMHUB_BASE__INST4_SEG3 0 648#define MMHUB_BASE__INST4_SEG4 0 649 650#define MMHUB_BASE__INST5_SEG0 0 651#define MMHUB_BASE__INST5_SEG1 0 652#define MMHUB_BASE__INST5_SEG2 0 653#define MMHUB_BASE__INST5_SEG3 0 654#define MMHUB_BASE__INST5_SEG4 0 655 656#define MMHUB_BASE__INST6_SEG0 0 657#define MMHUB_BASE__INST6_SEG1 0 658#define MMHUB_BASE__INST6_SEG2 0 659#define MMHUB_BASE__INST6_SEG3 0 660#define MMHUB_BASE__INST6_SEG4 0 661 662#define MP0_BASE__INST0_SEG0 0x00016000 663#define MP0_BASE__INST0_SEG1 0x00DC0000 664#define MP0_BASE__INST0_SEG2 0x00E00000 665#define MP0_BASE__INST0_SEG3 0x00E40000 666#define MP0_BASE__INST0_SEG4 0x0243FC00 667 668#define MP0_BASE__INST1_SEG0 0 669#define MP0_BASE__INST1_SEG1 0 670#define MP0_BASE__INST1_SEG2 0 671#define MP0_BASE__INST1_SEG3 0 672#define MP0_BASE__INST1_SEG4 0 673 674#define MP0_BASE__INST2_SEG0 0 675#define MP0_BASE__INST2_SEG1 0 676#define MP0_BASE__INST2_SEG2 0 677#define MP0_BASE__INST2_SEG3 0 678#define MP0_BASE__INST2_SEG4 0 679 680#define MP0_BASE__INST3_SEG0 0 681#define MP0_BASE__INST3_SEG1 0 682#define MP0_BASE__INST3_SEG2 0 683#define MP0_BASE__INST3_SEG3 0 684#define MP0_BASE__INST3_SEG4 0 685 686#define MP0_BASE__INST4_SEG0 0 687#define MP0_BASE__INST4_SEG1 0 688#define MP0_BASE__INST4_SEG2 0 689#define MP0_BASE__INST4_SEG3 0 690#define MP0_BASE__INST4_SEG4 0 691 692#define MP0_BASE__INST5_SEG0 0 693#define MP0_BASE__INST5_SEG1 0 694#define MP0_BASE__INST5_SEG2 0 695#define MP0_BASE__INST5_SEG3 0 696#define MP0_BASE__INST5_SEG4 0 697 698#define MP0_BASE__INST6_SEG0 0 699#define MP0_BASE__INST6_SEG1 0 700#define MP0_BASE__INST6_SEG2 0 701#define MP0_BASE__INST6_SEG3 0 702#define MP0_BASE__INST6_SEG4 0 703 704#define MP1_BASE__INST0_SEG0 0x00016000 705#define MP1_BASE__INST0_SEG1 0x00DC0000 706#define MP1_BASE__INST0_SEG2 0x00E00000 707#define MP1_BASE__INST0_SEG3 0x00E40000 708#define MP1_BASE__INST0_SEG4 0x0243FC00 709 710#define MP1_BASE__INST1_SEG0 0 711#define MP1_BASE__INST1_SEG1 0 712#define MP1_BASE__INST1_SEG2 0 713#define MP1_BASE__INST1_SEG3 0 714#define MP1_BASE__INST1_SEG4 0 715 716#define MP1_BASE__INST2_SEG0 0 717#define MP1_BASE__INST2_SEG1 0 718#define MP1_BASE__INST2_SEG2 0 719#define MP1_BASE__INST2_SEG3 0 720#define MP1_BASE__INST2_SEG4 0 721 722#define MP1_BASE__INST3_SEG0 0 723#define MP1_BASE__INST3_SEG1 0 724#define MP1_BASE__INST3_SEG2 0 725#define MP1_BASE__INST3_SEG3 0 726#define MP1_BASE__INST3_SEG4 0 727 728#define MP1_BASE__INST4_SEG0 0 729#define MP1_BASE__INST4_SEG1 0 730#define MP1_BASE__INST4_SEG2 0 731#define MP1_BASE__INST4_SEG3 0 732#define MP1_BASE__INST4_SEG4 0 733 734#define MP1_BASE__INST5_SEG0 0 735#define MP1_BASE__INST5_SEG1 0 736#define MP1_BASE__INST5_SEG2 0 737#define MP1_BASE__INST5_SEG3 0 738#define MP1_BASE__INST5_SEG4 0 739 740#define MP1_BASE__INST6_SEG0 0 741#define MP1_BASE__INST6_SEG1 0 742#define MP1_BASE__INST6_SEG2 0 743#define MP1_BASE__INST6_SEG3 0 744#define MP1_BASE__INST6_SEG4 0 745 746#define NBIO_BASE__INST0_SEG0 0x00000000 747#define NBIO_BASE__INST0_SEG1 0x00000014 748#define NBIO_BASE__INST0_SEG2 0x00000D20 749#define NBIO_BASE__INST0_SEG3 0x00010400 750#define NBIO_BASE__INST0_SEG4 0x0241B000 751 752#define NBIO_BASE__INST1_SEG0 0 753#define NBIO_BASE__INST1_SEG1 0 754#define NBIO_BASE__INST1_SEG2 0 755#define NBIO_BASE__INST1_SEG3 0 756#define NBIO_BASE__INST1_SEG4 0 757 758#define NBIO_BASE__INST2_SEG0 0 759#define NBIO_BASE__INST2_SEG1 0 760#define NBIO_BASE__INST2_SEG2 0 761#define NBIO_BASE__INST2_SEG3 0 762#define NBIO_BASE__INST2_SEG4 0 763 764#define NBIO_BASE__INST3_SEG0 0 765#define NBIO_BASE__INST3_SEG1 0 766#define NBIO_BASE__INST3_SEG2 0 767#define NBIO_BASE__INST3_SEG3 0 768#define NBIO_BASE__INST3_SEG4 0 769 770#define NBIO_BASE__INST4_SEG0 0 771#define NBIO_BASE__INST4_SEG1 0 772#define NBIO_BASE__INST4_SEG2 0 773#define NBIO_BASE__INST4_SEG3 0 774#define NBIO_BASE__INST4_SEG4 0 775 776#define NBIO_BASE__INST5_SEG0 0 777#define NBIO_BASE__INST5_SEG1 0 778#define NBIO_BASE__INST5_SEG2 0 779#define NBIO_BASE__INST5_SEG3 0 780#define NBIO_BASE__INST5_SEG4 0 781 782#define NBIO_BASE__INST6_SEG0 0 783#define NBIO_BASE__INST6_SEG1 0 784#define NBIO_BASE__INST6_SEG2 0 785#define NBIO_BASE__INST6_SEG3 0 786#define NBIO_BASE__INST6_SEG4 0 787 788#define OSSSYS_BASE__INST0_SEG0 0x000010A0 789#define OSSSYS_BASE__INST0_SEG1 0x0240A000 790#define OSSSYS_BASE__INST0_SEG2 0 791#define OSSSYS_BASE__INST0_SEG3 0 792#define OSSSYS_BASE__INST0_SEG4 0 793 794#define OSSSYS_BASE__INST1_SEG0 0 795#define OSSSYS_BASE__INST1_SEG1 0 796#define OSSSYS_BASE__INST1_SEG2 0 797#define OSSSYS_BASE__INST1_SEG3 0 798#define OSSSYS_BASE__INST1_SEG4 0 799 800#define OSSSYS_BASE__INST2_SEG0 0 801#define OSSSYS_BASE__INST2_SEG1 0 802#define OSSSYS_BASE__INST2_SEG2 0 803#define OSSSYS_BASE__INST2_SEG3 0 804#define OSSSYS_BASE__INST2_SEG4 0 805 806#define OSSSYS_BASE__INST3_SEG0 0 807#define OSSSYS_BASE__INST3_SEG1 0 808#define OSSSYS_BASE__INST3_SEG2 0 809#define OSSSYS_BASE__INST3_SEG3 0 810#define OSSSYS_BASE__INST3_SEG4 0 811 812#define OSSSYS_BASE__INST4_SEG0 0 813#define OSSSYS_BASE__INST4_SEG1 0 814#define OSSSYS_BASE__INST4_SEG2 0 815#define OSSSYS_BASE__INST4_SEG3 0 816#define OSSSYS_BASE__INST4_SEG4 0 817 818#define OSSSYS_BASE__INST5_SEG0 0 819#define OSSSYS_BASE__INST5_SEG1 0 820#define OSSSYS_BASE__INST5_SEG2 0 821#define OSSSYS_BASE__INST5_SEG3 0 822#define OSSSYS_BASE__INST5_SEG4 0 823 824#define OSSSYS_BASE__INST6_SEG0 0 825#define OSSSYS_BASE__INST6_SEG1 0 826#define OSSSYS_BASE__INST6_SEG2 0 827#define OSSSYS_BASE__INST6_SEG3 0 828#define OSSSYS_BASE__INST6_SEG4 0 829 830#define PCIE0_BASE__INST0_SEG0 0x00000000 831#define PCIE0_BASE__INST0_SEG1 0x00000014 832#define PCIE0_BASE__INST0_SEG2 0x00000D20 833#define PCIE0_BASE__INST0_SEG3 0x00010400 834#define PCIE0_BASE__INST0_SEG4 0x0241B000 835 836#define PCIE0_BASE__INST1_SEG0 0 837#define PCIE0_BASE__INST1_SEG1 0 838#define PCIE0_BASE__INST1_SEG2 0 839#define PCIE0_BASE__INST1_SEG3 0 840#define PCIE0_BASE__INST1_SEG4 0 841 842#define PCIE0_BASE__INST2_SEG0 0 843#define PCIE0_BASE__INST2_SEG1 0 844#define PCIE0_BASE__INST2_SEG2 0 845#define PCIE0_BASE__INST2_SEG3 0 846#define PCIE0_BASE__INST2_SEG4 0 847 848#define PCIE0_BASE__INST3_SEG0 0 849#define PCIE0_BASE__INST3_SEG1 0 850#define PCIE0_BASE__INST3_SEG2 0 851#define PCIE0_BASE__INST3_SEG3 0 852#define PCIE0_BASE__INST3_SEG4 0 853 854#define PCIE0_BASE__INST4_SEG0 0 855#define PCIE0_BASE__INST4_SEG1 0 856#define PCIE0_BASE__INST4_SEG2 0 857#define PCIE0_BASE__INST4_SEG3 0 858#define PCIE0_BASE__INST4_SEG4 0 859 860#define PCIE0_BASE__INST5_SEG0 0 861#define PCIE0_BASE__INST5_SEG1 0 862#define PCIE0_BASE__INST5_SEG2 0 863#define PCIE0_BASE__INST5_SEG3 0 864#define PCIE0_BASE__INST5_SEG4 0 865 866#define PCIE0_BASE__INST6_SEG0 0 867#define PCIE0_BASE__INST6_SEG1 0 868#define PCIE0_BASE__INST6_SEG2 0 869#define PCIE0_BASE__INST6_SEG3 0 870#define PCIE0_BASE__INST6_SEG4 0 871 872#define SDMA0_BASE__INST0_SEG0 0x00001260 873#define SDMA0_BASE__INST0_SEG1 0x0000A000 874#define SDMA0_BASE__INST0_SEG2 0x0001C000 875#define SDMA0_BASE__INST0_SEG3 0x02402C00 876#define SDMA0_BASE__INST0_SEG4 0 877 878#define SDMA0_BASE__INST1_SEG0 0 879#define SDMA0_BASE__INST1_SEG1 0 880#define SDMA0_BASE__INST1_SEG2 0 881#define SDMA0_BASE__INST1_SEG3 0 882#define SDMA0_BASE__INST1_SEG4 0 883 884#define SDMA0_BASE__INST2_SEG0 0 885#define SDMA0_BASE__INST2_SEG1 0 886#define SDMA0_BASE__INST2_SEG2 0 887#define SDMA0_BASE__INST2_SEG3 0 888#define SDMA0_BASE__INST2_SEG4 0 889 890#define SDMA0_BASE__INST3_SEG0 0 891#define SDMA0_BASE__INST3_SEG1 0 892#define SDMA0_BASE__INST3_SEG2 0 893#define SDMA0_BASE__INST3_SEG3 0 894#define SDMA0_BASE__INST3_SEG4 0 895 896#define SDMA0_BASE__INST4_SEG0 0 897#define SDMA0_BASE__INST4_SEG1 0 898#define SDMA0_BASE__INST4_SEG2 0 899#define SDMA0_BASE__INST4_SEG3 0 900#define SDMA0_BASE__INST4_SEG4 0 901 902#define SDMA0_BASE__INST5_SEG0 0 903#define SDMA0_BASE__INST5_SEG1 0 904#define SDMA0_BASE__INST5_SEG2 0 905#define SDMA0_BASE__INST5_SEG3 0 906#define SDMA0_BASE__INST5_SEG4 0 907 908#define SDMA0_BASE__INST6_SEG0 0 909#define SDMA0_BASE__INST6_SEG1 0 910#define SDMA0_BASE__INST6_SEG2 0 911#define SDMA0_BASE__INST6_SEG3 0 912#define SDMA0_BASE__INST6_SEG4 0 913 914#define SDMA1_BASE__INST0_SEG0 0x00001260 915#define SDMA1_BASE__INST0_SEG1 0x0000A000 916#define SDMA1_BASE__INST0_SEG2 0x0001C000 917#define SDMA1_BASE__INST0_SEG3 0x02402C00 918#define SDMA1_BASE__INST0_SEG4 0 919 920#define SDMA1_BASE__INST1_SEG0 0 921#define SDMA1_BASE__INST1_SEG1 0 922#define SDMA1_BASE__INST1_SEG2 0 923#define SDMA1_BASE__INST1_SEG3 0 924#define SDMA1_BASE__INST1_SEG4 0 925 926#define SDMA1_BASE__INST2_SEG0 0 927#define SDMA1_BASE__INST2_SEG1 0 928#define SDMA1_BASE__INST2_SEG2 0 929#define SDMA1_BASE__INST2_SEG3 0 930#define SDMA1_BASE__INST2_SEG4 0 931 932#define SDMA1_BASE__INST3_SEG0 0 933#define SDMA1_BASE__INST3_SEG1 0 934#define SDMA1_BASE__INST3_SEG2 0 935#define SDMA1_BASE__INST3_SEG3 0 936#define SDMA1_BASE__INST3_SEG4 0 937 938#define SDMA1_BASE__INST4_SEG0 0 939#define SDMA1_BASE__INST4_SEG1 0 940#define SDMA1_BASE__INST4_SEG2 0 941#define SDMA1_BASE__INST4_SEG3 0 942#define SDMA1_BASE__INST4_SEG4 0 943 944#define SDMA1_BASE__INST5_SEG0 0 945#define SDMA1_BASE__INST5_SEG1 0 946#define SDMA1_BASE__INST5_SEG2 0 947#define SDMA1_BASE__INST5_SEG3 0 948#define SDMA1_BASE__INST5_SEG4 0 949 950#define SDMA1_BASE__INST6_SEG0 0 951#define SDMA1_BASE__INST6_SEG1 0 952#define SDMA1_BASE__INST6_SEG2 0 953#define SDMA1_BASE__INST6_SEG3 0 954#define SDMA1_BASE__INST6_SEG4 0 955 956#define SMUIO_BASE__INST0_SEG0 0x00016800 957#define SMUIO_BASE__INST0_SEG1 0x00016A00 958#define SMUIO_BASE__INST0_SEG2 0x00440000 959#define SMUIO_BASE__INST0_SEG3 0x02401000 960#define SMUIO_BASE__INST0_SEG4 0 961 962#define SMUIO_BASE__INST1_SEG0 0 963#define SMUIO_BASE__INST1_SEG1 0 964#define SMUIO_BASE__INST1_SEG2 0 965#define SMUIO_BASE__INST1_SEG3 0 966#define SMUIO_BASE__INST1_SEG4 0 967 968#define SMUIO_BASE__INST2_SEG0 0 969#define SMUIO_BASE__INST2_SEG1 0 970#define SMUIO_BASE__INST2_SEG2 0 971#define SMUIO_BASE__INST2_SEG3 0 972#define SMUIO_BASE__INST2_SEG4 0 973 974#define SMUIO_BASE__INST3_SEG0 0 975#define SMUIO_BASE__INST3_SEG1 0 976#define SMUIO_BASE__INST3_SEG2 0 977#define SMUIO_BASE__INST3_SEG3 0 978#define SMUIO_BASE__INST3_SEG4 0 979 980#define SMUIO_BASE__INST4_SEG0 0 981#define SMUIO_BASE__INST4_SEG1 0 982#define SMUIO_BASE__INST4_SEG2 0 983#define SMUIO_BASE__INST4_SEG3 0 984#define SMUIO_BASE__INST4_SEG4 0 985 986#define SMUIO_BASE__INST5_SEG0 0 987#define SMUIO_BASE__INST5_SEG1 0 988#define SMUIO_BASE__INST5_SEG2 0 989#define SMUIO_BASE__INST5_SEG3 0 990#define SMUIO_BASE__INST5_SEG4 0 991 992#define SMUIO_BASE__INST6_SEG0 0 993#define SMUIO_BASE__INST6_SEG1 0 994#define SMUIO_BASE__INST6_SEG2 0 995#define SMUIO_BASE__INST6_SEG3 0 996#define SMUIO_BASE__INST6_SEG4 0 997 998#define THM_BASE__INST0_SEG0 0x00016600 999#define THM_BASE__INST0_SEG1 0x02400C00 1000#define THM_BASE__INST0_SEG2 0 1001#define THM_BASE__INST0_SEG3 0 1002#define THM_BASE__INST0_SEG4 0 1003 1004#define THM_BASE__INST1_SEG0 0 1005#define THM_BASE__INST1_SEG1 0 1006#define THM_BASE__INST1_SEG2 0 1007#define THM_BASE__INST1_SEG3 0 1008#define THM_BASE__INST1_SEG4 0 1009 1010#define THM_BASE__INST2_SEG0 0 1011#define THM_BASE__INST2_SEG1 0 1012#define THM_BASE__INST2_SEG2 0 1013#define THM_BASE__INST2_SEG3 0 1014#define THM_BASE__INST2_SEG4 0 1015 1016#define THM_BASE__INST3_SEG0 0 1017#define THM_BASE__INST3_SEG1 0 1018#define THM_BASE__INST3_SEG2 0 1019#define THM_BASE__INST3_SEG3 0 1020#define THM_BASE__INST3_SEG4 0 1021 1022#define THM_BASE__INST4_SEG0 0 1023#define THM_BASE__INST4_SEG1 0 1024#define THM_BASE__INST4_SEG2 0 1025#define THM_BASE__INST4_SEG3 0 1026#define THM_BASE__INST4_SEG4 0 1027 1028#define THM_BASE__INST5_SEG0 0 1029#define THM_BASE__INST5_SEG1 0 1030#define THM_BASE__INST5_SEG2 0 1031#define THM_BASE__INST5_SEG3 0 1032#define THM_BASE__INST5_SEG4 0 1033 1034#define THM_BASE__INST6_SEG0 0 1035#define THM_BASE__INST6_SEG1 0 1036#define THM_BASE__INST6_SEG2 0 1037#define THM_BASE__INST6_SEG3 0 1038#define THM_BASE__INST6_SEG4 0 1039 1040#define UMC_BASE__INST0_SEG0 0x00014000 1041#define UMC_BASE__INST0_SEG1 0x02425800 1042#define UMC_BASE__INST0_SEG2 0 1043#define UMC_BASE__INST0_SEG3 0 1044#define UMC_BASE__INST0_SEG4 0 1045 1046#define UMC_BASE__INST1_SEG0 0x00054000 1047#define UMC_BASE__INST1_SEG1 0x02425C00 1048#define UMC_BASE__INST1_SEG2 0 1049#define UMC_BASE__INST1_SEG3 0 1050#define UMC_BASE__INST1_SEG4 0 1051 1052#define UMC_BASE__INST2_SEG0 0x00094000 1053#define UMC_BASE__INST2_SEG1 0x02426000 1054#define UMC_BASE__INST2_SEG2 0 1055#define UMC_BASE__INST2_SEG3 0 1056#define UMC_BASE__INST2_SEG4 0 1057 1058#define UMC_BASE__INST3_SEG0 0x000D4000 1059#define UMC_BASE__INST3_SEG1 0x02426400 1060#define UMC_BASE__INST3_SEG2 0 1061#define UMC_BASE__INST3_SEG3 0 1062#define UMC_BASE__INST3_SEG4 0 1063 1064#define UMC_BASE__INST4_SEG0 0x00114000 1065#define UMC_BASE__INST4_SEG1 0x02426800 1066#define UMC_BASE__INST4_SEG2 0 1067#define UMC_BASE__INST4_SEG3 0 1068#define UMC_BASE__INST4_SEG4 0 1069 1070#define UMC_BASE__INST5_SEG0 0x00154000 1071#define UMC_BASE__INST5_SEG1 0x02426C00 1072#define UMC_BASE__INST5_SEG2 0 1073#define UMC_BASE__INST5_SEG3 0 1074#define UMC_BASE__INST5_SEG4 0 1075 1076#define UMC_BASE__INST6_SEG0 0x00194000 1077#define UMC_BASE__INST6_SEG1 0x02427000 1078#define UMC_BASE__INST6_SEG2 0 1079#define UMC_BASE__INST6_SEG3 0 1080#define UMC_BASE__INST6_SEG4 0 1081 1082#define USB0_BASE__INST0_SEG0 0x0242A800 1083#define USB0_BASE__INST0_SEG1 0x05B00000 1084#define USB0_BASE__INST0_SEG2 0 1085#define USB0_BASE__INST0_SEG3 0 1086#define USB0_BASE__INST0_SEG4 0 1087 1088#define USB0_BASE__INST1_SEG0 0 1089#define USB0_BASE__INST1_SEG1 0 1090#define USB0_BASE__INST1_SEG2 0 1091#define USB0_BASE__INST1_SEG3 0 1092#define USB0_BASE__INST1_SEG4 0 1093 1094#define USB0_BASE__INST2_SEG0 0 1095#define USB0_BASE__INST2_SEG1 0 1096#define USB0_BASE__INST2_SEG2 0 1097#define USB0_BASE__INST2_SEG3 0 1098#define USB0_BASE__INST2_SEG4 0 1099 1100#define USB0_BASE__INST3_SEG0 0 1101#define USB0_BASE__INST3_SEG1 0 1102#define USB0_BASE__INST3_SEG2 0 1103#define USB0_BASE__INST3_SEG3 0 1104#define USB0_BASE__INST3_SEG4 0 1105 1106#define USB0_BASE__INST4_SEG0 0 1107#define USB0_BASE__INST4_SEG1 0 1108#define USB0_BASE__INST4_SEG2 0 1109#define USB0_BASE__INST4_SEG3 0 1110#define USB0_BASE__INST4_SEG4 0 1111 1112#define USB0_BASE__INST5_SEG0 0 1113#define USB0_BASE__INST5_SEG1 0 1114#define USB0_BASE__INST5_SEG2 0 1115#define USB0_BASE__INST5_SEG3 0 1116#define USB0_BASE__INST5_SEG4 0 1117 1118#define USB0_BASE__INST6_SEG0 0 1119#define USB0_BASE__INST6_SEG1 0 1120#define USB0_BASE__INST6_SEG2 0 1121#define USB0_BASE__INST6_SEG3 0 1122#define USB0_BASE__INST6_SEG4 0 1123 1124#define VCN_BASE__INST0_SEG0 0x00007800 1125#define VCN_BASE__INST0_SEG1 0x00007E00 1126#define VCN_BASE__INST0_SEG2 0x02403000 1127#define VCN_BASE__INST0_SEG3 0 1128#define VCN_BASE__INST0_SEG4 0 1129 1130#define VCN_BASE__INST1_SEG0 0x00007B00 1131#define VCN_BASE__INST1_SEG1 0x00012000 1132#define VCN_BASE__INST1_SEG2 0x02445000 1133#define VCN_BASE__INST1_SEG3 0 1134#define VCN_BASE__INST1_SEG4 0 1135 1136#define VCN_BASE__INST2_SEG0 0 1137#define VCN_BASE__INST2_SEG1 0 1138#define VCN_BASE__INST2_SEG2 0 1139#define VCN_BASE__INST2_SEG3 0 1140#define VCN_BASE__INST2_SEG4 0 1141 1142#define VCN_BASE__INST3_SEG0 0 1143#define VCN_BASE__INST3_SEG1 0 1144#define VCN_BASE__INST3_SEG2 0 1145#define VCN_BASE__INST3_SEG3 0 1146#define VCN_BASE__INST3_SEG4 0 1147 1148#define VCN_BASE__INST4_SEG0 0 1149#define VCN_BASE__INST4_SEG1 0 1150#define VCN_BASE__INST4_SEG2 0 1151#define VCN_BASE__INST4_SEG3 0 1152#define VCN_BASE__INST4_SEG4 0 1153 1154#define VCN_BASE__INST5_SEG0 0 1155#define VCN_BASE__INST5_SEG1 0 1156#define VCN_BASE__INST5_SEG2 0 1157#define VCN_BASE__INST5_SEG3 0 1158#define VCN_BASE__INST5_SEG4 0 1159 1160#define VCN_BASE__INST6_SEG0 0 1161#define VCN_BASE__INST6_SEG1 0 1162#define VCN_BASE__INST6_SEG2 0 1163#define VCN_BASE__INST6_SEG3 0 1164#define VCN_BASE__INST6_SEG4 0 1165 1166#endif 1167