/linux-master/drivers/gpu/drm/amd/display/dc/dsc/ |
H A D | Makefile | 29 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o macro 31 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
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H A D | dc_dsc.c | 35 /* default DSC policy target bitrate limit is 16bpp */ 38 /* default DSC policy enables DSC only when needed */ 63 if (!timing->flags.DSC) { 94 if (timing->flags.DSC) 203 dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__); 219 dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__); 279 dm_error("%s: DPCD DSC throughput mode not recognized.\n", __func__); 310 dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__); 406 if (dpcd_dsc_branch_decoder_caps == NULL) { // branch decoder DPCD DSC dat [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/link/ |
H A D | link_validation.c | 128 if (timing->flags.DSC && !timing->dsc_cfg.is_frl) 129 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */ 130 outputTiming.flags.DSC = 0;
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H A D | link_dpms.c | 748 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 774 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 792 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 809 /* Enable DSC hw block */ 836 /* Enable DSC in encoder */ 838 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 848 /* Enable DSC in OPTC */ 849 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 856 /* disable DSC in OPTC */ 861 /* disable DSC i [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/link/hwss/ |
H A D | link_hwss_hpo_dp.c | 99 stream->timing.flags.DSC,
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/linux-master/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl0073/ |
H A D | ctrl0073dp.h | 274 NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC; member in struct:NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS
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/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_mst_types.c | 233 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 242 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display 840 params[i].timing->flags.DSC = 1; 853 params[i].timing->flags.DSC = 0; 867 params[i].timing->flags.DSC, 1109 stream->timing.flags.DSC = 0; 1222 /* add a check for older MST DSC with no virtual DPCDs */ 1249 * check if cached virtual MST DSC caps are available and DSC is supported 1369 if (stream->timing.flags.DSC [all...] |
H A D | amdgpu_dm.c | 6014 stream->timing.flags.DSC = 0; 6073 stream->timing.flags.DSC = 1; 6088 stream->timing.flags.DSC = 1; 6112 /* Set DSC policy according to dsc_clock_en */ 6131 stream->timing.flags.DSC = 1; 6132 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 6150 stream->timing.flags.DSC = 1; 6151 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 6157 /* Overwrite the stream flag if DSC is enabled through debugfs */ 6159 stream->timing.flags.DSC [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_dio_stream_encoder.c | 239 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 383 /* Set DSC-related configuration. 384 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_dio_stream_encoder.c | 272 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 378 /* Set DSC-related configuration. 379 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_dio_stream_encoder.c | 271 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dmub_replay.c | 196 copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); 197 // WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
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H A D | dmub_psr.c | 379 copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); 382 * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) 383 * Note that PSRSU+DSC is still under development.
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_stream_encoder.c | 275 /* Set DSC-related configuration. 276 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 463 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
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/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_hw_types.h | 772 uint32_t DSC : 1; /* Use DSC with this timing */ member in struct:dc_crtc_timing_flags 822 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ 823 uint32_t num_slices_v; /* Number of DSC slices - vertical */ 824 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 825 bool block_pred_enable; /* DSC block prediction enable */ 826 uint32_t linebuf_depth; /* DSC line buffer depth */ 827 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ 828 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ 829 int32_t rc_buffer_size; /* DSC R [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
H A D | dcn314_hwseq.c | 88 /* Enable DSC hw block */ 112 /* Enable DSC in OPTC */ 113 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 119 /* disable DSC in OPTC */ 124 /* disable DSC block */ 184 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC); 186 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */ 190 /* disconnect DSC block from stream */
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_dccg.c | 555 * non-DSC 4:2:0 mode pixel rate/2 4 556 * DSC native 4:2:0 pixel rate/2 4 557 * DSC native 4:2:2 pixel rate/2 4 565 (params->timing->flags.DSC && params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
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/linux-master/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_stream.c | 781 stream->timing.flags.DSC,
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H A D | dc.c | 635 param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; 1757 /* block DSC for now, as VBIOS does not currently support DSC timings */ 1758 if (crtc_timing->flags.DSC) 2987 uint32_t old_dsc_enabled = stream->timing.flags.DSC; 2991 /* Use temporarry context for validating new DSC config */ 2996 stream->timing.flags.DSC = enable_dsc; 2999 stream->timing.flags.DSC = old_dsc_enabled; 3005 DC_ERROR("Failed to allocate new validate context for DSC change\n");
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/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_translation_helper.c | 619 out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC; 683 if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple) 695 if (in->timing.flags.DSC) {
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H A D | dml2_mall_phantom.c | 712 phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.c | 1331 /* Return old DSC to avoid the need for re-programming */ 1338 /* Find first free DSC */ 1370 /* Get a DSC if required and available */ 1429 /* Get a DSC if required and available */ 1430 if (result == DC_OK && dc_stream->timing.flags.DSC) 1539 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { 1665 /* Validate DSC config, dsc count validation is already done */ 1677 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
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/linux-master/drivers/gpu/drm/amd/display/dc/link/protocols/ |
H A D | link_dp_capability.c | 781 /* for DSC enabled case, we search for minimum lane count */ 934 /* enable edp link optimization for DSC eDP case */ 935 if (stream->timing.flags.DSC) { 945 tmp_timing.flags.DSC = 0; 1807 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */ 1836 DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index); 1845 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode 1855 /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA. 1856 * Clear FEC and DSC capabilities as a work around if that is not the case. 1861 DC_LOG_DSC("Clear DSC SUPPOR [all...] |
H A D | link_edp_panel_control.c | 353 if (!crtc_timing->flags.DSC)
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/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
H A D | dcn10_optc.c | 1603 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1606 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1609 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1617 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
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