1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28#include "dc_bios_types.h" 29#include "dcn30/dcn30_dio_stream_encoder.h" 30#include "dcn314_dio_stream_encoder.h" 31#include "reg_helper.h" 32#include "hw_shared.h" 33#include "link.h" 34#include "dpcd_defs.h" 35 36#define DC_LOGGER \ 37 enc1->base.ctx->logger 38 39#define REG(reg)\ 40 (enc1->regs->reg) 41 42#undef FN 43#define FN(reg_name, field_name) \ 44 enc1->se_shift->field_name, enc1->se_mask->field_name 45 46#define VBI_LINE_0 0 47#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 48 49#define CTX \ 50 enc1->base.ctx 51 52void enc314_reset_fifo(struct stream_encoder *enc, bool reset) 53{ 54 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 55 uint32_t reset_val = reset ? 1 : 0; 56 uint32_t is_symclk_on; 57 58 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); 59 REG_GET(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, &is_symclk_on); 60 61 if (is_symclk_on) 62 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); 63 else 64 udelay(10); 65} 66 67void enc314_enable_fifo(struct stream_encoder *enc) 68{ 69 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 70 71 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); 72 73 enc314_reset_fifo(enc, true); 74 enc314_reset_fifo(enc, false); 75 76 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); 77} 78 79void enc314_disable_fifo(struct stream_encoder *enc) 80{ 81 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 82 83 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); 84} 85 86void enc314_dp_set_odm_combine( 87 struct stream_encoder *enc, 88 bool odm_combine) 89{ 90 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 91 92 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine); 93} 94 95/* setup stream encoder in dvi mode */ 96void enc314_stream_encoder_dvi_set_stream_attribute( 97 struct stream_encoder *enc, 98 struct dc_crtc_timing *crtc_timing, 99 bool is_dual_link) 100{ 101 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 102 103 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 104 struct bp_encoder_control cntl = {0}; 105 106 cntl.action = ENCODER_CONTROL_SETUP; 107 cntl.engine_id = enc1->base.id; 108 cntl.signal = is_dual_link ? 109 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 110 cntl.enable_dp_audio = false; 111 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 112 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 113 114 if (enc1->base.bp->funcs->encoder_control( 115 enc1->base.bp, &cntl) != BP_RESULT_OK) 116 return; 117 118 } else { 119 120 //Set pattern for clock channel, default vlue 0x63 does not work 121 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); 122 123 //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup 124 125 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg 126 127 enc314_enable_fifo(enc); 128 } 129 130 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 131 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 132 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 133} 134 135/* setup stream encoder in hdmi mode */ 136void enc314_stream_encoder_hdmi_set_stream_attribute( 137 struct stream_encoder *enc, 138 struct dc_crtc_timing *crtc_timing, 139 int actual_pix_clk_khz, 140 bool enable_audio) 141{ 142 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 143 144 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 145 struct bp_encoder_control cntl = {0}; 146 147 cntl.action = ENCODER_CONTROL_SETUP; 148 cntl.engine_id = enc1->base.id; 149 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 150 cntl.enable_dp_audio = enable_audio; 151 cntl.pixel_clock = actual_pix_clk_khz; 152 cntl.lanes_number = LANE_COUNT_FOUR; 153 154 if (enc1->base.bp->funcs->encoder_control( 155 enc1->base.bp, &cntl) != BP_RESULT_OK) 156 return; 157 158 } else { 159 160 //Set pattern for clock channel, default vlue 0x63 does not work 161 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); 162 163 //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup 164 165 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg 166 167 enc314_enable_fifo(enc); 168 } 169 170 /* Configure pixel encoding */ 171 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 172 173 /* setup HDMI engine */ 174 REG_UPDATE_6(HDMI_CONTROL, 175 HDMI_PACKET_GEN_VERSION, 1, 176 HDMI_KEEPOUT_MODE, 1, 177 HDMI_DEEP_COLOR_ENABLE, 0, 178 HDMI_DATA_SCRAMBLE_EN, 0, 179 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, 180 HDMI_CLOCK_CHANNEL_RATE, 0); 181 182 /* Configure color depth */ 183 switch (crtc_timing->display_color_depth) { 184 case COLOR_DEPTH_888: 185 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 186 break; 187 case COLOR_DEPTH_101010: 188 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 189 REG_UPDATE_2(HDMI_CONTROL, 190 HDMI_DEEP_COLOR_DEPTH, 1, 191 HDMI_DEEP_COLOR_ENABLE, 0); 192 } else { 193 REG_UPDATE_2(HDMI_CONTROL, 194 HDMI_DEEP_COLOR_DEPTH, 1, 195 HDMI_DEEP_COLOR_ENABLE, 1); 196 } 197 break; 198 case COLOR_DEPTH_121212: 199 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 200 REG_UPDATE_2(HDMI_CONTROL, 201 HDMI_DEEP_COLOR_DEPTH, 2, 202 HDMI_DEEP_COLOR_ENABLE, 0); 203 } else { 204 REG_UPDATE_2(HDMI_CONTROL, 205 HDMI_DEEP_COLOR_DEPTH, 2, 206 HDMI_DEEP_COLOR_ENABLE, 1); 207 } 208 break; 209 case COLOR_DEPTH_161616: 210 REG_UPDATE_2(HDMI_CONTROL, 211 HDMI_DEEP_COLOR_DEPTH, 3, 212 HDMI_DEEP_COLOR_ENABLE, 1); 213 break; 214 default: 215 break; 216 } 217 218 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 219 /* enable HDMI data scrambler 220 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 221 * Clock channel frequency is 1/4 of character rate. 222 */ 223 REG_UPDATE_2(HDMI_CONTROL, 224 HDMI_DATA_SCRAMBLE_EN, 1, 225 HDMI_CLOCK_CHANNEL_RATE, 1); 226 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 227 228 /* TODO: New feature for DCE11, still need to implement */ 229 230 /* enable HDMI data scrambler 231 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 232 * Clock channel frequency is the same 233 * as character rate 234 */ 235 REG_UPDATE_2(HDMI_CONTROL, 236 HDMI_DATA_SCRAMBLE_EN, 1, 237 HDMI_CLOCK_CHANNEL_RATE, 0); 238 } 239 240 241 /* Enable transmission of General Control packet on every frame */ 242 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 243 HDMI_GC_CONT, 1, 244 HDMI_GC_SEND, 1, 245 HDMI_NULL_SEND, 1); 246 247 /* Disable Audio Content Protection packet transmission */ 248 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); 249 250 /* following belongs to audio */ 251 /* Enable Audio InfoFrame packet transmission. */ 252 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 253 254 /* update double-buffered AUDIO_INFO registers immediately */ 255 ASSERT(enc->afmt); 256 enc->afmt->funcs->audio_info_immediate_update(enc->afmt); 257 258 /* Select line number on which to send Audio InfoFrame packets */ 259 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 260 VBI_LINE_0 + 2); 261 262 /* set HDMI GC AVMUTE */ 263 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 264} 265 266 267 268static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 269{ 270 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 271 272 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 273 && !timing->dsc_cfg.ycbcr422_simple); 274 return two_pix; 275} 276 277void enc314_stream_encoder_dp_blank( 278 struct dc_link *link, 279 struct stream_encoder *enc) 280{ 281 enc1_stream_encoder_dp_blank(link, enc); 282 283 /* Disable FIFO after the DP vid stream is disabled to avoid corruption. */ 284 if (enc->ctx->dc->debug.dig_fifo_off_in_blank) 285 enc314_disable_fifo(enc); 286} 287 288void enc314_stream_encoder_dp_unblank( 289 struct dc_link *link, 290 struct stream_encoder *enc, 291 const struct encoder_unblank_param *param) 292{ 293 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 294 295 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 296 uint32_t n_vid = 0x8000; 297 uint32_t m_vid; 298 uint32_t n_multiply = 0; 299 uint32_t pix_per_cycle = 0; 300 uint64_t m_vid_l = n_vid; 301 302 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ 303 if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { 304 /*this logic should be the same in get_pixel_clock_parameters() */ 305 n_multiply = 1; 306 pix_per_cycle = 1; 307 } 308 /* M / N = Fstream / Flink 309 * m_vid / n_vid = pixel rate / link rate 310 */ 311 312 m_vid_l *= param->timing.pix_clk_100hz / 10; 313 m_vid_l = div_u64(m_vid_l, 314 param->link_settings.link_rate 315 * LINK_RATE_REF_FREQ_IN_KHZ); 316 317 m_vid = (uint32_t) m_vid_l; 318 319 /* enable auto measurement */ 320 321 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 322 323 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 324 * therefore program initial value for Mvid and Nvid 325 */ 326 327 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 328 329 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 330 331 REG_UPDATE_2(DP_VID_TIMING, 332 DP_VID_M_N_GEN_EN, 1, 333 DP_VID_N_MUL, n_multiply); 334 335 REG_UPDATE(DP_PIXEL_FORMAT, 336 DP_PIXEL_PER_CYCLE_PROCESSING_MODE, 337 pix_per_cycle); 338 } 339 340 /* make sure stream is disabled before resetting steer fifo */ 341 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); 342 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); 343 344 /* DIG_START is removed from the register spec */ 345 346 /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen 347 * that it overflows during mode transition, and sometimes doesn't recover. 348 */ 349 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); 350 udelay(10); 351 352 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 353 354 /* wait 100us for DIG/DP logic to prime 355 * (i.e. a few video lines) 356 */ 357 udelay(100); 358 359 /* the hardware would start sending video at the start of the next DP 360 * frame (i.e. rising edge of the vblank). 361 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 362 * register has no effect on enable transition! HW always guarantees 363 * VID_STREAM enable at start of next frame, and this is not 364 * programmable 365 */ 366 367 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 368 369 /* 370 * DIG Resync FIFO now needs to be explicitly enabled. 371 * This should come after DP_VID_STREAM_ENABLE per HW docs. 372 */ 373 enc314_enable_fifo(enc); 374 375 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); 376} 377 378/* Set DSC-related configuration. 379 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 380 * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 381 * dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN32 382 */ 383void enc314_dp_set_dsc_config(struct stream_encoder *enc, 384 enum optc_dsc_mode dsc_mode, 385 uint32_t dsc_bytes_per_pixel, 386 uint32_t dsc_slice_width) 387{ 388 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 389 390 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); 391} 392 393/* this function read dsc related register fields to be logged later in dcn10_log_hw_state 394 * into a dcn_dsc_state struct. 395 */ 396void enc314_read_state(struct stream_encoder *enc, struct enc_state *s) 397{ 398 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 399 400 //if dsc is enabled, continue to read 401 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); 402 if (s->dsc_mode) { 403 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num); 404 405 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); 406 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); 407 408 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable); 409 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); 410 } 411} 412 413void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) 414{ 415 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 416 417 // The naming of this field is confusing, what it means is the output mode of otg, which 418 // is the input mode of the dig 419 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0); 420} 421 422 423static const struct stream_encoder_funcs dcn314_str_enc_funcs = { 424 .dp_set_odm_combine = 425 enc314_dp_set_odm_combine, 426 .dp_set_stream_attribute = 427 enc2_stream_encoder_dp_set_stream_attribute, 428 .hdmi_set_stream_attribute = 429 enc314_stream_encoder_hdmi_set_stream_attribute, 430 .dvi_set_stream_attribute = 431 enc314_stream_encoder_dvi_set_stream_attribute, 432 .set_throttled_vcp_size = 433 enc1_stream_encoder_set_throttled_vcp_size, 434 .update_hdmi_info_packets = 435 enc3_stream_encoder_update_hdmi_info_packets, 436 .stop_hdmi_info_packets = 437 enc3_stream_encoder_stop_hdmi_info_packets, 438 .update_dp_info_packets_sdp_line_num = 439 enc3_stream_encoder_update_dp_info_packets_sdp_line_num, 440 .update_dp_info_packets = 441 enc3_stream_encoder_update_dp_info_packets, 442 .stop_dp_info_packets = 443 enc1_stream_encoder_stop_dp_info_packets, 444 .dp_blank = 445 enc314_stream_encoder_dp_blank, 446 .dp_unblank = 447 enc314_stream_encoder_dp_unblank, 448 .audio_mute_control = enc3_audio_mute_control, 449 450 .dp_audio_setup = enc3_se_dp_audio_setup, 451 .dp_audio_enable = enc3_se_dp_audio_enable, 452 .dp_audio_disable = enc1_se_dp_audio_disable, 453 454 .hdmi_audio_setup = enc3_se_hdmi_audio_setup, 455 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 456 .setup_stereo_sync = enc1_setup_stereo_sync, 457 .set_avmute = enc1_stream_encoder_set_avmute, 458 .dig_connect_to_otg = enc1_dig_connect_to_otg, 459 .dig_source_otg = enc1_dig_source_otg, 460 461 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, 462 463 .enc_read_state = enc314_read_state, 464 .dp_set_dsc_config = enc314_dp_set_dsc_config, 465 .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, 466 .set_dynamic_metadata = enc2_set_dynamic_metadata, 467 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, 468 469 .enable_fifo = enc314_enable_fifo, 470 .disable_fifo = enc314_disable_fifo, 471 .set_input_mode = enc314_set_dig_input_mode, 472}; 473 474void dcn314_dio_stream_encoder_construct( 475 struct dcn10_stream_encoder *enc1, 476 struct dc_context *ctx, 477 struct dc_bios *bp, 478 enum engine_id eng_id, 479 struct vpg *vpg, 480 struct afmt *afmt, 481 const struct dcn10_stream_enc_registers *regs, 482 const struct dcn10_stream_encoder_shift *se_shift, 483 const struct dcn10_stream_encoder_mask *se_mask) 484{ 485 enc1->base.funcs = &dcn314_str_enc_funcs; 486 enc1->base.ctx = ctx; 487 enc1->base.id = eng_id; 488 enc1->base.bp = bp; 489 enc1->base.vpg = vpg; 490 enc1->base.afmt = afmt; 491 enc1->regs = regs; 492 enc1->se_shift = se_shift; 493 enc1->se_mask = se_mask; 494 enc1->base.stream_enc_inst = vpg->inst; 495} 496 497