1/* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include <drm/display/drm_dp_helper.h> 27#include <drm/display/drm_dp_mst_helper.h> 28#include <drm/drm_atomic.h> 29#include <drm/drm_atomic_helper.h> 30#include <drm/drm_fixed.h> 31#include <drm/drm_edid.h> 32#include "dm_services.h" 33#include "amdgpu.h" 34#include "amdgpu_dm.h" 35#include "amdgpu_dm_mst_types.h" 36#include "amdgpu_dm_hdcp.h" 37 38#include "dc.h" 39#include "dm_helpers.h" 40 41#include "ddc_service_types.h" 42#include "dpcd_defs.h" 43 44#include "dmub_cmd.h" 45#if defined(CONFIG_DEBUG_FS) 46#include "amdgpu_dm_debugfs.h" 47#endif 48 49#include "dc/resource/dcn20/dcn20_resource.h" 50 51#define PEAK_FACTOR_X1000 1006 52 53static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 54 struct drm_dp_aux_msg *msg) 55{ 56 ssize_t result = 0; 57 struct aux_payload payload; 58 enum aux_return_code_type operation_result; 59 struct amdgpu_device *adev; 60 struct ddc_service *ddc; 61 62 if (WARN_ON(msg->size > 16)) 63 return -E2BIG; 64 65 payload.address = msg->address; 66 payload.data = msg->buffer; 67 payload.length = msg->size; 68 payload.reply = &msg->reply; 69 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0; 70 payload.write = (msg->request & DP_AUX_I2C_READ) == 0; 71 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0; 72 payload.write_status_update = 73 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0; 74 payload.defer_delay = 0; 75 76 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload, 77 &operation_result); 78 79 /* 80 * w/a on certain intel platform where hpd is unexpected to pull low during 81 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON 82 * aux transaction is succuess in such case, therefore bypass the error 83 */ 84 ddc = TO_DM_AUX(aux)->ddc_service; 85 adev = ddc->ctx->driver_context; 86 if (adev->dm.aux_hpd_discon_quirk) { 87 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE && 88 operation_result == AUX_RET_ERROR_HPD_DISCON) { 89 result = 0; 90 operation_result = AUX_RET_SUCCESS; 91 } 92 } 93 94 if (payload.write && result >= 0) 95 result = msg->size; 96 97 if (result < 0) 98 switch (operation_result) { 99 case AUX_RET_SUCCESS: 100 break; 101 case AUX_RET_ERROR_HPD_DISCON: 102 case AUX_RET_ERROR_UNKNOWN: 103 case AUX_RET_ERROR_INVALID_OPERATION: 104 case AUX_RET_ERROR_PROTOCOL_ERROR: 105 result = -EIO; 106 break; 107 case AUX_RET_ERROR_INVALID_REPLY: 108 case AUX_RET_ERROR_ENGINE_ACQUIRE: 109 result = -EBUSY; 110 break; 111 case AUX_RET_ERROR_TIMEOUT: 112 result = -ETIMEDOUT; 113 break; 114 } 115 116 return result; 117} 118 119static void 120dm_dp_mst_connector_destroy(struct drm_connector *connector) 121{ 122 struct amdgpu_dm_connector *aconnector = 123 to_amdgpu_dm_connector(connector); 124 125 if (aconnector->dc_sink) { 126 dc_link_remove_remote_sink(aconnector->dc_link, 127 aconnector->dc_sink); 128 dc_sink_release(aconnector->dc_sink); 129 } 130 131 kfree(aconnector->edid); 132 133 drm_connector_cleanup(connector); 134 drm_dp_mst_put_port_malloc(aconnector->mst_output_port); 135 kfree(aconnector); 136} 137 138static int 139amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) 140{ 141 struct amdgpu_dm_connector *amdgpu_dm_connector = 142 to_amdgpu_dm_connector(connector); 143 int r; 144 145 r = drm_dp_mst_connector_late_register(connector, 146 amdgpu_dm_connector->mst_output_port); 147 if (r < 0) 148 return r; 149 150#if defined(CONFIG_DEBUG_FS) 151 connector_debugfs_init(amdgpu_dm_connector); 152#endif 153 154 return 0; 155} 156 157static void 158amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) 159{ 160 struct amdgpu_dm_connector *aconnector = 161 to_amdgpu_dm_connector(connector); 162 struct drm_dp_mst_port *port = aconnector->mst_output_port; 163 struct amdgpu_dm_connector *root = aconnector->mst_root; 164 struct dc_link *dc_link = aconnector->dc_link; 165 struct dc_sink *dc_sink = aconnector->dc_sink; 166 167 drm_dp_mst_connector_early_unregister(connector, port); 168 169 /* 170 * Release dc_sink for connector which its attached port is 171 * no longer in the mst topology 172 */ 173 drm_modeset_lock(&root->mst_mgr.base.lock, NULL); 174 if (dc_sink) { 175 if (dc_link->sink_count) 176 dc_link_remove_remote_sink(dc_link, dc_sink); 177 178 drm_dbg_dp(connector->dev, 179 "DM_MST: remove remote sink 0x%p, %d remaining\n", 180 dc_sink, dc_link->sink_count); 181 182 dc_sink_release(dc_sink); 183 aconnector->dc_sink = NULL; 184 aconnector->edid = NULL; 185 } 186 187 aconnector->mst_status = MST_STATUS_DEFAULT; 188 drm_modeset_unlock(&root->mst_mgr.base.lock); 189} 190 191static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { 192 .fill_modes = drm_helper_probe_single_connector_modes, 193 .destroy = dm_dp_mst_connector_destroy, 194 .reset = amdgpu_dm_connector_funcs_reset, 195 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 196 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 197 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 198 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 199 .late_register = amdgpu_dm_mst_connector_late_register, 200 .early_unregister = amdgpu_dm_mst_connector_early_unregister, 201}; 202 203bool needs_dsc_aux_workaround(struct dc_link *link) 204{ 205 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 206 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) && 207 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2) 208 return true; 209 210 return false; 211} 212 213static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port) 214{ 215 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F 216 217 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) { 218 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 219 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) { 220 DRM_INFO("Synaptics Cascaded MST hub\n"); 221 return true; 222 } 223 } 224 225 return false; 226} 227 228static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) 229{ 230 struct dc_sink *dc_sink = aconnector->dc_sink; 231 struct drm_dp_mst_port *port = aconnector->mst_output_port; 232 u8 dsc_caps[16] = { 0 }; 233 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 234 u8 *dsc_branch_dec_caps = NULL; 235 236 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); 237 238 /* 239 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs 240 * because it only check the dsc/fec caps of the "port variable" and not the dock 241 * 242 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display 243 * 244 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux 245 * 246 */ 247 if (!aconnector->dsc_aux && !port->parent->port_parent && 248 needs_dsc_aux_workaround(aconnector->dc_link)) 249 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux; 250 251 /* synaptics cascaded MST hub case */ 252 if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port)) 253 aconnector->dsc_aux = port->mgr->aux; 254 255 if (!aconnector->dsc_aux) 256 return false; 257 258 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) 259 return false; 260 261 if (drm_dp_dpcd_read(aconnector->dsc_aux, 262 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3) 263 dsc_branch_dec_caps = dsc_branch_dec_caps_raw; 264 265 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 266 dsc_caps, dsc_branch_dec_caps, 267 &dc_sink->dsc_caps.dsc_dec_caps)) 268 return false; 269 270 return true; 271} 272 273static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) 274{ 275 union dp_downstream_port_present ds_port_present; 276 277 if (!aconnector->dsc_aux) 278 return false; 279 280 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) { 281 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n"); 282 return false; 283 } 284 285 aconnector->mst_downstream_port_present = ds_port_present; 286 DRM_INFO("Downstream port present %d, type %d\n", 287 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE); 288 289 return true; 290} 291 292static int dm_dp_mst_get_modes(struct drm_connector *connector) 293{ 294 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 295 int ret = 0; 296 297 if (!aconnector) 298 return drm_add_edid_modes(connector, NULL); 299 300 if (!aconnector->edid) { 301 struct edid *edid; 302 303 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); 304 305 if (!edid) { 306 amdgpu_dm_set_mst_status(&aconnector->mst_status, 307 MST_REMOTE_EDID, false); 308 309 drm_connector_update_edid_property( 310 &aconnector->base, 311 NULL); 312 313 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); 314 if (!aconnector->dc_sink) { 315 struct dc_sink *dc_sink; 316 struct dc_sink_init_data init_params = { 317 .link = aconnector->dc_link, 318 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 319 320 dc_sink = dc_link_add_remote_sink( 321 aconnector->dc_link, 322 NULL, 323 0, 324 &init_params); 325 326 if (!dc_sink) { 327 DRM_ERROR("Unable to add a remote sink\n"); 328 return 0; 329 } 330 331 drm_dbg_dp(connector->dev, 332 "DM_MST: add remote sink 0x%p, %d remaining\n", 333 dc_sink, 334 aconnector->dc_link->sink_count); 335 336 dc_sink->priv = aconnector; 337 aconnector->dc_sink = dc_sink; 338 } 339 340 return ret; 341 } 342 343 aconnector->edid = edid; 344 amdgpu_dm_set_mst_status(&aconnector->mst_status, 345 MST_REMOTE_EDID, true); 346 } 347 348 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) { 349 dc_sink_release(aconnector->dc_sink); 350 aconnector->dc_sink = NULL; 351 } 352 353 if (!aconnector->dc_sink) { 354 struct dc_sink *dc_sink; 355 struct dc_sink_init_data init_params = { 356 .link = aconnector->dc_link, 357 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 358 dc_sink = dc_link_add_remote_sink( 359 aconnector->dc_link, 360 (uint8_t *)aconnector->edid, 361 (aconnector->edid->extensions + 1) * EDID_LENGTH, 362 &init_params); 363 364 if (!dc_sink) { 365 DRM_ERROR("Unable to add a remote sink\n"); 366 return 0; 367 } 368 369 drm_dbg_dp(connector->dev, 370 "DM_MST: add remote sink 0x%p, %d remaining\n", 371 dc_sink, aconnector->dc_link->sink_count); 372 373 dc_sink->priv = aconnector; 374 /* dc_link_add_remote_sink returns a new reference */ 375 aconnector->dc_sink = dc_sink; 376 377 /* when display is unplugged from mst hub, connctor will be 378 * destroyed within dm_dp_mst_connector_destroy. connector 379 * hdcp perperties, like type, undesired, desired, enabled, 380 * will be lost. So, save hdcp properties into hdcp_work within 381 * amdgpu_dm_atomic_commit_tail. if the same display is 382 * plugged back with same display index, its hdcp properties 383 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 384 */ 385 if (aconnector->dc_sink && connector->state) { 386 struct drm_device *dev = connector->dev; 387 struct amdgpu_device *adev = drm_to_adev(dev); 388 389 if (adev->dm.hdcp_workqueue) { 390 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 391 struct hdcp_workqueue *hdcp_w = 392 &hdcp_work[aconnector->dc_link->link_index]; 393 394 connector->state->hdcp_content_type = 395 hdcp_w->hdcp_content_type[connector->index]; 396 connector->state->content_protection = 397 hdcp_w->content_protection[connector->index]; 398 } 399 } 400 401 if (aconnector->dc_sink) { 402 amdgpu_dm_update_freesync_caps( 403 connector, aconnector->edid); 404 405 if (!validate_dsc_caps_on_connector(aconnector)) 406 memset(&aconnector->dc_sink->dsc_caps, 407 0, sizeof(aconnector->dc_sink->dsc_caps)); 408 409 if (!retrieve_downstream_port_device(aconnector)) 410 memset(&aconnector->mst_downstream_port_present, 411 0, sizeof(aconnector->mst_downstream_port_present)); 412 } 413 } 414 415 drm_connector_update_edid_property( 416 &aconnector->base, aconnector->edid); 417 418 ret = drm_add_edid_modes(connector, aconnector->edid); 419 420 return ret; 421} 422 423static struct drm_encoder * 424dm_mst_atomic_best_encoder(struct drm_connector *connector, 425 struct drm_atomic_state *state) 426{ 427 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 428 connector); 429 struct amdgpu_device *adev = drm_to_adev(connector->dev); 430 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); 431 432 return &adev->dm.mst_encoders[acrtc->crtc_id].base; 433} 434 435static int 436dm_dp_mst_detect(struct drm_connector *connector, 437 struct drm_modeset_acquire_ctx *ctx, bool force) 438{ 439 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 440 struct amdgpu_dm_connector *master = aconnector->mst_root; 441 struct drm_dp_mst_port *port = aconnector->mst_output_port; 442 int connection_status; 443 444 if (drm_connector_is_unregistered(connector)) 445 return connector_status_disconnected; 446 447 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, 448 aconnector->mst_output_port); 449 450 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) { 451 uint8_t dpcd_rev; 452 int ret; 453 454 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev); 455 456 if (ret == 1) { 457 port->dpcd_rev = dpcd_rev; 458 459 /* Could be DP1.2 DP Rx case*/ 460 if (!dpcd_rev) { 461 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev); 462 463 if (ret == 1) 464 port->dpcd_rev = dpcd_rev; 465 } 466 467 if (!dpcd_rev) 468 DRM_DEBUG_KMS("Can't decide DPCD revision number!"); 469 } 470 471 /* 472 * Could be legacy sink, logical port etc on DP1.2. 473 * Will get Nack under these cases when issue remote 474 * DPCD read. 475 */ 476 if (ret != 1) 477 DRM_DEBUG_KMS("Can't access DPCD"); 478 } else if (port->pdt == DP_PEER_DEVICE_NONE) { 479 port->dpcd_rev = 0; 480 } 481 482 /* 483 * Release dc_sink for connector which unplug event is notified by CSN msg 484 */ 485 if (connection_status == connector_status_disconnected && aconnector->dc_sink) { 486 if (aconnector->dc_link->sink_count) 487 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); 488 489 drm_dbg_dp(connector->dev, 490 "DM_MST: remove remote sink 0x%p, %d remaining\n", 491 aconnector->dc_link, 492 aconnector->dc_link->sink_count); 493 494 dc_sink_release(aconnector->dc_sink); 495 aconnector->dc_sink = NULL; 496 aconnector->edid = NULL; 497 498 amdgpu_dm_set_mst_status(&aconnector->mst_status, 499 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD, 500 false); 501 } 502 503 return connection_status; 504} 505 506static int dm_dp_mst_atomic_check(struct drm_connector *connector, 507 struct drm_atomic_state *state) 508{ 509 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 510 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; 511 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; 512 513 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); 514} 515 516static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { 517 .get_modes = dm_dp_mst_get_modes, 518 .mode_valid = amdgpu_dm_connector_mode_valid, 519 .atomic_best_encoder = dm_mst_atomic_best_encoder, 520 .detect_ctx = dm_dp_mst_detect, 521 .atomic_check = dm_dp_mst_atomic_check, 522}; 523 524static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 525{ 526 drm_encoder_cleanup(encoder); 527} 528 529static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 530 .destroy = amdgpu_dm_encoder_destroy, 531}; 532 533void 534dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev) 535{ 536 struct drm_device *dev = adev_to_drm(adev); 537 int i; 538 539 for (i = 0; i < adev->dm.display_indexes_num; i++) { 540 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i]; 541 struct drm_encoder *encoder = &amdgpu_encoder->base; 542 543 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 544 545 drm_encoder_init( 546 dev, 547 &amdgpu_encoder->base, 548 &amdgpu_dm_encoder_funcs, 549 DRM_MODE_ENCODER_DPMST, 550 NULL); 551 552 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs); 553 } 554} 555 556static struct drm_connector * 557dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 558 struct drm_dp_mst_port *port, 559 const char *pathprop) 560{ 561 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 562 struct drm_device *dev = master->base.dev; 563 struct amdgpu_device *adev = drm_to_adev(dev); 564 struct amdgpu_dm_connector *aconnector; 565 struct drm_connector *connector; 566 int i; 567 568 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 569 if (!aconnector) 570 return NULL; 571 572 connector = &aconnector->base; 573 aconnector->mst_output_port = port; 574 aconnector->mst_root = master; 575 amdgpu_dm_set_mst_status(&aconnector->mst_status, 576 MST_PROBE, true); 577 578 if (drm_connector_init( 579 dev, 580 connector, 581 &dm_dp_mst_connector_funcs, 582 DRM_MODE_CONNECTOR_DisplayPort)) { 583 kfree(aconnector); 584 return NULL; 585 } 586 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs); 587 588 amdgpu_dm_connector_init_helper( 589 &adev->dm, 590 aconnector, 591 DRM_MODE_CONNECTOR_DisplayPort, 592 master->dc_link, 593 master->connector_id); 594 595 for (i = 0; i < adev->dm.display_indexes_num; i++) { 596 drm_connector_attach_encoder(&aconnector->base, 597 &adev->dm.mst_encoders[i].base); 598 } 599 600 connector->max_bpc_property = master->base.max_bpc_property; 601 if (connector->max_bpc_property) 602 drm_connector_attach_max_bpc_property(connector, 8, 16); 603 604 connector->vrr_capable_property = master->base.vrr_capable_property; 605 if (connector->vrr_capable_property) 606 drm_connector_attach_vrr_capable_property(connector); 607 608 drm_object_attach_property( 609 &connector->base, 610 dev->mode_config.path_property, 611 0); 612 drm_object_attach_property( 613 &connector->base, 614 dev->mode_config.tile_property, 615 0); 616 617 drm_connector_set_path_property(connector, pathprop); 618 619 /* 620 * Initialize connector state before adding the connectror to drm and 621 * framebuffer lists 622 */ 623 amdgpu_dm_connector_funcs_reset(connector); 624 625 drm_dp_mst_get_port_malloc(port); 626 627 return connector; 628} 629 630void dm_handle_mst_sideband_msg_ready_event( 631 struct drm_dp_mst_topology_mgr *mgr, 632 enum mst_msg_ready_type msg_rdy_type) 633{ 634 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 635 uint8_t dret; 636 bool new_irq_handled = false; 637 int dpcd_addr; 638 uint8_t dpcd_bytes_to_read; 639 const uint8_t max_process_count = 30; 640 uint8_t process_count = 0; 641 u8 retry; 642 struct amdgpu_dm_connector *aconnector = 643 container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 644 645 646 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 647 648 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 649 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 650 /* DPCD 0x200 - 0x201 for downstream IRQ */ 651 dpcd_addr = DP_SINK_COUNT; 652 } else { 653 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 654 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 655 dpcd_addr = DP_SINK_COUNT_ESI; 656 } 657 658 mutex_lock(&aconnector->handle_mst_msg_ready); 659 660 while (process_count < max_process_count) { 661 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; 662 663 process_count++; 664 665 dret = drm_dp_dpcd_read( 666 &aconnector->dm_dp_aux.aux, 667 dpcd_addr, 668 esi, 669 dpcd_bytes_to_read); 670 671 if (dret != dpcd_bytes_to_read) { 672 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!"); 673 break; 674 } 675 676 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 677 678 switch (msg_rdy_type) { 679 case DOWN_REP_MSG_RDY_EVENT: 680 /* Only handle DOWN_REP_MSG_RDY case*/ 681 esi[1] &= DP_DOWN_REP_MSG_RDY; 682 break; 683 case UP_REQ_MSG_RDY_EVENT: 684 /* Only handle UP_REQ_MSG_RDY case*/ 685 esi[1] &= DP_UP_REQ_MSG_RDY; 686 break; 687 default: 688 /* Handle both cases*/ 689 esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY); 690 break; 691 } 692 693 if (!esi[1]) 694 break; 695 696 /* handle MST irq */ 697 if (aconnector->mst_mgr.mst_state) 698 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, 699 esi, 700 ack, 701 &new_irq_handled); 702 703 if (new_irq_handled) { 704 /* ACK at DPCD to notify down stream */ 705 for (retry = 0; retry < 3; retry++) { 706 ssize_t wret; 707 708 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, 709 dpcd_addr + 1, 710 ack[1]); 711 if (wret == 1) 712 break; 713 } 714 715 if (retry == 3) { 716 DRM_ERROR("Failed to ack MST event.\n"); 717 break; 718 } 719 720 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); 721 722 new_irq_handled = false; 723 } else { 724 break; 725 } 726 } 727 728 mutex_unlock(&aconnector->handle_mst_msg_ready); 729 730 if (process_count == max_process_count) 731 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 732} 733 734static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) 735{ 736 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); 737} 738 739static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 740 .add_connector = dm_dp_add_mst_connector, 741 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, 742}; 743 744void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 745 struct amdgpu_dm_connector *aconnector, 746 int link_index) 747{ 748 struct dc_link_settings max_link_enc_cap = {0}; 749 750 aconnector->dm_dp_aux.aux.name = 751 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", 752 link_index); 753 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; 754 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; 755 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; 756 757 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 758 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 759 &aconnector->base); 760 761 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 762 return; 763 764 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); 765 aconnector->mst_mgr.cbs = &dm_mst_cbs; 766 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), 767 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); 768 769 drm_connector_attach_dp_subconnector_property(&aconnector->base); 770} 771 772int dm_mst_get_pbn_divider(struct dc_link *link) 773{ 774 if (!link) 775 return 0; 776 777 return dc_link_bandwidth_kbps(link, 778 dc_link_get_link_cap(link)) / (8 * 1000 * 54); 779} 780 781struct dsc_mst_fairness_params { 782 struct dc_crtc_timing *timing; 783 struct dc_sink *sink; 784 struct dc_dsc_bw_range bw_range; 785 bool compression_possible; 786 struct drm_dp_mst_port *port; 787 enum dsc_clock_force_state clock_force_enable; 788 uint32_t num_slices_h; 789 uint32_t num_slices_v; 790 uint32_t bpp_overwrite; 791 struct amdgpu_dm_connector *aconnector; 792}; 793 794static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) 795{ 796 u8 link_coding_cap; 797 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B; 798 799 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link); 800 if (link_coding_cap == DP_128b_132b_ENCODING) 801 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B; 802 803 return fec_overhead_multiplier_x1000; 804} 805 806static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) 807{ 808 u64 peak_kbps = kbps; 809 810 peak_kbps *= 1006; 811 peak_kbps *= fec_overhead_multiplier_x1000; 812 peak_kbps = div_u64(peak_kbps, 1000 * 1000); 813 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); 814} 815 816static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, 817 struct dsc_mst_fairness_vars *vars, 818 int count, 819 int k) 820{ 821 struct drm_connector *drm_connector; 822 int i; 823 struct dc_dsc_config_options dsc_options = {0}; 824 825 for (i = 0; i < count; i++) { 826 drm_connector = ¶ms[i].aconnector->base; 827 828 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options); 829 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 830 831 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); 832 if (vars[i + k].dsc_enabled && dc_dsc_compute_config( 833 params[i].sink->ctx->dc->res_pool->dscs[0], 834 ¶ms[i].sink->dsc_caps.dsc_dec_caps, 835 &dsc_options, 836 0, 837 params[i].timing, 838 dc_link_get_highest_encoding_format(params[i].aconnector->dc_link), 839 ¶ms[i].timing->dsc_cfg)) { 840 params[i].timing->flags.DSC = 1; 841 842 if (params[i].bpp_overwrite) 843 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; 844 else 845 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; 846 847 if (params[i].num_slices_h) 848 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; 849 850 if (params[i].num_slices_v) 851 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; 852 } else { 853 params[i].timing->flags.DSC = 0; 854 } 855 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; 856 } 857 858 for (i = 0; i < count; i++) { 859 if (params[i].sink) { 860 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 861 params[i].sink->sink_signal != SIGNAL_TYPE_NONE) 862 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i, 863 params[i].sink->edid_caps.display_name); 864 } 865 866 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n", 867 params[i].timing->flags.DSC, 868 params[i].timing->dsc_cfg.bits_per_pixel, 869 vars[i + k].pbn); 870 } 871} 872 873static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) 874{ 875 struct dc_dsc_config dsc_config; 876 u64 kbps; 877 878 struct drm_connector *drm_connector = ¶m.aconnector->base; 879 struct dc_dsc_config_options dsc_options = {0}; 880 881 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); 882 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 883 884 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); 885 dc_dsc_compute_config( 886 param.sink->ctx->dc->res_pool->dscs[0], 887 ¶m.sink->dsc_caps.dsc_dec_caps, 888 &dsc_options, 889 (int) kbps, param.timing, 890 dc_link_get_highest_encoding_format(param.aconnector->dc_link), 891 &dsc_config); 892 893 return dsc_config.bits_per_pixel; 894} 895 896static int increase_dsc_bpp(struct drm_atomic_state *state, 897 struct drm_dp_mst_topology_state *mst_state, 898 struct dc_link *dc_link, 899 struct dsc_mst_fairness_params *params, 900 struct dsc_mst_fairness_vars *vars, 901 int count, 902 int k) 903{ 904 int i; 905 bool bpp_increased[MAX_PIPES]; 906 int initial_slack[MAX_PIPES]; 907 int min_initial_slack; 908 int next_index; 909 int remaining_to_increase = 0; 910 int link_timeslots_used; 911 int fair_pbn_alloc; 912 int ret = 0; 913 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 914 915 for (i = 0; i < count; i++) { 916 if (vars[i + k].dsc_enabled) { 917 initial_slack[i] = 918 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn; 919 bpp_increased[i] = false; 920 remaining_to_increase += 1; 921 } else { 922 initial_slack[i] = 0; 923 bpp_increased[i] = true; 924 } 925 } 926 927 while (remaining_to_increase) { 928 next_index = -1; 929 min_initial_slack = -1; 930 for (i = 0; i < count; i++) { 931 if (!bpp_increased[i]) { 932 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { 933 min_initial_slack = initial_slack[i]; 934 next_index = i; 935 } 936 } 937 } 938 939 if (next_index == -1) 940 break; 941 942 link_timeslots_used = 0; 943 944 for (i = 0; i < count; i++) 945 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div)); 946 947 fair_pbn_alloc = 948 (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div); 949 950 if (initial_slack[next_index] > fair_pbn_alloc) { 951 vars[next_index].pbn += fair_pbn_alloc; 952 ret = drm_dp_atomic_find_time_slots(state, 953 params[next_index].port->mgr, 954 params[next_index].port, 955 vars[next_index].pbn); 956 if (ret < 0) 957 return ret; 958 959 ret = drm_dp_mst_atomic_check(state); 960 if (ret == 0) { 961 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); 962 } else { 963 vars[next_index].pbn -= fair_pbn_alloc; 964 ret = drm_dp_atomic_find_time_slots(state, 965 params[next_index].port->mgr, 966 params[next_index].port, 967 vars[next_index].pbn); 968 if (ret < 0) 969 return ret; 970 } 971 } else { 972 vars[next_index].pbn += initial_slack[next_index]; 973 ret = drm_dp_atomic_find_time_slots(state, 974 params[next_index].port->mgr, 975 params[next_index].port, 976 vars[next_index].pbn); 977 if (ret < 0) 978 return ret; 979 980 ret = drm_dp_mst_atomic_check(state); 981 if (ret == 0) { 982 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; 983 } else { 984 vars[next_index].pbn -= initial_slack[next_index]; 985 ret = drm_dp_atomic_find_time_slots(state, 986 params[next_index].port->mgr, 987 params[next_index].port, 988 vars[next_index].pbn); 989 if (ret < 0) 990 return ret; 991 } 992 } 993 994 bpp_increased[next_index] = true; 995 remaining_to_increase--; 996 } 997 return 0; 998} 999 1000static int try_disable_dsc(struct drm_atomic_state *state, 1001 struct dc_link *dc_link, 1002 struct dsc_mst_fairness_params *params, 1003 struct dsc_mst_fairness_vars *vars, 1004 int count, 1005 int k) 1006{ 1007 int i; 1008 bool tried[MAX_PIPES]; 1009 int kbps_increase[MAX_PIPES]; 1010 int max_kbps_increase; 1011 int next_index; 1012 int remaining_to_try = 0; 1013 int ret; 1014 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1015 1016 for (i = 0; i < count; i++) { 1017 if (vars[i + k].dsc_enabled 1018 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16 1019 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) { 1020 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; 1021 tried[i] = false; 1022 remaining_to_try += 1; 1023 } else { 1024 kbps_increase[i] = 0; 1025 tried[i] = true; 1026 } 1027 } 1028 1029 while (remaining_to_try) { 1030 next_index = -1; 1031 max_kbps_increase = -1; 1032 for (i = 0; i < count; i++) { 1033 if (!tried[i]) { 1034 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { 1035 max_kbps_increase = kbps_increase[i]; 1036 next_index = i; 1037 } 1038 } 1039 } 1040 1041 if (next_index == -1) 1042 break; 1043 1044 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1045 ret = drm_dp_atomic_find_time_slots(state, 1046 params[next_index].port->mgr, 1047 params[next_index].port, 1048 vars[next_index].pbn); 1049 if (ret < 0) 1050 return ret; 1051 1052 ret = drm_dp_mst_atomic_check(state); 1053 if (ret == 0) { 1054 vars[next_index].dsc_enabled = false; 1055 vars[next_index].bpp_x16 = 0; 1056 } else { 1057 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000); 1058 ret = drm_dp_atomic_find_time_slots(state, 1059 params[next_index].port->mgr, 1060 params[next_index].port, 1061 vars[next_index].pbn); 1062 if (ret < 0) 1063 return ret; 1064 } 1065 1066 tried[next_index] = true; 1067 remaining_to_try--; 1068 } 1069 return 0; 1070} 1071 1072static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 1073 struct dc_state *dc_state, 1074 struct dc_link *dc_link, 1075 struct dsc_mst_fairness_vars *vars, 1076 struct drm_dp_mst_topology_mgr *mgr, 1077 int *link_vars_start_index) 1078{ 1079 struct dc_stream_state *stream; 1080 struct dsc_mst_fairness_params params[MAX_PIPES]; 1081 struct amdgpu_dm_connector *aconnector; 1082 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr); 1083 int count = 0; 1084 int i, k, ret; 1085 bool debugfs_overwrite = false; 1086 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1087 1088 memset(params, 0, sizeof(params)); 1089 1090 if (IS_ERR(mst_state)) 1091 return PTR_ERR(mst_state); 1092 1093 /* Set up params */ 1094 for (i = 0; i < dc_state->stream_count; i++) { 1095 struct dc_dsc_policy dsc_policy = {0}; 1096 1097 stream = dc_state->streams[i]; 1098 1099 if (stream->link != dc_link) 1100 continue; 1101 1102 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1103 if (!aconnector) 1104 continue; 1105 1106 if (!aconnector->mst_output_port) 1107 continue; 1108 1109 stream->timing.flags.DSC = 0; 1110 1111 params[count].timing = &stream->timing; 1112 params[count].sink = stream->sink; 1113 params[count].aconnector = aconnector; 1114 params[count].port = aconnector->mst_output_port; 1115 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable; 1116 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE) 1117 debugfs_overwrite = true; 1118 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 1119 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 1120 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel; 1121 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported; 1122 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy); 1123 if (!dc_dsc_compute_bandwidth_range( 1124 stream->sink->ctx->dc->res_pool->dscs[0], 1125 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1126 dsc_policy.min_target_bpp * 16, 1127 dsc_policy.max_target_bpp * 16, 1128 &stream->sink->dsc_caps.dsc_dec_caps, 1129 &stream->timing, 1130 dc_link_get_highest_encoding_format(dc_link), 1131 ¶ms[count].bw_range)) 1132 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 1133 dc_link_get_highest_encoding_format(dc_link)); 1134 1135 count++; 1136 } 1137 1138 if (count == 0) { 1139 ASSERT(0); 1140 return 0; 1141 } 1142 1143 /* k is start index of vars for current phy link used by mst hub */ 1144 k = *link_vars_start_index; 1145 /* set vars start index for next mst hub phy link */ 1146 *link_vars_start_index += count; 1147 1148 /* Try no compression */ 1149 for (i = 0; i < count; i++) { 1150 vars[i + k].aconnector = params[i].aconnector; 1151 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1152 vars[i + k].dsc_enabled = false; 1153 vars[i + k].bpp_x16 = 0; 1154 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, 1155 vars[i + k].pbn); 1156 if (ret < 0) 1157 return ret; 1158 } 1159 ret = drm_dp_mst_atomic_check(state); 1160 if (ret == 0 && !debugfs_overwrite) { 1161 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1162 return 0; 1163 } else if (ret != -ENOSPC) { 1164 return ret; 1165 } 1166 1167 /* Try max compression */ 1168 for (i = 0; i < count; i++) { 1169 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { 1170 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000); 1171 vars[i + k].dsc_enabled = true; 1172 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; 1173 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1174 params[i].port, vars[i + k].pbn); 1175 if (ret < 0) 1176 return ret; 1177 } else { 1178 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1179 vars[i + k].dsc_enabled = false; 1180 vars[i + k].bpp_x16 = 0; 1181 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1182 params[i].port, vars[i + k].pbn); 1183 if (ret < 0) 1184 return ret; 1185 } 1186 } 1187 ret = drm_dp_mst_atomic_check(state); 1188 if (ret != 0) 1189 return ret; 1190 1191 /* Optimize degree of compression */ 1192 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k); 1193 if (ret < 0) 1194 return ret; 1195 1196 ret = try_disable_dsc(state, dc_link, params, vars, count, k); 1197 if (ret < 0) 1198 return ret; 1199 1200 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1201 1202 return 0; 1203} 1204 1205static bool is_dsc_need_re_compute( 1206 struct drm_atomic_state *state, 1207 struct dc_state *dc_state, 1208 struct dc_link *dc_link) 1209{ 1210 int i, j; 1211 bool is_dsc_need_re_compute = false; 1212 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; 1213 int new_stream_on_link_num = 0; 1214 struct amdgpu_dm_connector *aconnector; 1215 struct dc_stream_state *stream; 1216 const struct dc *dc = dc_link->dc; 1217 1218 /* only check phy used by dsc mst branch */ 1219 if (dc_link->type != dc_connection_mst_branch) 1220 return false; 1221 1222 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || 1223 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1224 return false; 1225 1226 for (i = 0; i < MAX_PIPES; i++) 1227 stream_on_link[i] = NULL; 1228 1229 /* check if there is mode change in new request */ 1230 for (i = 0; i < dc_state->stream_count; i++) { 1231 struct drm_crtc_state *new_crtc_state; 1232 struct drm_connector_state *new_conn_state; 1233 1234 stream = dc_state->streams[i]; 1235 if (!stream) 1236 continue; 1237 1238 /* check if stream using the same link for mst */ 1239 if (stream->link != dc_link) 1240 continue; 1241 1242 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context; 1243 if (!aconnector) 1244 continue; 1245 1246 stream_on_link[new_stream_on_link_num] = aconnector; 1247 new_stream_on_link_num++; 1248 1249 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); 1250 if (!new_conn_state) 1251 continue; 1252 1253 if (IS_ERR(new_conn_state)) 1254 continue; 1255 1256 if (!new_conn_state->crtc) 1257 continue; 1258 1259 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 1260 if (!new_crtc_state) 1261 continue; 1262 1263 if (IS_ERR(new_crtc_state)) 1264 continue; 1265 1266 if (new_crtc_state->enable && new_crtc_state->active) { 1267 if (new_crtc_state->mode_changed || new_crtc_state->active_changed || 1268 new_crtc_state->connectors_changed) 1269 return true; 1270 } 1271 } 1272 1273 /* check current_state if there stream on link but it is not in 1274 * new request state 1275 */ 1276 for (i = 0; i < dc->current_state->stream_count; i++) { 1277 stream = dc->current_state->streams[i]; 1278 /* only check stream on the mst hub */ 1279 if (stream->link != dc_link) 1280 continue; 1281 1282 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1283 if (!aconnector) 1284 continue; 1285 1286 for (j = 0; j < new_stream_on_link_num; j++) { 1287 if (stream_on_link[j]) { 1288 if (aconnector == stream_on_link[j]) 1289 break; 1290 } 1291 } 1292 1293 if (j == new_stream_on_link_num) { 1294 /* not in new state */ 1295 is_dsc_need_re_compute = true; 1296 break; 1297 } 1298 } 1299 1300 return is_dsc_need_re_compute; 1301} 1302 1303int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1304 struct dc_state *dc_state, 1305 struct dsc_mst_fairness_vars *vars) 1306{ 1307 int i, j; 1308 struct dc_stream_state *stream; 1309 bool computed_streams[MAX_PIPES]; 1310 struct amdgpu_dm_connector *aconnector; 1311 struct drm_dp_mst_topology_mgr *mst_mgr; 1312 struct resource_pool *res_pool; 1313 int link_vars_start_index = 0; 1314 int ret = 0; 1315 1316 for (i = 0; i < dc_state->stream_count; i++) 1317 computed_streams[i] = false; 1318 1319 for (i = 0; i < dc_state->stream_count; i++) { 1320 stream = dc_state->streams[i]; 1321 res_pool = stream->ctx->dc->res_pool; 1322 1323 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1324 continue; 1325 1326 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1327 1328 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1329 continue; 1330 1331 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1332 continue; 1333 1334 if (computed_streams[i]) 1335 continue; 1336 1337 if (res_pool->funcs->remove_stream_from_ctx && 1338 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) 1339 return -EINVAL; 1340 1341 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1342 continue; 1343 1344 mst_mgr = aconnector->mst_output_port->mgr; 1345 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1346 &link_vars_start_index); 1347 if (ret != 0) 1348 return ret; 1349 1350 for (j = 0; j < dc_state->stream_count; j++) { 1351 if (dc_state->streams[j]->link == stream->link) 1352 computed_streams[j] = true; 1353 } 1354 } 1355 1356 for (i = 0; i < dc_state->stream_count; i++) { 1357 stream = dc_state->streams[i]; 1358 1359 if (stream->timing.flags.DSC == 1) 1360 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) 1361 return -EINVAL; 1362 } 1363 1364 return ret; 1365} 1366 1367static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1368 struct dc_state *dc_state, 1369 struct dsc_mst_fairness_vars *vars) 1370{ 1371 int i, j; 1372 struct dc_stream_state *stream; 1373 bool computed_streams[MAX_PIPES]; 1374 struct amdgpu_dm_connector *aconnector; 1375 struct drm_dp_mst_topology_mgr *mst_mgr; 1376 int link_vars_start_index = 0; 1377 int ret = 0; 1378 1379 for (i = 0; i < dc_state->stream_count; i++) 1380 computed_streams[i] = false; 1381 1382 for (i = 0; i < dc_state->stream_count; i++) { 1383 stream = dc_state->streams[i]; 1384 1385 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1386 continue; 1387 1388 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1389 1390 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1391 continue; 1392 1393 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1394 continue; 1395 1396 if (computed_streams[i]) 1397 continue; 1398 1399 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1400 continue; 1401 1402 mst_mgr = aconnector->mst_output_port->mgr; 1403 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1404 &link_vars_start_index); 1405 if (ret != 0) 1406 return ret; 1407 1408 for (j = 0; j < dc_state->stream_count; j++) { 1409 if (dc_state->streams[j]->link == stream->link) 1410 computed_streams[j] = true; 1411 } 1412 } 1413 1414 return ret; 1415} 1416 1417static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, 1418 struct dc_stream_state *stream) 1419{ 1420 int i; 1421 struct drm_crtc *crtc; 1422 struct drm_crtc_state *new_state, *old_state; 1423 1424 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) { 1425 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state); 1426 1427 if (dm_state->stream == stream) 1428 return i; 1429 } 1430 return -1; 1431} 1432 1433static bool is_link_to_dschub(struct dc_link *dc_link) 1434{ 1435 union dpcd_dsc_basic_capabilities *dsc_caps = 1436 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps; 1437 1438 /* only check phy used by dsc mst branch */ 1439 if (dc_link->type != dc_connection_mst_branch) 1440 return false; 1441 1442 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT || 1443 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1444 return false; 1445 return true; 1446} 1447 1448static bool is_dsc_precompute_needed(struct drm_atomic_state *state) 1449{ 1450 int i; 1451 struct drm_crtc *crtc; 1452 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1453 bool ret = false; 1454 1455 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1456 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state); 1457 1458 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) { 1459 ret = false; 1460 break; 1461 } 1462 if (dm_crtc_state->stream && dm_crtc_state->stream->link) 1463 if (is_link_to_dschub(dm_crtc_state->stream->link)) 1464 ret = true; 1465 } 1466 return ret; 1467} 1468 1469int pre_validate_dsc(struct drm_atomic_state *state, 1470 struct dm_atomic_state **dm_state_ptr, 1471 struct dsc_mst_fairness_vars *vars) 1472{ 1473 int i; 1474 struct dm_atomic_state *dm_state; 1475 struct dc_state *local_dc_state = NULL; 1476 int ret = 0; 1477 1478 if (!is_dsc_precompute_needed(state)) { 1479 DRM_INFO_ONCE("DSC precompute is not needed.\n"); 1480 return 0; 1481 } 1482 ret = dm_atomic_get_state(state, dm_state_ptr); 1483 if (ret != 0) { 1484 DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); 1485 return ret; 1486 } 1487 dm_state = *dm_state_ptr; 1488 1489 /* 1490 * create local vailable for dc_state. copy content of streams of dm_state->context 1491 * to local variable. make sure stream pointer of local variable not the same as stream 1492 * from dm_state->context. 1493 */ 1494 1495 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL); 1496 if (!local_dc_state) 1497 return -ENOMEM; 1498 1499 for (i = 0; i < local_dc_state->stream_count; i++) { 1500 struct dc_stream_state *stream = dm_state->context->streams[i]; 1501 int ind = find_crtc_index_in_state_by_stream(state, stream); 1502 1503 if (ind >= 0) { 1504 struct drm_connector *connector; 1505 struct amdgpu_dm_connector *aconnector; 1506 struct drm_connector_state *drm_new_conn_state; 1507 struct dm_connector_state *dm_new_conn_state; 1508 struct dm_crtc_state *dm_old_crtc_state; 1509 1510 connector = 1511 amdgpu_dm_find_first_crtc_matching_connector(state, 1512 state->crtcs[ind].ptr); 1513 aconnector = to_amdgpu_dm_connector(connector); 1514 drm_new_conn_state = 1515 drm_atomic_get_new_connector_state(state, 1516 &aconnector->base); 1517 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 1518 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state); 1519 1520 local_dc_state->streams[i] = 1521 create_validate_stream_for_sink(aconnector, 1522 &state->crtcs[ind].new_state->mode, 1523 dm_new_conn_state, 1524 dm_old_crtc_state->stream); 1525 if (local_dc_state->streams[i] == NULL) { 1526 ret = -EINVAL; 1527 break; 1528 } 1529 } 1530 } 1531 1532 if (ret != 0) 1533 goto clean_exit; 1534 1535 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars); 1536 if (ret != 0) { 1537 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); 1538 ret = -EINVAL; 1539 goto clean_exit; 1540 } 1541 1542 /* 1543 * compare local_streams -> timing with dm_state->context, 1544 * if the same set crtc_state->mode-change = 0; 1545 */ 1546 for (i = 0; i < local_dc_state->stream_count; i++) { 1547 struct dc_stream_state *stream = dm_state->context->streams[i]; 1548 1549 if (local_dc_state->streams[i] && 1550 dc_is_timing_changed(stream, local_dc_state->streams[i])) { 1551 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i); 1552 } else { 1553 int ind = find_crtc_index_in_state_by_stream(state, stream); 1554 1555 if (ind >= 0) 1556 state->crtcs[ind].new_state->mode_changed = 0; 1557 } 1558 } 1559clean_exit: 1560 for (i = 0; i < local_dc_state->stream_count; i++) { 1561 struct dc_stream_state *stream = dm_state->context->streams[i]; 1562 1563 if (local_dc_state->streams[i] != stream) 1564 dc_stream_release(local_dc_state->streams[i]); 1565 } 1566 1567 kfree(local_dc_state); 1568 1569 return ret; 1570} 1571 1572static unsigned int kbps_from_pbn(unsigned int pbn) 1573{ 1574 unsigned int kbps = pbn; 1575 1576 kbps *= (1000000 / PEAK_FACTOR_X1000); 1577 kbps *= 8; 1578 kbps *= 54; 1579 kbps /= 64; 1580 1581 return kbps; 1582} 1583 1584static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 1585 struct dc_dsc_bw_range *bw_range) 1586{ 1587 struct dc_dsc_policy dsc_policy = {0}; 1588 1589 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy); 1590 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], 1591 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1592 dsc_policy.min_target_bpp * 16, 1593 dsc_policy.max_target_bpp * 16, 1594 &stream->sink->dsc_caps.dsc_dec_caps, 1595 &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range); 1596 1597 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; 1598} 1599 1600enum dc_status dm_dp_mst_is_port_support_mode( 1601 struct amdgpu_dm_connector *aconnector, 1602 struct dc_stream_state *stream) 1603{ 1604 int bpp, pbn, branch_max_throughput_mps = 0; 1605 struct dc_link_settings cur_link_settings; 1606 unsigned int end_to_end_bw_in_kbps = 0; 1607 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0; 1608 struct dc_dsc_bw_range bw_range = {0}; 1609 struct dc_dsc_config_options dsc_options = {0}; 1610 1611 /* 1612 * Consider the case with the depth of the mst topology tree is equal or less than 2 1613 * A. When dsc bitstream can be transmitted along the entire path 1614 * 1. dsc is possible between source and branch/leaf device (common dsc params is possible), AND 1615 * 2. dsc passthrough supported at MST branch, or 1616 * 3. dsc decoding supported at leaf MST device 1617 * Use maximum dsc compression as bw constraint 1618 * B. When dsc bitstream cannot be transmitted along the entire path 1619 * Use native bw as bw constraint 1620 */ 1621 if (is_dsc_common_config_possible(stream, &bw_range) && 1622 (aconnector->mst_output_port->passthrough_aux || 1623 aconnector->dsc_aux == &aconnector->mst_output_port->aux)) { 1624 cur_link_settings = stream->link->verified_link_cap; 1625 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, &cur_link_settings); 1626 down_link_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn); 1627 1628 /* pick the end to end bw bottleneck */ 1629 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, down_link_bw_in_kbps); 1630 1631 if (end_to_end_bw_in_kbps < bw_range.min_kbps) { 1632 DRM_DEBUG_DRIVER("maximum dsc compression cannot fit into end-to-end bandwidth\n"); 1633 return DC_FAIL_BANDWIDTH_VALIDATE; 1634 } 1635 1636 if (end_to_end_bw_in_kbps < bw_range.stream_kbps) { 1637 dc_dsc_get_default_config_option(stream->link->dc, &dsc_options); 1638 dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16; 1639 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0], 1640 &stream->sink->dsc_caps.dsc_dec_caps, 1641 &dsc_options, 1642 end_to_end_bw_in_kbps, 1643 &stream->timing, 1644 dc_link_get_highest_encoding_format(stream->link), 1645 &stream->timing.dsc_cfg)) { 1646 stream->timing.flags.DSC = 1; 1647 DRM_DEBUG_DRIVER("end-to-end bandwidth require dsc and dsc config found\n"); 1648 } else { 1649 DRM_DEBUG_DRIVER("end-to-end bandwidth require dsc but dsc config not found\n"); 1650 return DC_FAIL_BANDWIDTH_VALIDATE; 1651 } 1652 } 1653 } else { 1654 /* check if mode could be supported within full_pbn */ 1655 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; 1656 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4); 1657 if (pbn > aconnector->mst_output_port->full_pbn) 1658 return DC_FAIL_BANDWIDTH_VALIDATE; 1659 } 1660 1661 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ 1662 switch (stream->timing.pixel_encoding) { 1663 case PIXEL_ENCODING_RGB: 1664 case PIXEL_ENCODING_YCBCR444: 1665 branch_max_throughput_mps = 1666 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps; 1667 break; 1668 case PIXEL_ENCODING_YCBCR422: 1669 case PIXEL_ENCODING_YCBCR420: 1670 branch_max_throughput_mps = 1671 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps; 1672 break; 1673 default: 1674 break; 1675 } 1676 1677 if (branch_max_throughput_mps != 0 && 1678 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) 1679 return DC_FAIL_BANDWIDTH_VALIDATE; 1680 1681 return DC_OK; 1682} 1683