Searched refs:DPLL (Results 1 - 11 of 11) sorted by relevance

/linux-master/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h15 #define DPLL 3 macro
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h15 #define DPLL 3 macro
/linux-master/arch/arm/mach-omap2/
H A Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c406 hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
464 "Unknown DPLL mode %08x in programmed "
523 /* In case of DSI, DPLL will not be used */
551 /* In case of DSI, DPLL will not be used */
1117 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
1118 * Enable) must be set to ���1��� in both the DPLL A Control Register
1119 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
1294 * possible to share the DPLL between CRT and HDMI. Enabling
1299 * DPLLs and so DPLL sharing is the only way to get three pipes
1301 * and potentially avoid enabling the second DPLL, bu
[all...]
H A Dintel_dvo.c459 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE);
465 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
H A Dintel_display_power_well.c1196 * CHV DPLL B/C have some issues if VGA mode is enabled.
1199 u32 val = intel_de_read(dev_priv, DPLL(pipe));
1205 intel_de_write(dev_priv, DPLL(pipe), val);
1358 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1541 * (eg. for pipe B DPLL) the entire channel will
H A Dintel_display.c380 dpll_reg = DPLL(0);
384 dpll_reg = DPLL(0);
1310 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1311 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
8186 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8189 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8190 intel_de_write(dev_priv, DPLL(pipe), dpll);
8193 intel_de_posting_read(dev_priv, DPLL(pipe));
8197 * DPLL is enabled and the clocks are stable.
8201 intel_de_write(dev_priv, DPLL(pip
[all...]
H A Dintel_display_power.c1771 u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
1844 /* cmnlane needs DPLL registers */
H A Dintel_pps.c122 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
125 * The DPLL for the pipe must be enabled for this to work.
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h256 #define DPLL 0x034A macro
/linux-master/drivers/gpu/drm/i915/
H A Di915_reg.h671 #define DPLL(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
755 * Selects the phase for the 10X DPLL clock for the PCIe
788 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
794 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
4839 /* DPLL control1 */
4854 /* DPLL control2 */
4862 /* DPLL Status */
4866 /* DPLL cfg */
1415 #define DPLL macro

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