Lines Matching refs:DPLL
380 dpll_reg = DPLL(0);
384 dpll_reg = DPLL(0);
1310 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1311 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
8186 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8189 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8190 intel_de_write(dev_priv, DPLL(pipe), dpll);
8193 intel_de_posting_read(dev_priv, DPLL(pipe));
8197 * DPLL is enabled and the clocks are stable.
8201 intel_de_write(dev_priv, DPLL(pipe), dpll);
8205 intel_de_write(dev_priv, DPLL(pipe), dpll);
8206 intel_de_posting_read(dev_priv, DPLL(pipe));
8239 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8240 intel_de_posting_read(dev_priv, DPLL(pipe));