i915/display/intel_dpll.c

406 	hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
464 				    "Unknown DPLL mode %08x in programmed "
523 	/* In case of DSI, DPLL will not be used */
551 	/* In case of DSI, DPLL will not be used */
1117 	 *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
1118 	 *  Enable) must be set to ���1��� in both the DPLL A Control Register
1119 	 *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
1294 	 * possible to share the DPLL between CRT and HDMI. Enabling
1299 	 * DPLLs and so DPLL sharing is the only way to get three pipes
1301 	 * and potentially avoid enabling the second DPLL, but it's not
1303 	 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
1433 	/* DPLL not used with DSI, but still need the rest set up */
1459 	/* DPLL not used with DSI, but still need the rest set up */
1755 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
1782 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
1842 	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1845 	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS);
1846 	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1849 	intel_de_posting_read(dev_priv, DPLL(pipe));
1856 		 * DPLL is enabled and the clocks are stable.
1860 		intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1865 		intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1866 		intel_de_posting_read(dev_priv, DPLL(pipe));
1994 	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1995 	intel_de_posting_read(dev_priv, DPLL(pipe));
1998 	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1999 		drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
2015 	intel_de_write(dev_priv, DPLL(pipe),
2141 	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
2144 	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
2161 	intel_de_write(dev_priv, DPLL(pipe),
2186 			    (intel_de_read(dev_priv, DPLL(PIPE_B)) &
2244 	intel_de_write(dev_priv, DPLL(pipe), val);
2245 	intel_de_posting_read(dev_priv, DPLL(pipe));
2262 	intel_de_write(dev_priv, DPLL(pipe), val);
2263 	intel_de_posting_read(dev_priv, DPLL(pipe));
2288 	intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
2289 	intel_de_posting_read(dev_priv, DPLL(pipe));
2315 	cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;