Searched refs:DCCG_GATE_DISABLE_CNTL2 (Results 1 - 22 of 22) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.h65 SR(DCCG_GATE_DISABLE_CNTL2),\
139 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
140 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
141 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
142 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
143 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
H A Ddcn31_dccg.c458 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
465 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
475 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
482 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
492 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
499 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
509 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
516 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
526 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
533 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.h73 SR(DCCG_GATE_DISABLE_CNTL2),\
191 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
192 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
193 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
194 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
195 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dccg.h154 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\
155 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
156 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
157 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
158 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
197 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\
H A Ddcn35_dccg.c370 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
374 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
378 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
382 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
386 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c617 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
622 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
623 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
624 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
625 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
626 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABL
[all...]
H A Ddcn35_resource.h168 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c597 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
598 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
599 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
600 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
601 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
602 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
603 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
604 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
605 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
606 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABL
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c152 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
155 REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,
310 REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, 0,
315 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, 0);
316 REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, 0,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.h199 SR(DCCG_GATE_DISABLE_CNTL2), \
424 SR(DCCG_GATE_DISABLE_CNTL2), \
636 uint32_t DCCG_GATE_DISABLE_CNTL2; member in struct:dce_hwseq_registers
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c365 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h380 uint32_t DCCG_GATE_DISABLE_CNTL2; member in struct:dccg_registers
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c251 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c783 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c693 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c684 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c681 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c929 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c687 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c536 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c533 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1665 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);

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