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3a87e25a |
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27-Jun-2023 |
Daniel Miess <daniel.miess@amd.com> |
drm/amd/display: Fix DP2 link training failure with RCO [Why] When RCO is enabled for symclk32_le we get failures during DP2 link traing compliance tests. [How] Break out symclk32_le RCO into a separate function that is called for hpo when link is enabled/disabled. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Daniel Miess <daniel.miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1f5dcb73 |
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10-Jun-2022 |
Michael Strauss <michael.strauss@amd.com> |
drm/amd/display: Fix dpstreamclk programming [WHY] Currently programming incorrect hpo inst as well as selecting incorrect source [HOW] Use hpo inst instead of otg inst to select dpstreamclk inst Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ee7b62e1 |
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28-Jun-2022 |
Roman Li <roman.li@amd.com> |
drm/amd/display: Enable DCN314 in DC Add support for DCN 3.1.4 in Display Core Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d3dfceb5 |
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23-Feb-2022 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: Add dependant changes for DCN32/321 [Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a8201902 |
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13-May-2022 |
Leung, Martin <Martin.Leung@amd.com> |
drm/amdgpu/display: Prepare for new interfaces why: lut pipeline will be hooked up differently in some asics need to add new interfaces how: add them Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Martin <martin.leung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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05d6aea3 |
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23-Jan-2022 |
David Galiffi <David.Galiffi@amd.com> |
drm/amd/display: Disable physym clock [How & Why] Disable physym clock when it's not in use. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: David Galiffi <David.Galiffi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0015cce5 |
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23-Jan-2022 |
David Galiffi <David.Galiffi@amd.com> |
drm/amd/display: Fix disabling dccg clocks [How & Why] Updated procedure to match hardware programming guide. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: David Galiffi <David.Galiffi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e7414a1a |
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22-Sep-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Disable hdmistream and hdmichar clocks [Why & How] Disable hdmistream and hdmichar root clocks when not being used. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bda24462 |
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22-Sep-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le [Why & How] Disable dpstreamclk, symclk32_se, and symclk32_le when not in use. Reviewed-by: Ariel Bernstein <eric.yang2@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e22ad7e3 |
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22-Sep-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Disable dsc root clock when not being used [Why & How] Disable root clock for dsc when not being used. Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d76b12da |
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26-Jul-2021 |
Fangzhi Zuo <Jerry.Zuo@amd.com> |
drm/amd/display: Add DP 2.0 DCCG HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | | +--------------------+ | | v ===============|============= v +------------------+ | DIO Output Mux | +------------------+ | v +-----+ | PHY | +-----+ | PHYD32CLK[0] v +------+ | DCCG | +------+ | v SYMCLK32 Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d8a2b4f3 |
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19-May-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Add DCN3.1 DCCG Add programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ | DCCG | +--------+ Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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