/freebsd-11-stable/sys/arm/amlogic/aml8726/ |
H A D | aml8726_usb_phy-m3.c | 105 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro 259 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 268 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 275 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 282 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 289 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 296 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 303 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 310 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 322 CSR_BARRIER(s [all...] |
H A D | aml8726_pic.c | 113 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro 128 CSR_BARRIER(aml8726_pic_sc, AML_PIC_STAT_CLR_REG(nb)); 257 CSR_BARRIER(aml8726_pic_sc, AML_PIC_MASK_REG(nb)); 276 CSR_BARRIER(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
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H A D | aml8726_usb_phy-m6.c | 102 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro 251 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); 275 CSR_BARRIER(sc, AML_USB_PHY_CTRL_REG); 287 CSR_BARRIER(sc, AML_USB_PHY_CTRL_REG); 309 CSR_BARRIER(sc, AML_USB_PHY_ADP_BC_REG); 384 CSR_BARRIER(sc, AML_USB_PHY_CTRL_REG);
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H A D | aml8726_sdxc-m8.c | 154 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro 207 CSR_BARRIER(sc, AML_SDXC_SOFT_RESET_REG); 239 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); 246 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); 250 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); 284 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); 291 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); 309 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); 435 CSR_BARRIER(sc, AML_SDXC_SEND_REG); 452 CSR_BARRIER(s [all...] |
H A D | aml8726_clkmsr.c | 107 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro 125 CSR_BARRIER(sc, AML_CLKMSR_0_REG); 133 CSR_BARRIER(sc, AML_CLKMSR_0_REG); 141 CSR_BARRIER(sc, AML_CLKMSR_0_REG);
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H A D | aml8726_rtc.c | 127 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro 139 CSR_BARRIER(sc, AML_RTC_0_REG); 167 CSR_BARRIER(sc, AML_RTC_0_REG); 174 CSR_BARRIER(sc, AML_RTC_0_REG); 283 CSR_BARRIER(sc, AML_RTC_0_REG);
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H A D | aml8726_wdt.c | 102 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro 153 CSR_BARRIER(sc, AML_WDT_CTRL_REG);
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H A D | aml8726_mmc.c | 102 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro 211 CSR_BARRIER(sc, AML_MMC_IRQ_CONFIG_REG); 348 CSR_BARRIER(sc, AML_MMC_CMD_SEND_REG); 365 CSR_BARRIER(sc, AML_MMC_IRQ_STATUS_REG); 478 CSR_BARRIER(sc, AML_MMC_IRQ_STATUS_REG);
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/freebsd-11-stable/sys/dev/tl/ |
H A D | if_tl.c | 376 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 379 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 389 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 392 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 402 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 405 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 416 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 419 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 430 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 433 CSR_BARRIER(s [all...] |
H A D | if_tlreg.h | 472 #define CSR_BARRIER(sc, reg, length, flags) \ macro
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/freebsd-11-stable/sys/dev/bm/ |
H A D | if_bmreg.h | 169 #define CSR_BARRIER(sc, reg, length, flags) \ macro
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H A D | if_bm.c | 173 CSR_BARRIER(sc, BM_MII_CSR, 2, 189 CSR_BARRIER(sc, BM_MII_CSR, 2,
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/freebsd-11-stable/sys/dev/xl/ |
H A D | if_xlreg.h | 666 #define CSR_BARRIER(sc, reg, length, flags) \ macro 670 CSR_BARRIER(sc, XL_COMMAND, 2, \ 673 CSR_BARRIER(sc, XL_COMMAND, 2, \
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H A D | if_xl.c | 390 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 408 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
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/freebsd-11-stable/sys/dev/wb/ |
H A D | if_wbreg.h | 381 #define CSR_BARRIER(sc, reg, length, flags) \ macro
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H A D | if_wb.c | 356 CSR_BARRIER(sc, WB_SIO, 4, 373 CSR_BARRIER(sc, WB_SIO, 4,
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/freebsd-11-stable/sys/dev/ste/ |
H A D | if_stereg.h | 495 #define CSR_BARRIER(sc, reg, length, flags) \ macro
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H A D | if_ste.c | 214 CSR_BARRIER(sc, STE_PHYCTL, 1, 231 CSR_BARRIER(sc, STE_PHYCTL, 1,
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/freebsd-11-stable/sys/dev/stge/ |
H A D | if_stgereg.h | 102 #define CSR_BARRIER(_sc, reg, length, flags) \ macro
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H A D | if_stge.c | 258 CSR_BARRIER(sc, STGE_PhyCtrl, 1, 276 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
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/freebsd-11-stable/sys/dev/sis/ |
H A D | if_sis.c | 124 #define CSR_BARRIER(sc, reg, length, flags) \ macro 447 CSR_BARRIER(sc, SIS_EECTL, 4, 463 CSR_BARRIER(sc, SIS_EECTL, 4,
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/freebsd-11-stable/sys/dev/rl/ |
H A D | if_rl.c | 368 CSR_BARRIER(sc, RL_MII, 1, 385 CSR_BARRIER(sc, RL_MII, 1,
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H A D | if_rlreg.h | 962 #define CSR_BARRIER(sc, reg, length, flags) \ macro
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