1139825Simp/*- 238363Swpaul * Copyright (c) 1997, 1998 338363Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 438363Swpaul * 538363Swpaul * Redistribution and use in source and binary forms, with or without 638363Swpaul * modification, are permitted provided that the following conditions 738363Swpaul * are met: 838363Swpaul * 1. Redistributions of source code must retain the above copyright 938363Swpaul * notice, this list of conditions and the following disclaimer. 1038363Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1138363Swpaul * notice, this list of conditions and the following disclaimer in the 1238363Swpaul * documentation and/or other materials provided with the distribution. 1338363Swpaul * 3. All advertising materials mentioning features or use of this software 1438363Swpaul * must display the following acknowledgement: 1538363Swpaul * This product includes software developed by Bill Paul. 1638363Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1738363Swpaul * may be used to endorse or promote products derived from this software 1838363Swpaul * without specific prior written permission. 1938363Swpaul * 2038363Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2138363Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2238363Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338363Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2438363Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2538363Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2638363Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2738363Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2838363Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2938363Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3038363Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3138363Swpaul * 3250477Speter * $FreeBSD$ 3338363Swpaul */ 3438363Swpaul 3538363Swpaul#define XL_EE_READ 0x0080 /* read, 5 bit address */ 3638363Swpaul#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 3738363Swpaul#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 3838363Swpaul#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 3967233Simp#define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */ 4038363Swpaul#define XL_EE_BUSY 0x8000 4138363Swpaul 4238363Swpaul#define XL_EE_EADDR0 0x00 /* station address, first word */ 4338363Swpaul#define XL_EE_EADDR1 0x01 /* station address, next word, */ 4438363Swpaul#define XL_EE_EADDR2 0x02 /* station address, last word */ 4538363Swpaul#define XL_EE_PRODID 0x03 /* product ID code */ 4638363Swpaul#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 4738363Swpaul#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 4838363Swpaul#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 4938363Swpaul#define XL_EE_MFG_ID 0x07 5038363Swpaul#define XL_EE_PCI_PARM 0x08 5138363Swpaul#define XL_EE_ROM_ONFO 0x09 5238363Swpaul#define XL_EE_OEM_ADR0 0x0A 53131596Sbms#define XL_EE_OEM_ADR1 0x0B 5438363Swpaul#define XL_EE_OEM_ADR2 0x0C 5538363Swpaul#define XL_EE_SOFTINFO1 0x0D 5638363Swpaul#define XL_EE_COMPAT 0x0E 5738363Swpaul#define XL_EE_SOFTINFO2 0x0F 5838363Swpaul#define XL_EE_CAPS 0x10 /* capabilities word */ 5938363Swpaul#define XL_EE_RSVD0 0x11 6038363Swpaul#define XL_EE_ICFG_0 0x12 6138363Swpaul#define XL_EE_ICFG_1 0x13 6238363Swpaul#define XL_EE_RSVD1 0x14 6338363Swpaul#define XL_EE_SOFTINFO3 0x15 6438363Swpaul#define XL_EE_RSVD_2 0x16 6538363Swpaul 6638363Swpaul/* 6738363Swpaul * Bits in the capabilities word 6838363Swpaul */ 6938363Swpaul#define XL_CAPS_PNP 0x0001 7038363Swpaul#define XL_CAPS_FULL_DUPLEX 0x0002 7138363Swpaul#define XL_CAPS_LARGE_PKTS 0x0004 7238363Swpaul#define XL_CAPS_SLAVE_DMA 0x0008 7338363Swpaul#define XL_CAPS_SECOND_DMA 0x0010 7438363Swpaul#define XL_CAPS_FULL_BM 0x0020 7538363Swpaul#define XL_CAPS_FRAG_BM 0x0040 7638363Swpaul#define XL_CAPS_CRC_PASSTHRU 0x0080 7738363Swpaul#define XL_CAPS_TXDONE 0x0100 7838363Swpaul#define XL_CAPS_NO_TXLENGTH 0x0200 7938363Swpaul#define XL_CAPS_RX_REPEAT 0x0400 8038363Swpaul#define XL_CAPS_SNOOPING 0x0800 8138363Swpaul#define XL_CAPS_100MBPS 0x1000 8238363Swpaul#define XL_CAPS_PWRMGMT 0x2000 8338363Swpaul 84211717Syongari/* 85211717Syongari * Bits in the software information 2 word 86211717Syongari */ 87211717Syongari#define XL_SINFO2_FIXED_BCAST_RX_BUG 0x0002 88211717Syongari#define XL_SINFO2_FIXED_ENDEC_LOOP_BUG 0x0004 89211717Syongari#define XL_SINFO2_AUX_WOL_CON 0x0008 90211717Syongari#define XL_SINFO2_PME_PULSED 0x0010 91211717Syongari#define XL_SINFO2_FIXED_MWI_BUG 0x0020 92211717Syongari#define XL_SINFO2_WOL_AFTER_PWR_LOSS 0x0040 93211717Syongari#define XL_SINFO2_AUTO_RST_TO_D0 0x0080 94211717Syongari 9577548Swpaul#define XL_PACKET_SIZE 1540 96117375Swpaul#define XL_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 97117375Swpaul 9838363Swpaul/* 9938363Swpaul * Register layouts. 10038363Swpaul */ 10138363Swpaul#define XL_COMMAND 0x0E 10238363Swpaul#define XL_STATUS 0x0E 10338363Swpaul 10438363Swpaul#define XL_TX_STATUS 0x1B 10538363Swpaul#define XL_TX_FREE 0x1C 10638363Swpaul#define XL_DMACTL 0x20 10738363Swpaul#define XL_DOWNLIST_PTR 0x24 10851441Swpaul#define XL_DOWN_POLL 0x2D /* 3c90xB only */ 10938363Swpaul#define XL_TX_FREETHRESH 0x2F 11038363Swpaul#define XL_UPLIST_PTR 0x38 11138363Swpaul#define XL_UPLIST_STATUS 0x30 11251441Swpaul#define XL_UP_POLL 0x3D /* 3c90xB only */ 11338363Swpaul 11438363Swpaul#define XL_PKTSTAT_UP_STALLED 0x00002000 11538363Swpaul#define XL_PKTSTAT_UP_ERROR 0x00004000 11638363Swpaul#define XL_PKTSTAT_UP_CMPLT 0x00008000 11738363Swpaul 11838363Swpaul#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 11938363Swpaul#define XL_DMACTL_DOWN_STALLED 0x00000004 12038363Swpaul#define XL_DMACTL_UP_CMPLT 0x00000008 12138363Swpaul#define XL_DMACTL_DOWN_CMPLT 0x00000010 12238363Swpaul#define XL_DMACTL_UP_RX_EARLY 0x00000020 12338363Swpaul#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 12438363Swpaul#define XL_DMACTL_DOWN_INPROG 0x00000080 12538363Swpaul#define XL_DMACTL_COUNTER_SPEED 0x00000100 12638363Swpaul#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 127221568Syongari#define XL_DMACTL_UP_ALTSEQ_DIS 0x00010000 /* 3c90xB/3c90xC */ 128221568Syongari#define XL_DMACTL_DOWN_ALTSEQ_DIS 0x00020000 /* 3c90xC only */ 129221568Syongari#define XL_DMACTL_DEFEAT_MWI 0x00100000 /* 3c90xB/3c90xC */ 130221568Syongari#define XL_DMACTL_DEFEAT_MRL 0x00100000 /* 3c90xB/3c90xC */ 131221568Syongari#define XL_DMACTL_UP_OVERRUN_DISC_DIS 0x00200000 /* 3c90xB/3c90xC */ 13238363Swpaul#define XL_DMACTL_TARGET_ABORT 0x40000000 13338363Swpaul#define XL_DMACTL_MASTER_ABORT 0x80000000 13438363Swpaul 13538363Swpaul/* 13638363Swpaul * Command codes. Some command codes require that we wait for 13738363Swpaul * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 13838363Swpaul */ 13938363Swpaul#define XL_CMD_RESET 0x0000 /* mustwait */ 14038363Swpaul#define XL_CMD_WINSEL 0x0800 14138363Swpaul#define XL_CMD_COAX_START 0x1000 14238363Swpaul#define XL_CMD_RX_DISABLE 0x1800 14338363Swpaul#define XL_CMD_RX_ENABLE 0x2000 14438363Swpaul#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 14538363Swpaul#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 14638363Swpaul#define XL_CMD_UP_UNSTALL 0x3001 14738363Swpaul#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 14838363Swpaul#define XL_CMD_DOWN_UNSTALL 0x3003 14938363Swpaul#define XL_CMD_RX_DISCARD 0x4000 15038363Swpaul#define XL_CMD_TX_ENABLE 0x4800 15138363Swpaul#define XL_CMD_TX_DISABLE 0x5000 15238363Swpaul#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 15338363Swpaul#define XL_CMD_INTR_FAKE 0x6000 15438363Swpaul#define XL_CMD_INTR_ACK 0x6800 15538363Swpaul#define XL_CMD_INTR_ENB 0x7000 15638363Swpaul#define XL_CMD_STAT_ENB 0x7800 15738363Swpaul#define XL_CMD_RX_SET_FILT 0x8000 15838363Swpaul#define XL_CMD_RX_SET_THRESH 0x8800 15938363Swpaul#define XL_CMD_TX_SET_THRESH 0x9000 16038363Swpaul#define XL_CMD_TX_SET_START 0x9800 16138363Swpaul#define XL_CMD_DMA_UP 0xA000 16238363Swpaul#define XL_CMD_DMA_STOP 0xA001 16338363Swpaul#define XL_CMD_STATS_ENABLE 0xA800 16438363Swpaul#define XL_CMD_STATS_DISABLE 0xB000 16538363Swpaul#define XL_CMD_COAX_STOP 0xB800 16638363Swpaul 16738363Swpaul#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 16838363Swpaul#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 16938363Swpaul 17038363Swpaul#define XL_HASH_SET 0x0400 17138363Swpaul#define XL_HASHFILT_SIZE 256 17238363Swpaul 17338363Swpaul/* 17438363Swpaul * status codes 17538363Swpaul * Note that bits 15 to 13 indicate the currently visible register window 17638363Swpaul * which may be anything from 0 to 7. 17738363Swpaul */ 17838363Swpaul#define XL_STAT_INTLATCH 0x0001 /* 0 */ 17938363Swpaul#define XL_STAT_ADFAIL 0x0002 /* 1 */ 18038363Swpaul#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 18138363Swpaul#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 182131596Sbms#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 18338363Swpaul#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 184131596Sbms#define XL_STAT_INTREQ 0x0040 /* 6 */ 185131596Sbms#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 18638363Swpaul#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 18738363Swpaul#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 18838363Swpaul#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 18938363Swpaul#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 19038363Swpaul#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 191131596Sbms#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 19238363Swpaul 19338363Swpaul/* 19438526Swpaul * Interrupts we normally want enabled. 19538526Swpaul */ 19638526Swpaul#define XL_INTRS \ 19788079Ssilby (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 19838526Swpaul XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 19938526Swpaul 20038526Swpaul/* 20138363Swpaul * Window 0 registers 20238363Swpaul */ 20338363Swpaul#define XL_W0_EE_DATA 0x0C 20438363Swpaul#define XL_W0_EE_CMD 0x0A 20538363Swpaul#define XL_W0_RSRC_CFG 0x08 20638363Swpaul#define XL_W0_ADDR_CFG 0x06 20738363Swpaul#define XL_W0_CFG_CTRL 0x04 20838363Swpaul 20938363Swpaul#define XL_W0_PROD_ID 0x02 21038363Swpaul#define XL_W0_MFG_ID 0x00 21138363Swpaul 21238363Swpaul/* 21338363Swpaul * Window 1 21438363Swpaul */ 21538363Swpaul 21638363Swpaul#define XL_W1_TX_FIFO 0x10 21738363Swpaul 21838363Swpaul#define XL_W1_FREE_TX 0x0C 21938363Swpaul#define XL_W1_TX_STATUS 0x0B 22038363Swpaul#define XL_W1_TX_TIMER 0x0A 22138363Swpaul#define XL_W1_RX_STATUS 0x08 22238363Swpaul#define XL_W1_RX_FIFO 0x00 22338363Swpaul 22438363Swpaul/* 22538363Swpaul * RX status codes 22638363Swpaul */ 22738363Swpaul#define XL_RXSTATUS_OVERRUN 0x01 22838363Swpaul#define XL_RXSTATUS_RUNT 0x02 22938363Swpaul#define XL_RXSTATUS_ALIGN 0x04 23038363Swpaul#define XL_RXSTATUS_CRC 0x08 23138363Swpaul#define XL_RXSTATUS_OVERSIZE 0x10 23238363Swpaul#define XL_RXSTATUS_DRIBBLE 0x20 23338363Swpaul 23438363Swpaul/* 23538363Swpaul * TX status codes 23638363Swpaul */ 237131596Sbms#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 23838363Swpaul#define XL_TXSTATUS_OVERFLOW 0x04 23938363Swpaul#define XL_TXSTATUS_MAXCOLS 0x08 24038363Swpaul#define XL_TXSTATUS_UNDERRUN 0x10 24138363Swpaul#define XL_TXSTATUS_JABBER 0x20 24238363Swpaul#define XL_TXSTATUS_INTREQ 0x40 24338363Swpaul#define XL_TXSTATUS_COMPLETE 0x80 24438363Swpaul 24538363Swpaul/* 24638363Swpaul * Window 2 24738363Swpaul */ 24838363Swpaul#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 24938363Swpaul#define XL_W2_STATION_MASK_HI 0x0A 25038363Swpaul#define XL_W2_STATION_MASK_MID 0x08 25138363Swpaul#define XL_W2_STATION_MASK_LO 0x06 25238363Swpaul#define XL_W2_STATION_ADDR_HI 0x04 25338363Swpaul#define XL_W2_STATION_ADDR_MID 0x02 25438363Swpaul#define XL_W2_STATION_ADDR_LO 0x00 25538363Swpaul 256131596Sbms#define XL_RESETOPT_FEATUREMASK (0x0001 | 0x0002 | 0x004) 25738363Swpaul#define XL_RESETOPT_D3RESETDIS 0x0008 25838363Swpaul#define XL_RESETOPT_DISADVFD 0x0010 25938363Swpaul#define XL_RESETOPT_DISADV100 0x0020 26038363Swpaul#define XL_RESETOPT_DISAUTONEG 0x0040 26138363Swpaul#define XL_RESETOPT_DEBUGMODE 0x0080 26238363Swpaul#define XL_RESETOPT_FASTAUTO 0x0100 26338363Swpaul#define XL_RESETOPT_FASTEE 0x0200 26438363Swpaul#define XL_RESETOPT_FORCEDCONF 0x0400 26538363Swpaul#define XL_RESETOPT_TESTPDTPDR 0x0800 26638363Swpaul#define XL_RESETOPT_TEST100TX 0x1000 26738363Swpaul#define XL_RESETOPT_TEST100RX 0x2000 26838363Swpaul 26967233Simp#define XL_RESETOPT_INVERT_LED 0x0010 27067233Simp#define XL_RESETOPT_INVERT_MII 0x4000 27167233Simp 27238363Swpaul/* 27338363Swpaul * Window 3 (fifo management) 27438363Swpaul */ 27538363Swpaul#define XL_W3_INTERNAL_CFG 0x00 276131596Sbms#define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */ 27738363Swpaul#define XL_W3_RESET_OPT 0x08 27838363Swpaul#define XL_W3_FREE_TX 0x0C 27938363Swpaul#define XL_W3_FREE_RX 0x0A 28038363Swpaul#define XL_W3_MAC_CTRL 0x06 28138363Swpaul 28238363Swpaul#define XL_ICFG_CONNECTOR_MASK 0x00F00000 28338363Swpaul#define XL_ICFG_CONNECTOR_BITS 20 28438363Swpaul 28538363Swpaul#define XL_ICFG_RAMSIZE_MASK 0x00000007 28638363Swpaul#define XL_ICFG_RAMWIDTH 0x00000008 287131596Sbms#define XL_ICFG_ROMSIZE_MASK (0x00000040 | 0x00000080) 28838363Swpaul#define XL_ICFG_DISABLE_BASSD 0x00000100 28938363Swpaul#define XL_ICFG_RAMLOC 0x00000200 290131596Sbms#define XL_ICFG_RAMPART (0x00010000 | 0x00020000) 291131596Sbms#define XL_ICFG_XCVRSEL (0x00100000 | 0x00200000 | 0x00400000) 29238363Swpaul#define XL_ICFG_AUTOSEL 0x01000000 29338363Swpaul 29438363Swpaul#define XL_XCVR_10BT 0x00 29538363Swpaul#define XL_XCVR_AUI 0x01 29638363Swpaul#define XL_XCVR_RSVD_0 0x02 29738363Swpaul#define XL_XCVR_COAX 0x03 29838363Swpaul#define XL_XCVR_100BTX 0x04 29938363Swpaul#define XL_XCVR_100BFX 0x05 30038363Swpaul#define XL_XCVR_MII 0x06 30138363Swpaul#define XL_XCVR_RSVD_1 0x07 30238363Swpaul#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 30338363Swpaul 30438363Swpaul#define XL_MACCTRL_DEFER_EXT_END 0x0001 30538363Swpaul#define XL_MACCTRL_DEFER_0 0x0002 30638363Swpaul#define XL_MACCTRL_DEFER_1 0x0004 30738363Swpaul#define XL_MACCTRL_DEFER_2 0x0008 30838363Swpaul#define XL_MACCTRL_DEFER_3 0x0010 30938363Swpaul#define XL_MACCTRL_DUPLEX 0x0020 31038363Swpaul#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 311131596Sbms#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 /* 3c905B only */ 312131596Sbms#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 /* 3c905B only */ 313131596Sbms#define XL_MACCTRL_VLT_END 0x0200 /* 3c905B only */ 31438363Swpaul 31538363Swpaul/* 31638363Swpaul * The 'reset options' register contains power-on reset values 31738363Swpaul * loaded from the EEPROM. This includes the supported media 31838363Swpaul * types on the card. It is also known as the media options register. 31938363Swpaul */ 32038363Swpaul#define XL_W3_MEDIA_OPT 0x08 32138363Swpaul 32238363Swpaul#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 32338363Swpaul#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 32438363Swpaul#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 32538363Swpaul#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 32638363Swpaul#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 32738363Swpaul#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 32838363Swpaul#define XL_MEDIAOPT_MII 0x0040 /* MII */ 32938363Swpaul#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 33038363Swpaul 33138363Swpaul#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 33238363Swpaul#define XL_MEDIAOPT_MASK 0x01FF 33338363Swpaul 33438363Swpaul/* 33538363Swpaul * Window 4 (diagnostics) 33638363Swpaul */ 33738363Swpaul#define XL_W4_UPPERBYTESOK 0x0D 33838363Swpaul#define XL_W4_BADSSD 0x0C 33938363Swpaul#define XL_W4_MEDIA_STATUS 0x0A 34038363Swpaul#define XL_W4_PHY_MGMT 0x08 34138363Swpaul#define XL_W4_NET_DIAG 0x06 34238363Swpaul#define XL_W4_FIFO_DIAG 0x04 34338363Swpaul#define XL_W4_VCO_DIAG 0x02 34438363Swpaul 34538363Swpaul#define XL_W4_CTRLR_STAT 0x08 34638363Swpaul#define XL_W4_TX_DIAG 0x00 34738363Swpaul 34838363Swpaul#define XL_MII_CLK 0x01 34938363Swpaul#define XL_MII_DATA 0x02 35038363Swpaul#define XL_MII_DIR 0x04 35138363Swpaul 35238363Swpaul#define XL_MEDIA_SQE 0x0008 35338363Swpaul#define XL_MEDIA_10TP 0x00C0 35438363Swpaul#define XL_MEDIA_LNK 0x0080 35538363Swpaul#define XL_MEDIA_LNKBEAT 0x0800 35638363Swpaul 35738363Swpaul#define XL_MEDIASTAT_CRCSTRIP 0x0004 35838363Swpaul#define XL_MEDIASTAT_SQEENB 0x0008 35938363Swpaul#define XL_MEDIASTAT_COLDET 0x0010 36038363Swpaul#define XL_MEDIASTAT_CARRIER 0x0020 36138363Swpaul#define XL_MEDIASTAT_JABGUARD 0x0040 36238363Swpaul#define XL_MEDIASTAT_LINKBEAT 0x0080 36338363Swpaul#define XL_MEDIASTAT_JABDETECT 0x0200 36438363Swpaul#define XL_MEDIASTAT_POLREVERS 0x0400 36538363Swpaul#define XL_MEDIASTAT_LINKDETECT 0x0800 36638363Swpaul#define XL_MEDIASTAT_TXINPROG 0x1000 36738363Swpaul#define XL_MEDIASTAT_DCENB 0x4000 36838363Swpaul#define XL_MEDIASTAT_AUIDIS 0x8000 36938363Swpaul 37038363Swpaul#define XL_NETDIAG_TEST_LOWVOLT 0x0001 371131596Sbms#define XL_NETDIAG_ASIC_REVMASK \ 372131596Sbms (0x0002 | 0x0004 | 0x0008 | 0x0010 | 0x0020) 37338363Swpaul#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 37438363Swpaul#define XL_NETDIAG_STATS_ENABLED 0x0080 37538363Swpaul#define XL_NETDIAG_TX_FATALERR 0x0100 37638363Swpaul#define XL_NETDIAG_TRANSMITTING 0x0200 37738363Swpaul#define XL_NETDIAG_RX_ENABLED 0x0400 37838363Swpaul#define XL_NETDIAG_TX_ENABLED 0x0800 37938363Swpaul#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 38038363Swpaul#define XL_NETDIAG_MAC_LOOPBACK 0x2000 38138363Swpaul#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 38238363Swpaul#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 38338363Swpaul 38438363Swpaul/* 38538363Swpaul * Window 5 38638363Swpaul */ 38738363Swpaul#define XL_W5_STAT_ENB 0x0C 38838363Swpaul#define XL_W5_INTR_ENB 0x0A 38940588Swpaul#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 39038363Swpaul#define XL_W5_RX_FILTER 0x08 39138363Swpaul#define XL_W5_RX_EARLYTHRESH 0x06 39238363Swpaul#define XL_W5_TX_AVAILTHRESH 0x02 39338363Swpaul#define XL_W5_TX_STARTTHRESH 0x00 39438363Swpaul 39538363Swpaul/* 39638363Swpaul * RX filter bits 39738363Swpaul */ 39838363Swpaul#define XL_RXFILTER_INDIVIDUAL 0x01 39938363Swpaul#define XL_RXFILTER_ALLMULTI 0x02 40038363Swpaul#define XL_RXFILTER_BROADCAST 0x04 40138363Swpaul#define XL_RXFILTER_ALLFRAMES 0x08 402131596Sbms#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 40338363Swpaul 40438363Swpaul/* 40538363Swpaul * Window 6 (stats) 40638363Swpaul */ 40738363Swpaul#define XL_W6_TX_BYTES_OK 0x0C 40838363Swpaul#define XL_W6_RX_BYTES_OK 0x0A 40938363Swpaul#define XL_W6_UPPER_FRAMES_OK 0x09 41038363Swpaul#define XL_W6_DEFERRED 0x08 41138363Swpaul#define XL_W6_RX_OK 0x07 41238363Swpaul#define XL_W6_TX_OK 0x06 41338363Swpaul#define XL_W6_RX_OVERRUN 0x05 41438363Swpaul#define XL_W6_COL_LATE 0x04 41538363Swpaul#define XL_W6_COL_SINGLE 0x03 41638363Swpaul#define XL_W6_COL_MULTIPLE 0x02 41738363Swpaul#define XL_W6_SQE_ERRORS 0x01 41838363Swpaul#define XL_W6_CARRIER_LOST 0x00 41938363Swpaul 42038363Swpaul/* 42138363Swpaul * Window 7 (bus master control) 42238363Swpaul */ 42338363Swpaul#define XL_W7_BM_ADDR 0x00 42438363Swpaul#define XL_W7_BM_LEN 0x06 42538363Swpaul#define XL_W7_BM_STATUS 0x0B 42638363Swpaul#define XL_W7_BM_TIMEr 0x0A 427211717Syongari#define XL_W7_BM_PME 0x0C 42838363Swpaul 429211717Syongari#define XL_BM_PME_WAKE 0x0001 430211717Syongari#define XL_BM_PME_MAGIC 0x0002 431211717Syongari#define XL_BM_PME_LINKCHG 0x0004 432211717Syongari#define XL_BM_PME_WAKETIMER 0x0008 43338363Swpaul/* 43438363Swpaul * bus master control registers 43538363Swpaul */ 43638363Swpaul#define XL_BM_PKTSTAT 0x20 43738363Swpaul#define XL_BM_DOWNLISTPTR 0x24 43838363Swpaul#define XL_BM_FRAGADDR 0x28 43938363Swpaul#define XL_BM_FRAGLEN 0x2C 44038363Swpaul#define XL_BM_TXFREETHRESH 0x2F 44138363Swpaul#define XL_BM_UPPKTSTAT 0x30 44238363Swpaul#define XL_BM_UPLISTPTR 0x38 44338363Swpaul 44438363Swpaul#define XL_LAST_FRAG 0x80000000 44538363Swpaul 446107959Smux#define XL_MAXFRAGS 63 447107959Smux#define XL_RX_LIST_CNT 128 448107959Smux#define XL_TX_LIST_CNT 256 449131596Sbms#define XL_RX_LIST_SZ \ 450131596Sbms (XL_RX_LIST_CNT * sizeof(struct xl_list_onefrag)) 451131596Sbms#define XL_TX_LIST_SZ \ 452131596Sbms (XL_TX_LIST_CNT * sizeof(struct xl_list)) 453107959Smux#define XL_MIN_FRAMELEN 60 454107959Smux#define ETHER_ALIGN 2 455107959Smux#define XL_INC(x, y) (x) = (x + 1) % y 456107959Smux 45738363Swpaul/* 45838363Swpaul * Boomerang/Cyclone TX/RX list structure. 45938363Swpaul * For the TX lists, bits 0 to 12 of the status word indicate 46038363Swpaul * length. 46138363Swpaul * This looks suspiciously like the ThunderLAN, doesn't it. 46238363Swpaul */ 46338363Swpaulstruct xl_frag { 46438363Swpaul u_int32_t xl_addr; /* 63 addr/len pairs */ 46538363Swpaul u_int32_t xl_len; 46638363Swpaul}; 46738363Swpaul 46838363Swpaulstruct xl_list { 46938363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 47038363Swpaul u_int32_t xl_status; 471107959Smux struct xl_frag xl_frag[XL_MAXFRAGS]; 47238363Swpaul}; 47338363Swpaul 47438363Swpaulstruct xl_list_onefrag { 47538363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 476221561Syongari volatile u_int32_t xl_status; 477221561Syongari volatile struct xl_frag xl_frag; 47838363Swpaul}; 47938363Swpaul 48038363Swpaulstruct xl_list_data { 481107959Smux struct xl_list_onefrag *xl_rx_list; 482107959Smux struct xl_list *xl_tx_list; 483107959Smux u_int32_t xl_rx_dmaaddr; 484107959Smux bus_dma_tag_t xl_rx_tag; 485107959Smux bus_dmamap_t xl_rx_dmamap; 486109503Stmm u_int32_t xl_tx_dmaaddr; 487107959Smux bus_dma_tag_t xl_tx_tag; 488107959Smux bus_dmamap_t xl_tx_dmamap; 48938363Swpaul}; 49038363Swpaul 49138363Swpaulstruct xl_chain { 49238363Swpaul struct xl_list *xl_ptr; 49338363Swpaul struct mbuf *xl_mbuf; 49438363Swpaul struct xl_chain *xl_next; 49551441Swpaul struct xl_chain *xl_prev; 49651441Swpaul u_int32_t xl_phys; 497107959Smux bus_dmamap_t xl_map; 49838363Swpaul}; 49938363Swpaul 50038363Swpaulstruct xl_chain_onefrag { 50138363Swpaul struct xl_list_onefrag *xl_ptr; 50238363Swpaul struct mbuf *xl_mbuf; 50338363Swpaul struct xl_chain_onefrag *xl_next; 504107959Smux bus_dmamap_t xl_map; 50538363Swpaul}; 50638363Swpaul 50738363Swpaulstruct xl_chain_data { 50838363Swpaul struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 50938363Swpaul struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 510177562Smarius bus_dma_segment_t xl_tx_segs[XL_MAXFRAGS]; 51138363Swpaul 51238363Swpaul struct xl_chain_onefrag *xl_rx_head; 51338363Swpaul 51451441Swpaul /* 3c90x "boomerang" queuing stuff */ 51538363Swpaul struct xl_chain *xl_tx_head; 51638363Swpaul struct xl_chain *xl_tx_tail; 51738363Swpaul struct xl_chain *xl_tx_free; 51851441Swpaul 51951441Swpaul /* 3c90xB "cyclone/hurricane/tornado" stuff */ 52051441Swpaul int xl_tx_prod; 52151441Swpaul int xl_tx_cons; 52251441Swpaul int xl_tx_cnt; 52338363Swpaul}; 52438363Swpaul 52538363Swpaul#define XL_RXSTAT_LENMASK 0x00001FFF 52638363Swpaul#define XL_RXSTAT_UP_ERROR 0x00004000 52738363Swpaul#define XL_RXSTAT_UP_CMPLT 0x00008000 52838363Swpaul#define XL_RXSTAT_UP_OVERRUN 0x00010000 52938363Swpaul#define XL_RXSTAT_RUNT 0x00020000 53038363Swpaul#define XL_RXSTAT_ALIGN 0x00040000 53138363Swpaul#define XL_RXSTAT_CRC 0x00080000 53238363Swpaul#define XL_RXSTAT_OVERSIZE 0x00100000 53338363Swpaul#define XL_RXSTAT_DRIBBLE 0x00800000 53438363Swpaul#define XL_RXSTAT_UP_OFLOW 0x01000000 53538363Swpaul#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 53638363Swpaul#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 53738363Swpaul#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 53838363Swpaul#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 53938363Swpaul#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 54038363Swpaul#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 54138363Swpaul#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 54238363Swpaul 54338363Swpaul#define XL_TXSTAT_LENMASK 0x00001FFF 54438363Swpaul#define XL_TXSTAT_CRCDIS 0x00002000 54538363Swpaul#define XL_TXSTAT_TX_INTR 0x00008000 54638363Swpaul#define XL_TXSTAT_DL_COMPLETE 0x00010000 54738363Swpaul#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 54838363Swpaul#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 54938363Swpaul#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 55051441Swpaul#define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */ 55151441Swpaul#define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */ 55238363Swpaul#define XL_TXSTAT_DL_INTR 0x80000000 55338363Swpaul 55438363Swpaul#define XL_CAPABILITY_BM 0x20 55538363Swpaul 55638363Swpaulstruct xl_type { 55738363Swpaul u_int16_t xl_vid; 55838363Swpaul u_int16_t xl_did; 559226995Smarius const char *xl_name; 56038363Swpaul}; 56138363Swpaul 56238363Swpaul/* 56338363Swpaul * The 3C905B adapters implement a few features that we want to 56438363Swpaul * take advantage of, namely the multicast hash filter. With older 56538363Swpaul * chips, you only have the option of turning on reception of all 56638363Swpaul * multicast frames, which is kind of lame. 56751441Swpaul * 56851441Swpaul * We also use this to decide on a transmit strategy. For the 3c90xB 56951441Swpaul * cards, we can use polled descriptor mode, which reduces CPU overhead. 57038363Swpaul */ 57138363Swpaul#define XL_TYPE_905B 1 57238363Swpaul#define XL_TYPE_90X 2 57338363Swpaul 57465170Swpaul#define XL_FLAG_FUNCREG 0x0001 57565170Swpaul#define XL_FLAG_PHYOK 0x0002 57665170Swpaul#define XL_FLAG_EEPROM_OFFSET_30 0x0004 57765170Swpaul#define XL_FLAG_WEIRDRESET 0x0008 57865170Swpaul#define XL_FLAG_8BITROM 0x0010 57967233Simp#define XL_FLAG_INVERT_LED_PWR 0x0020 58067233Simp#define XL_FLAG_INVERT_MII_PWR 0x0040 581105675Ssilby#define XL_FLAG_NO_XCVR_PWR 0x0080 582112364Ssilby#define XL_FLAG_USE_MMIO 0x0100 583120058Smdodd#define XL_FLAG_NO_MMIO 0x0200 584211717Syongari#define XL_FLAG_WOL 0x0400 58565170Swpaul 586105675Ssilby#define XL_NO_XCVR_PWR_MAGICBITS 0x0900 587105675Ssilby 58838363Swpaulstruct xl_softc { 589147256Sbrooks struct ifnet *xl_ifp; /* interface info */ 590162317Sru device_t xl_dev; /* device info */ 59138363Swpaul struct ifmedia ifmedia; /* media info */ 59245062Swpaul bus_space_handle_t xl_bhandle; 59345062Swpaul bus_space_tag_t xl_btag; 59448947Swpaul void *xl_intrhand; 59548947Swpaul struct resource *xl_irq; 59648947Swpaul struct resource *xl_res; 59750579Swpaul device_t xl_miibus; 598177562Smarius const struct xl_type *xl_info; /* 3Com adapter info */ 599107959Smux bus_dma_tag_t xl_mtag; 600111091Smux bus_dmamap_t xl_tmpmap; /* spare DMA map */ 60138363Swpaul u_int8_t xl_type; 60238363Swpaul u_int32_t xl_xcvr; 60338363Swpaul u_int16_t xl_media; 60438363Swpaul u_int16_t xl_caps; 60546514Swpaul u_int16_t xl_tx_thresh; 606211717Syongari int xl_pmcap; 60752244Swpaul int xl_if_flags; 608107959Smux struct xl_list_data xl_ldata; 60938363Swpaul struct xl_chain_data xl_cdata; 610221566Syongari struct callout xl_tick_callout; 611164935Smarius int xl_wdog_timer; 61265170Swpaul int xl_flags; 61365170Swpaul struct resource *xl_fres; 61465170Swpaul bus_space_handle_t xl_fhandle; 61565170Swpaul bus_space_tag_t xl_ftag; 61667087Swpaul struct mtx xl_mtx; 617146435Sglebius struct task xl_task; 618144155Sru#ifdef DEVICE_POLLING 619144155Sru int rxcycles; 620144155Sru#endif 62138363Swpaul}; 62238363Swpaul 62372200Sbmilekic#define XL_LOCK(_sc) mtx_lock(&(_sc)->xl_mtx) 62472200Sbmilekic#define XL_UNLOCK(_sc) mtx_unlock(&(_sc)->xl_mtx) 625122689Ssam#define XL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->xl_mtx, MA_OWNED) 62667087Swpaul 62738363Swpaul#define xl_rx_goodframes(x) \ 62838363Swpaul ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 62938363Swpaul 63038363Swpaul#define xl_tx_goodframes(x) \ 63138363Swpaul ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 63238363Swpaul 63338363Swpaulstruct xl_stats { 63438363Swpaul u_int8_t xl_carrier_lost; 63538363Swpaul u_int8_t xl_sqe_errs; 63638363Swpaul u_int8_t xl_tx_multi_collision; 63738363Swpaul u_int8_t xl_tx_single_collision; 63838363Swpaul u_int8_t xl_tx_late_collision; 63938363Swpaul u_int8_t xl_rx_overrun; 64038363Swpaul u_int8_t xl_tx_frames_ok; 64138363Swpaul u_int8_t xl_rx_frames_ok; 64238363Swpaul u_int8_t xl_tx_deferred; 64338363Swpaul u_int8_t xl_upper_frames_ok; 64438363Swpaul u_int16_t xl_rx_bytes_ok; 64538363Swpaul u_int16_t xl_tx_bytes_ok; 64638363Swpaul u_int16_t status; 64738363Swpaul}; 64838363Swpaul 64938363Swpaul/* 65038363Swpaul * register space access macros 65138363Swpaul */ 65238363Swpaul#define CSR_WRITE_4(sc, reg, val) \ 65345062Swpaul bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 65438363Swpaul#define CSR_WRITE_2(sc, reg, val) \ 65545062Swpaul bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 65638363Swpaul#define CSR_WRITE_1(sc, reg, val) \ 65745062Swpaul bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 65838363Swpaul 65945062Swpaul#define CSR_READ_4(sc, reg) \ 66045062Swpaul bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 66145062Swpaul#define CSR_READ_2(sc, reg) \ 66245062Swpaul bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 66345062Swpaul#define CSR_READ_1(sc, reg) \ 66445062Swpaul bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 66538363Swpaul 666226995Smarius#define CSR_BARRIER(sc, reg, length, flags) \ 667226995Smarius bus_space_barrier(sc->xl_btag, sc->xl_bhandle, reg, length, flags) 668226995Smarius 669226995Smarius#define XL_SEL_WIN(x) do { \ 670226995Smarius CSR_BARRIER(sc, XL_COMMAND, 2, \ 671226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); \ 672226995Smarius CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x); \ 673226995Smarius CSR_BARRIER(sc, XL_COMMAND, 2, \ 674226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); \ 675226995Smarius} while (0) 676226995Smarius 67738363Swpaul#define XL_TIMEOUT 1000 67838363Swpaul 67938363Swpaul/* 68038363Swpaul * General constants that are fun to know. 68138363Swpaul * 68238363Swpaul * 3Com PCI vendor ID 68338363Swpaul */ 68438363Swpaul#define TC_VENDORID 0x10B7 68538363Swpaul 68638363Swpaul/* 68738363Swpaul * 3Com chip device IDs. 68838363Swpaul */ 68938363Swpaul#define TC_DEVICEID_BOOMERANG_10BT 0x9000 69038363Swpaul#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 69138363Swpaul#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 69238363Swpaul#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 69346204Swpaul#define TC_DEVICEID_KRAKATOA_10BT 0x9004 69446204Swpaul#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 69546204Swpaul#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 69645693Swpaul#define TC_DEVICEID_CYCLONE_10FL 0x900A 69746204Swpaul#define TC_DEVICEID_HURRICANE_10_100BT 0x9055 69838363Swpaul#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 69945601Swpaul#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 70040097Swpaul#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 70147627Swpaul#define TC_DEVICEID_TORNADO_10_100BT 0x9200 702109688Ssilby#define TC_DEVICEID_TORNADO_10_100BT_920B 0x9201 703139649Srwatson#define TC_DEVICEID_TORNADO_10_100BT_920B_WNM 0x9202 70446204Swpaul#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 70551301Swpaul#define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805 70645629Swpaul#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 70754697Swpaul#define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500 708108752Ssilby#define TC_DEVICEID_HURRICANE_555 0x5055 70965170Swpaul#define TC_DEVICEID_HURRICANE_556 0x6055 71065170Swpaul#define TC_DEVICEID_HURRICANE_556B 0x6056 71168227Ssanpei#define TC_DEVICEID_HURRICANE_575A 0x5057 71267233Simp#define TC_DEVICEID_HURRICANE_575B 0x5157 71367233Simp#define TC_DEVICEID_HURRICANE_575C 0x5257 71482446Swpaul#define TC_DEVICEID_HURRICANE_656 0x6560 71582446Swpaul#define TC_DEVICEID_HURRICANE_656B 0x6562 71682446Swpaul#define TC_DEVICEID_TORNADO_656C 0x6564 71738363Swpaul 71838363Swpaul/* 71938363Swpaul * PCI low memory base and low I/O base register, and 72038363Swpaul * other PCI registers. Note: some are only available on 72138363Swpaul * the 3c905B, in particular those that related to power management. 72238363Swpaul */ 72338363Swpaul#define XL_PCI_VENDOR_ID 0x00 72438363Swpaul#define XL_PCI_DEVICE_ID 0x02 72538363Swpaul#define XL_PCI_COMMAND 0x04 72638363Swpaul#define XL_PCI_STATUS 0x06 72738363Swpaul#define XL_PCI_CLASSCODE 0x09 72838363Swpaul#define XL_PCI_LATENCY_TIMER 0x0D 72938363Swpaul#define XL_PCI_HEADER_TYPE 0x0E 73038363Swpaul#define XL_PCI_LOIO 0x10 73138363Swpaul#define XL_PCI_LOMEM 0x14 73265170Swpaul#define XL_PCI_FUNCMEM 0x18 73338363Swpaul#define XL_PCI_BIOSROM 0x30 73438363Swpaul#define XL_PCI_INTLINE 0x3C 73538363Swpaul#define XL_PCI_INTPIN 0x3D 73638363Swpaul#define XL_PCI_MINGNT 0x3E 73738363Swpaul#define XL_PCI_MINLAT 0x0F 73838363Swpaul#define XL_PCI_RESETOPT 0x48 73938363Swpaul#define XL_PCI_EEPROM_DATA 0x4C 74038363Swpaul 74138363Swpaul/* 3c905B-only registers */ 74238363Swpaul#define XL_PCI_CAPID 0xDC /* 8 bits */ 74338363Swpaul#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 74438363Swpaul#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 74538363Swpaul#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 74638363Swpaul 74738363Swpaul#define XL_PSTATE_MASK 0x0003 74838363Swpaul#define XL_PSTATE_D0 0x0000 74938363Swpaul#define XL_PSTATE_D1 0x0002 75038363Swpaul#define XL_PSTATE_D2 0x0002 75138363Swpaul#define XL_PSTATE_D3 0x0003 75238363Swpaul#define XL_PME_EN 0x0010 75338363Swpaul#define XL_PME_STATUS 0x8000 75438363Swpaul 75546204Swpaul#ifndef IFM_10_FL 75646204Swpaul#define IFM_10_FL 13 /* 10baseFL - Fiber */ 75746204Swpaul#endif 758