/u-boot/drivers/clk/rockchip/ |
H A D | clk_pll.c | 85 u32 *postdiv2, 92 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { 93 freq = fout_hz * (*postdiv1) * (*postdiv2); 105 *postdiv2 = 1; 118 u32 f_frac, postdiv1, postdiv2; local 124 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); 126 rate_table->postdiv2 = postdiv2; 83 rockchip_pll_clk_set_postdiv(ulong fout_hz, u32 *postdiv1, u32 *postdiv2, u32 *foutvco) argument 363 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; local [all...] |
H A D | clk_rk3128.c | 35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; 49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 53 div->postdiv2, vco_hz, output_hz); 66 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 82 u32 postdiv1, postdiv2 = 1; local 97 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 98 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 101 vco_khz = freq_khz * postdiv1 * postdiv2; 104 postdiv2 > max_postdiv2) { 111 div->postdiv2 244 u32 refdiv, fbdiv, postdiv1, postdiv2; local [all...] |
H A D | clk_rk3036.c | 38 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 56 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 58 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ 61 div->postdiv2, vco_hz, output_hz); 72 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 176 uint32_t refdiv, fbdiv, postdiv1, postdiv2; local 205 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 207 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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H A D | clk_rk322x.c | 36 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 54 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 58 div->postdiv2, vco_hz, output_hz); 71 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 178 uint32_t refdiv, fbdiv, postdiv1, postdiv2; local 207 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 209 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 328 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 332 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; 336 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 [all...] |
H A D | clk_rk3399.c | 44 u32 postdiv2; member in struct:pll_div 55 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; 329 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 332 "postdiv2=%d, vco=%u khz, output=%u khz\n", 334 div->postdiv2, vco_khz, output_khz); 355 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 371 u32 postdiv1, postdiv2 = 1; local 386 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 387 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 390 vco_khz = freq_khz * postdiv1 * postdiv2; [all...] |
H A D | clk_rv1108.c | 39 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 78 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 82 div->postdiv2, vco_hz, output_hz); 101 div->postdiv2 << POSTDIV2_SHIFT | 125 uint32_t refdiv, fbdiv, postdiv1, postdiv2; local 138 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; 140 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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H A D | clk_px30.c | 42 .postdiv2 = _postdiv2, \ 101 u32 postdiv1, postdiv2 = 1; local 116 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 117 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 120 vco_khz = rate_khz * postdiv1 * postdiv2; 123 postdiv2 > max_postdiv2) { 130 rate->postdiv2 = postdiv2; 220 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; 224 rate->postdiv2, vco_h 263 u32 refdiv, fbdiv, postdiv1, postdiv2; local [all...] |
H A D | clk_rk3328.c | 28 u32 postdiv2; member in struct:pll_div 39 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; 250 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 253 postdiv2=%d, vco=%u khz, output=%u khz\n", 255 div->postdiv2, vco_khz, output_khz); 276 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
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/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | clock.h | 67 .postdiv2 = _postdiv2, \ 91 unsigned int postdiv2; member in struct:rockchip_pll_rate_table
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H A D | cru_rk3036.h | 62 u32 postdiv2; member in struct:pll_div
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H A D | cru_rv1108.h | 59 u32 postdiv2; member in struct:pll_div
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H A D | cru_rk322x.h | 63 u32 postdiv2; member in struct:pll_div
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H A D | cru_rk3128.h | 69 u32 postdiv2; member in struct:pll_div
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H A D | cru_rv1126.h | 142 unsigned int postdiv2; member in struct:pll_rate_table
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H A D | cru_px30.h | 105 unsigned int postdiv2; member in struct:pll_rate_table
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H A D | cru_rk3568.h | 119 unsigned int postdiv2; member in struct:pll_rate_table
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/u-boot/drivers/ram/rockchip/ |
H A D | sdram_px30.c | 155 unsigned int refdiv, postdiv1, postdiv2, fbdiv; local 162 postdiv2 = 2; 165 postdiv2 = 1; 168 postdiv2 = 1; 171 postdiv2 = 1; 174 postdiv2 = 1; 177 postdiv2 = 1; 179 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; 184 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
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H A D | sdram_rk3328.c | 78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; local 85 postdiv2 = 2; 88 postdiv2 = 1; 91 postdiv2 = 1; 94 postdiv2 = 1; 97 postdiv2 = 1; 100 postdiv2 = 1; 102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; 106 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
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H A D | sdram_rv1126.c | 301 unsigned int refdiv, postdiv1, postdiv2, fbdiv; local 316 postdiv2 = 4; 319 postdiv2 = 4; 322 postdiv2 = 2; 325 postdiv2 = 2; 328 postdiv2 = 1; 331 postdiv2 = 1; 333 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; 352 writel(DSMPD(dsmpd) | POSTDIV2(postdiv2) | REFDIV(refdiv),
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/u-boot/arch/arm/mach-rockchip/rk3036/ |
H A D | sdram_rk3036.c | 38 * refdiv, fbdiv, postdiv1, postdiv2 343 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
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