1// SPDX-License-Identifier: GPL-2.0 2/* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#include <common.h> 7#include <clk-uclass.h> 8#include <dm.h> 9#include <errno.h> 10#include <log.h> 11#include <malloc.h> 12#include <syscon.h> 13#include <asm/arch-rockchip/clock.h> 14#include <asm/arch-rockchip/cru_rk322x.h> 15#include <asm/arch-rockchip/hardware.h> 16#include <dm/device-internal.h> 17#include <dm/lists.h> 18#include <dt-bindings/clock/rk3228-cru.h> 19#include <linux/bitops.h> 20#include <linux/delay.h> 21#include <linux/log2.h> 22#include <linux/stringify.h> 23 24enum { 25 VCO_MAX_HZ = 3200U * 1000000, 26 VCO_MIN_HZ = 800 * 1000000, 27 OUTPUT_MAX_HZ = 3200U * 1000000, 28 OUTPUT_MIN_HZ = 24 * 1000000, 29}; 30 31#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 32 33#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 34 .refdiv = _refdiv,\ 35 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \ 36 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 37 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \ 38 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \ 39 #hz "Hz cannot be hit with PLL "\ 40 "divisors on line " __stringify(__LINE__)); 41 42/* use integer mode*/ 43static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 44static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 45 46static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, 47 const struct pll_div *div) 48{ 49 int pll_id = rk_pll_id(clk_id); 50 struct rk322x_pll *pll = &cru->pll[pll_id]; 51 52 /* All PLLs have same VCO and output frequency range restrictions. */ 53 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 54 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 55 56 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 57 pll, div->fbdiv, div->refdiv, div->postdiv1, 58 div->postdiv2, vco_hz, output_hz); 59 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 60 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 61 62 /* use integer mode */ 63 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 64 /* Power down */ 65 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 66 67 rk_clrsetreg(&pll->con0, 68 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 69 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 70 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 71 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 72 div->refdiv << PLL_REFDIV_SHIFT)); 73 74 /* Power Up */ 75 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 76 77 /* waiting for pll lock */ 78 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 79 udelay(1); 80 81 return 0; 82} 83 84static void rkclk_init(struct rk322x_cru *cru) 85{ 86 u32 aclk_div; 87 u32 hclk_div; 88 u32 pclk_div; 89 90 /* pll enter slow-mode */ 91 rk_clrsetreg(&cru->cru_mode_con, 92 GPLL_MODE_MASK | APLL_MODE_MASK, 93 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 94 APLL_MODE_SLOW << APLL_MODE_SHIFT); 95 96 /* init pll */ 97 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 98 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 99 100 /* 101 * select apll as cpu/core clock pll source and 102 * set up dependent divisors for PERI and ACLK clocks. 103 * core hz : apll = 1:1 104 */ 105 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 106 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); 107 108 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 109 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); 110 111 rk_clrsetreg(&cru->cru_clksel_con[0], 112 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 113 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 114 0 << CORE_DIV_CON_SHIFT); 115 116 rk_clrsetreg(&cru->cru_clksel_con[1], 117 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 118 aclk_div << CORE_ACLK_DIV_SHIFT | 119 pclk_div << CORE_PERI_DIV_SHIFT); 120 121 /* 122 * select gpll as pd_bus bus clock source and 123 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 124 */ 125 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 126 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 127 128 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; 129 assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7); 130 131 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; 132 assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3); 133 134 rk_clrsetreg(&cru->cru_clksel_con[0], 135 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 136 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 137 aclk_div << BUS_ACLK_DIV_SHIFT); 138 139 rk_clrsetreg(&cru->cru_clksel_con[1], 140 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 141 pclk_div << BUS_PCLK_DIV_SHIFT | 142 hclk_div << BUS_HCLK_DIV_SHIFT); 143 144 /* 145 * select gpll as pd_peri bus clock source and 146 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 147 */ 148 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 149 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 150 151 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 152 assert((1 << hclk_div) * PERI_HCLK_HZ == 153 PERI_ACLK_HZ && (hclk_div < 0x4)); 154 155 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 156 assert((1 << pclk_div) * PERI_PCLK_HZ == 157 PERI_ACLK_HZ && pclk_div < 0x8); 158 159 rk_clrsetreg(&cru->cru_clksel_con[10], 160 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 161 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 162 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 163 pclk_div << PERI_PCLK_DIV_SHIFT | 164 hclk_div << PERI_HCLK_DIV_SHIFT | 165 aclk_div << PERI_ACLK_DIV_SHIFT); 166 167 /* PLL enter normal-mode */ 168 rk_clrsetreg(&cru->cru_mode_con, 169 GPLL_MODE_MASK | APLL_MODE_MASK, 170 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 171 APLL_MODE_NORM << APLL_MODE_SHIFT); 172} 173 174/* Get pll rate by id */ 175static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru, 176 enum rk_clk_id clk_id) 177{ 178 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 179 uint32_t con; 180 int pll_id = rk_pll_id(clk_id); 181 struct rk322x_pll *pll = &cru->pll[pll_id]; 182 static u8 clk_shift[CLK_COUNT] = { 183 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 184 GPLL_MODE_SHIFT, 0xff 185 }; 186 static u32 clk_mask[CLK_COUNT] = { 187 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, 188 GPLL_MODE_MASK, 0xff 189 }; 190 uint shift; 191 uint mask; 192 193 con = readl(&cru->cru_mode_con); 194 shift = clk_shift[clk_id]; 195 mask = clk_mask[clk_id]; 196 197 switch ((con & mask) >> shift) { 198 case GPLL_MODE_SLOW: 199 return OSC_HZ; 200 case GPLL_MODE_NORM: 201 202 /* normal mode */ 203 con = readl(&pll->con0); 204 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 205 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 206 con = readl(&pll->con1); 207 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 208 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 209 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 210 default: 211 return 32768; 212 } 213} 214 215static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, 216 int periph) 217{ 218 uint src_rate; 219 uint div, mux; 220 u32 con; 221 222 switch (periph) { 223 case HCLK_EMMC: 224 case SCLK_EMMC: 225 case SCLK_EMMC_SAMPLE: 226 con = readl(&cru->cru_clksel_con[11]); 227 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 228 con = readl(&cru->cru_clksel_con[12]); 229 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 230 break; 231 case HCLK_SDMMC: 232 case SCLK_SDMMC: 233 con = readl(&cru->cru_clksel_con[11]); 234 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 235 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 236 break; 237 default: 238 return -EINVAL; 239 } 240 241 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 242 return DIV_TO_RATE(src_rate, div) / 2; 243} 244 245static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) 246{ 247 ulong ret; 248 249 /* 250 * The gmac clock can be derived either from an external clock 251 * or can be generated from internally by a divider from SCLK_MAC. 252 */ 253 if (readl(&cru->cru_clksel_con[5]) & BIT(5)) { 254 /* An external clock will always generate the right rate... */ 255 ret = freq; 256 } else { 257 u32 con = readl(&cru->cru_clksel_con[5]); 258 ulong pll_rate; 259 u8 div; 260 261 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) 262 pll_rate = GPLL_HZ; 263 else 264 /* CPLL is not set */ 265 return -EPERM; 266 267 div = DIV_ROUND_UP(pll_rate, freq) - 1; 268 if (div <= 0x1f) 269 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK, 270 div << CLK_MAC_DIV_SHIFT); 271 else 272 debug("Unsupported div for gmac:%d\n", div); 273 274 return DIV_TO_RATE(pll_rate, div); 275 } 276 277 return ret; 278} 279 280static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, 281 int periph, uint freq) 282{ 283 int src_clk_div; 284 int mux; 285 286 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 287 288 /* mmc clock defaulg div 2 internal, need provide double in cru */ 289 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 290 291 if (src_clk_div > 128) { 292 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 293 assert(src_clk_div - 1 < 128); 294 mux = EMMC_SEL_24M; 295 } else { 296 mux = EMMC_SEL_GPLL; 297 } 298 299 switch (periph) { 300 case HCLK_EMMC: 301 case SCLK_EMMC: 302 case SCLK_EMMC_SAMPLE: 303 rk_clrsetreg(&cru->cru_clksel_con[11], 304 EMMC_PLL_MASK, 305 mux << EMMC_PLL_SHIFT); 306 rk_clrsetreg(&cru->cru_clksel_con[12], 307 EMMC_DIV_MASK, 308 (src_clk_div - 1) << EMMC_DIV_SHIFT); 309 break; 310 case HCLK_SDMMC: 311 case SCLK_SDMMC: 312 rk_clrsetreg(&cru->cru_clksel_con[11], 313 MMC0_PLL_MASK | MMC0_DIV_MASK, 314 mux << MMC0_PLL_SHIFT | 315 (src_clk_div - 1) << MMC0_DIV_SHIFT); 316 break; 317 default: 318 return -EINVAL; 319 } 320 321 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 322} 323 324static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate) 325{ 326 struct pll_div dpll_cfg; 327 328 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 329 switch (set_rate) { 330 case 400*MHz: 331 dpll_cfg = (struct pll_div) 332 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; 333 break; 334 case 600*MHz: 335 dpll_cfg = (struct pll_div) 336 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; 337 break; 338 case 800*MHz: 339 dpll_cfg = (struct pll_div) 340 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 341 break; 342 } 343 344 /* pll enter slow-mode */ 345 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 346 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 347 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg); 348 /* PLL enter normal-mode */ 349 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 350 DPLL_MODE_NORM << DPLL_MODE_SHIFT); 351 352 return set_rate; 353} 354static ulong rk322x_clk_get_rate(struct clk *clk) 355{ 356 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); 357 ulong rate, gclk_rate; 358 359 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 360 switch (clk->id) { 361 case 0 ... 63: 362 rate = rkclk_pll_get_rate(priv->cru, clk->id); 363 break; 364 case HCLK_EMMC: 365 case SCLK_EMMC: 366 case HCLK_SDMMC: 367 case SCLK_SDMMC: 368 rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); 369 break; 370 default: 371 return -ENOENT; 372 } 373 374 return rate; 375} 376 377static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) 378{ 379 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); 380 ulong new_rate, gclk_rate; 381 382 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 383 switch (clk->id) { 384 case HCLK_EMMC: 385 case SCLK_EMMC: 386 case HCLK_SDMMC: 387 case SCLK_SDMMC: 388 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 389 clk->id, rate); 390 break; 391 case CLK_DDR: 392 new_rate = rk322x_ddr_set_clk(priv->cru, rate); 393 break; 394 case SCLK_MAC: 395 new_rate = rk322x_mac_set_clk(priv->cru, rate); 396 break; 397 case PLL_GPLL: 398 return 0; 399 default: 400 return -ENOENT; 401 } 402 403 return new_rate; 404} 405 406static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent) 407{ 408 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); 409 struct rk322x_cru *cru = priv->cru; 410 411 /* 412 * If the requested parent is in the same clock-controller and the id 413 * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock. 414 */ 415 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) { 416 debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__); 417 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0); 418 return 0; 419 } 420 421 /* 422 * If the requested parent is in the same clock-controller and the id 423 * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock. 424 */ 425 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) { 426 debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__); 427 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5)); 428 return 0; 429 } 430 431 return -EINVAL; 432} 433 434static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent) 435{ 436 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); 437 const char *clock_output_name; 438 struct rk322x_cru *cru = priv->cru; 439 int ret; 440 441 ret = dev_read_string_index(parent->dev, "clock-output-names", 442 parent->id, &clock_output_name); 443 if (ret < 0) 444 return -ENODATA; 445 446 if (!strcmp(clock_output_name, "ext_gmac")) { 447 debug("%s: switching gmac extclk to ext_gmac\n", __func__); 448 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0); 449 return 0; 450 } else if (!strcmp(clock_output_name, "phy_50m_out")) { 451 debug("%s: switching gmac extclk to phy_50m_out\n", __func__); 452 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10)); 453 return 0; 454 } 455 456 return -EINVAL; 457} 458 459static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent) 460{ 461 switch (clk->id) { 462 case SCLK_MAC: 463 return rk322x_gmac_set_parent(clk, parent); 464 case SCLK_MAC_EXTCLK: 465 return rk322x_gmac_extclk_set_parent(clk, parent); 466 } 467 468 debug("%s: unsupported clk %ld\n", __func__, clk->id); 469 return -ENOENT; 470} 471 472static struct clk_ops rk322x_clk_ops = { 473 .get_rate = rk322x_clk_get_rate, 474 .set_rate = rk322x_clk_set_rate, 475 .set_parent = rk322x_clk_set_parent, 476}; 477 478static int rk322x_clk_of_to_plat(struct udevice *dev) 479{ 480 struct rk322x_clk_priv *priv = dev_get_priv(dev); 481 482 priv->cru = dev_read_addr_ptr(dev); 483 484 return 0; 485} 486 487static int rk322x_clk_probe(struct udevice *dev) 488{ 489 struct rk322x_clk_priv *priv = dev_get_priv(dev); 490 491 rkclk_init(priv->cru); 492 493 return 0; 494} 495 496static int rk322x_clk_bind(struct udevice *dev) 497{ 498 int ret; 499 struct udevice *sys_child; 500 struct sysreset_reg *priv; 501 502 /* The reset driver does not have a device node, so bind it here */ 503 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 504 &sys_child); 505 if (ret) { 506 debug("Warning: No sysreset driver: ret=%d\n", ret); 507 } else { 508 priv = malloc(sizeof(struct sysreset_reg)); 509 priv->glb_srst_fst_value = offsetof(struct rk322x_cru, 510 cru_glb_srst_fst_value); 511 priv->glb_srst_snd_value = offsetof(struct rk322x_cru, 512 cru_glb_srst_snd_value); 513 dev_set_priv(sys_child, priv); 514 } 515 516#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) 517 ret = offsetof(struct rk322x_cru, cru_softrst_con[0]); 518 ret = rockchip_reset_bind(dev, ret, 9); 519 if (ret) 520 debug("Warning: software reset driver bind failed\n"); 521#endif 522 523 return 0; 524} 525 526static const struct udevice_id rk322x_clk_ids[] = { 527 { .compatible = "rockchip,rk3228-cru" }, 528 { } 529}; 530 531U_BOOT_DRIVER(rockchip_rk322x_cru) = { 532 .name = "clk_rk322x", 533 .id = UCLASS_CLK, 534 .of_match = rk322x_clk_ids, 535 .priv_auto = sizeof(struct rk322x_clk_priv), 536 .of_to_plat = rk322x_clk_of_to_plat, 537 .ops = &rk322x_clk_ops, 538 .bind = rk322x_clk_bind, 539 .probe = rk322x_clk_probe, 540}; 541