1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 * Author: Andy Yan <andy.yan@rock-chips.com> 5 */ 6#ifndef _ASM_ARCH_CRU_RV1108_H 7#define _ASM_ARCH_CRU_RV1108_H 8 9#ifndef __ASSEMBLY__ 10#include <linux/bitops.h> 11#endif 12 13#define OSC_HZ (24 * 1000 * 1000) 14 15#define APLL_HZ (600 * 1000000) 16#define GPLL_HZ (1188 * 1000000) 17#define ACLK_PERI_HZ (148500000) 18#define HCLK_PERI_HZ (148500000) 19#define PCLK_PERI_HZ (74250000) 20#define ACLK_BUS_HZ (148500000) 21 22struct rv1108_clk_priv { 23 struct rv1108_cru *cru; 24 ulong rate; 25}; 26 27struct rv1108_cru { 28 struct rv1108_pll { 29 unsigned int con0; 30 unsigned int con1; 31 unsigned int con2; 32 unsigned int con3; 33 unsigned int con4; 34 unsigned int con5; 35 unsigned int reserved[2]; 36 } pll[3]; 37 unsigned int clksel_con[46]; 38 unsigned int reserved1[2]; 39 unsigned int clkgate_con[20]; 40 unsigned int reserved2[4]; 41 unsigned int softrst_con[13]; 42 unsigned int reserved3[3]; 43 unsigned int glb_srst_fst_val; 44 unsigned int glb_srst_snd_val; 45 unsigned int glb_cnt_th; 46 unsigned int misc_con; 47 unsigned int glb_rst_con; 48 unsigned int glb_rst_st; 49 unsigned int sdmmc_con[2]; 50 unsigned int sdio_con[2]; 51 unsigned int emmc_con[2]; 52}; 53check_member(rv1108_cru, emmc_con[1], 0x01ec); 54 55struct pll_div { 56 u32 refdiv; 57 u32 fbdiv; 58 u32 postdiv1; 59 u32 postdiv2; 60 u32 frac; 61}; 62 63enum { 64 /* PLL CON0 */ 65 FBDIV_MASK = 0xfff, 66 FBDIV_SHIFT = 0, 67 68 /* PLL CON1 */ 69 POSTDIV2_SHIFT = 12, 70 POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, 71 POSTDIV1_SHIFT = 8, 72 POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, 73 REFDIV_MASK = 0x3f, 74 REFDIV_SHIFT = 0, 75 76 /* PLL CON2 */ 77 LOCK_STA_SHIFT = 31, 78 LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, 79 FRACDIV_MASK = 0xffffff, 80 FRACDIV_SHIFT = 0, 81 82 /* PLL CON3 */ 83 WORK_MODE_SHIFT = 8, 84 WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, 85 WORK_MODE_SLOW = 0, 86 WORK_MODE_NORMAL = 1, 87 DSMPD_SHIFT = 3, 88 DSMPD_MASK = 1 << DSMPD_SHIFT, 89 INTEGER_MODE = 1, 90 GLOBAL_POWER_DOWN_SHIFT = 0, 91 GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT, 92 GLOBAL_POWER_DOWN = 1, 93 GLOBAL_POWER_UP = 0, 94 95 /* CLKSEL0_CON */ 96 CORE_PLL_SEL_SHIFT = 8, 97 CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, 98 CORE_PLL_SEL_APLL = 0, 99 CORE_PLL_SEL_GPLL = 1, 100 CORE_PLL_SEL_DPLL = 2, 101 CORE_CLK_DIV_SHIFT = 0, 102 CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, 103 104 /* CLKSEL_CON1 */ 105 PCLK_DBG_DIV_CON_SHIFT = 4, 106 PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT, 107 ACLK_CORE_DIV_CON_SHIFT = 0, 108 ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT, 109 110 /* CLKSEL_CON2 */ 111 ACLK_BUS_PLL_SEL_SHIFT = 8, 112 ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT, 113 ACLK_BUS_PLL_SEL_GPLL = 0, 114 ACLK_BUS_PLL_SEL_APLL = 1, 115 ACLK_BUS_PLL_SEL_DPLL = 2, 116 ACLK_BUS_DIV_CON_SHIFT = 0, 117 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 118 ACLK_BUS_DIV_CON_WIDTH = 5, 119 120 /* CLKSEL_CON3 */ 121 PCLK_BUS_DIV_CON_SHIFT = 8, 122 PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, 123 HCLK_BUS_DIV_CON_SHIFT = 0, 124 HCLK_BUS_DIV_CON_MASK = 0x1f, 125 126 /* CLKSEL_CON4 */ 127 CLK_DDR_PLL_SEL_SHIFT = 8, 128 CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT, 129 CLK_DDR_DIV_CON_SHIFT = 0, 130 CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT, 131 132 /* CLKSEL_CON19 */ 133 CLK_I2C1_PLL_SEL_SHIFT = 15, 134 CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, 135 CLK_I2C1_PLL_SEL_DPLL = 0, 136 CLK_I2C1_PLL_SEL_GPLL = 1, 137 CLK_I2C1_DIV_CON_SHIFT = 8, 138 CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT, 139 CLK_I2C0_PLL_SEL_SHIFT = 7, 140 CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, 141 CLK_I2C0_DIV_CON_SHIFT = 0, 142 CLK_I2C0_DIV_CON_MASK = 0x7f, 143 I2C_DIV_CON_WIDTH = 7, 144 145 /* CLKSEL_CON20 */ 146 CLK_I2C3_PLL_SEL_SHIFT = 15, 147 CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, 148 CLK_I2C3_PLL_SEL_DPLL = 0, 149 CLK_I2C3_PLL_SEL_GPLL = 1, 150 CLK_I2C3_DIV_CON_SHIFT = 8, 151 CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT, 152 CLK_I2C2_PLL_SEL_SHIFT = 7, 153 CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, 154 CLK_I2C2_DIV_CON_SHIFT = 0, 155 CLK_I2C2_DIV_CON_MASK = 0x7f, 156 157 /* CLKSEL_CON22 */ 158 CLK_SARADC_DIV_CON_SHIFT= 0, 159 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), 160 CLK_SARADC_DIV_CON_WIDTH= 10, 161 162 /* CLKSEL_CON23 */ 163 ACLK_PERI_PLL_SEL_SHIFT = 15, 164 ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT, 165 ACLK_PERI_PLL_SEL_GPLL = 0, 166 ACLK_PERI_PLL_SEL_DPLL = 1, 167 PCLK_PERI_DIV_CON_SHIFT = 10, 168 PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, 169 HCLK_PERI_DIV_CON_SHIFT = 5, 170 HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, 171 ACLK_PERI_DIV_CON_SHIFT = 0, 172 ACLK_PERI_DIV_CON_MASK = 0x1f, 173 PERI_DIV_CON_WIDTH = 5, 174 175 /* CLKSEL24_CON */ 176 MAC_PLL_SEL_SHIFT = 12, 177 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 178 MAC_PLL_SEL_APLL = 0, 179 MAC_PLL_SEL_GPLL = 1, 180 RMII_EXTCLK_SEL_SHIFT = 8, 181 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 182 MAC_CLK_DIV_MASK = 0x1f, 183 MAC_CLK_DIV_SHIFT = 0, 184 185 /* CLKSEL25_CON */ 186 EMMC_PLL_SEL_SHIFT = 12, 187 EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT, 188 EMMC_PLL_SEL_DPLL = 0, 189 EMMC_PLL_SEL_GPLL, 190 EMMC_PLL_SEL_OSC, 191 192 /* CLKSEL26_CON */ 193 EMMC_CLK_DIV_SHIFT = 8, 194 EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT, 195 196 /* CLKSEL27_CON */ 197 SFC_PLL_SEL_SHIFT = 7, 198 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 199 SFC_PLL_SEL_DPLL = 0, 200 SFC_PLL_SEL_GPLL = 1, 201 SFC_CLK_DIV_SHIFT = 0, 202 SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, 203 204 /* CLKSEL28_CON */ 205 ACLK_VIO1_PLL_SEL_SHIFT = 14, 206 ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT, 207 VIO_PLL_SEL_DPLL = 0, 208 VIO_PLL_SEL_GPLL = 1, 209 ACLK_VIO1_CLK_DIV_SHIFT = 8, 210 ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT, 211 CLK_VIO_DIV_CON_WIDTH = 5, 212 ACLK_VIO0_PLL_SEL_SHIFT = 6, 213 ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT, 214 ACLK_VIO0_CLK_DIV_SHIFT = 0, 215 ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT, 216 217 /* CLKSEL29_CON */ 218 PCLK_VIO_CLK_DIV_SHIFT = 8, 219 PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT, 220 HCLK_VIO_CLK_DIV_SHIFT = 0, 221 HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT, 222 223 /* CLKSEL32_CON */ 224 DCLK_VOP_SEL_SHIFT = 7, 225 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 226 DCLK_VOP_SEL_HDMI = 0, 227 DCLK_VOP_SEL_PLL = 1, 228 DCLK_VOP_PLL_SEL_SHIFT = 6, 229 DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, 230 DCLK_VOP_PLL_SEL_GPLL = 0, 231 DCLK_VOP_PLL_SEL_DPLL = 1, 232 DCLK_VOP_CLK_DIV_SHIFT = 0, 233 DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT, 234 DCLK_VOP_DIV_CON_WIDTH = 6, 235 236 /* SOFTRST1_CON*/ 237 DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0, 238 DDRPHY_SRSTN_CLKDIV_REQ = 1, 239 DDRPHY_SRSTN_CLKDIV_DIS = 0, 240 DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT, 241 DDRPHY_SRSTN_REQ_SHIFT = 1, 242 DDRPHY_SRSTN_REQ = 1, 243 DDRPHY_SRSTN_DIS = 0, 244 DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT, 245 DDRPHY_PSRSTN_REQ_SHIFT = 2, 246 DDRPHY_PSRSTN_REQ = 1, 247 DDRPHY_PSRSTN_DIS = 0, 248 DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT, 249 250 /* SOFTRST2_CON*/ 251 DDRUPCTL_PSRSTN_REQ_SHIFT = 0, 252 DDRUPCTL_PSRSTN_REQ = 1, 253 DDRUPCTL_PSRSTN_DIS = 0, 254 DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT, 255 DDRUPCTL_NSRSTN_REQ_SHIFT = 1, 256 DDRUPCTL_NSRSTN_REQ = 1, 257 DDRUPCTL_NSRSTN_DIS = 0, 258 DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT, 259}; 260#endif 261