1// SPDX-License-Identifier: GPL-2.0 2/* 3 * (C) Copyright 2015 Google, Inc 4 */ 5 6#include <common.h> 7#include <clk-uclass.h> 8#include <dm.h> 9#include <errno.h> 10#include <log.h> 11#include <malloc.h> 12#include <syscon.h> 13#include <asm/arch-rockchip/clock.h> 14#include <asm/arch-rockchip/cru_rk3036.h> 15#include <asm/arch-rockchip/hardware.h> 16#include <dm/device-internal.h> 17#include <dm/lists.h> 18#include <dt-bindings/clock/rk3036-cru.h> 19#include <linux/delay.h> 20#include <linux/log2.h> 21#include <linux/stringify.h> 22 23enum { 24 VCO_MAX_HZ = 2400U * 1000000, 25 VCO_MIN_HZ = 600 * 1000000, 26 OUTPUT_MAX_HZ = 2400U * 1000000, 27 OUTPUT_MIN_HZ = 24 * 1000000, 28}; 29 30#define RATE_TO_DIV(input_rate, output_rate) \ 31 ((input_rate) / (output_rate) - 1); 32 33#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 34 35#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 36 .refdiv = _refdiv,\ 37 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 38 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 39 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ 40 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ 41 #hz "Hz cannot be hit with PLL "\ 42 "divisors on line " __stringify(__LINE__)); 43 44/* use integer mode*/ 45static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 46static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 47 48static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, 49 const struct pll_div *div) 50{ 51 int pll_id = rk_pll_id(clk_id); 52 struct rk3036_pll *pll = &cru->pll[pll_id]; 53 54 /* All PLLs have same VCO and output frequency range restrictions. */ 55 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 56 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 57 58 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ 59 vco=%u Hz, output=%u Hz\n", 60 pll, div->fbdiv, div->refdiv, div->postdiv1, 61 div->postdiv2, vco_hz, output_hz); 62 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 63 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 64 65 /* use integer mode */ 66 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 67 68 rk_clrsetreg(&pll->con0, 69 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 70 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 71 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 72 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 73 div->refdiv << PLL_REFDIV_SHIFT)); 74 75 /* waiting for pll lock */ 76 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 77 udelay(1); 78 79 return 0; 80} 81 82static void rkclk_init(struct rk3036_cru *cru) 83{ 84 u32 aclk_div; 85 u32 hclk_div; 86 u32 pclk_div; 87 88 /* pll enter slow-mode */ 89 rk_clrsetreg(&cru->cru_mode_con, 90 GPLL_MODE_MASK | APLL_MODE_MASK, 91 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 92 APLL_MODE_SLOW << APLL_MODE_SHIFT); 93 94 /* init pll */ 95 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 96 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 97 98 /* 99 * select apll as cpu/core clock pll source and 100 * set up dependent divisors for PERI and ACLK clocks. 101 * core hz : apll = 1:1 102 */ 103 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 104 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); 105 106 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 107 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); 108 109 rk_clrsetreg(&cru->cru_clksel_con[0], 110 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 111 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 112 0 << CORE_DIV_CON_SHIFT); 113 114 rk_clrsetreg(&cru->cru_clksel_con[1], 115 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 116 aclk_div << CORE_ACLK_DIV_SHIFT | 117 pclk_div << CORE_PERI_DIV_SHIFT); 118 119 /* 120 * select apll as pd_bus bus clock source and 121 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 122 */ 123 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 124 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 125 126 pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; 127 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); 128 129 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; 130 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); 131 132 rk_clrsetreg(&cru->cru_clksel_con[0], 133 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 134 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 135 aclk_div << BUS_ACLK_DIV_SHIFT); 136 137 rk_clrsetreg(&cru->cru_clksel_con[1], 138 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 139 pclk_div << BUS_PCLK_DIV_SHIFT | 140 hclk_div << BUS_HCLK_DIV_SHIFT); 141 142 /* 143 * select gpll as pd_peri bus clock source and 144 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 145 */ 146 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 147 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 148 149 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 150 assert((1 << hclk_div) * PERI_HCLK_HZ == 151 PERI_ACLK_HZ && (hclk_div < 0x4)); 152 153 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 154 assert((1 << pclk_div) * PERI_PCLK_HZ == 155 PERI_ACLK_HZ && pclk_div < 0x8); 156 157 rk_clrsetreg(&cru->cru_clksel_con[10], 158 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 159 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 160 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 161 pclk_div << PERI_PCLK_DIV_SHIFT | 162 hclk_div << PERI_HCLK_DIV_SHIFT | 163 aclk_div << PERI_ACLK_DIV_SHIFT); 164 165 /* PLL enter normal-mode */ 166 rk_clrsetreg(&cru->cru_mode_con, 167 GPLL_MODE_MASK | APLL_MODE_MASK, 168 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 169 APLL_MODE_NORM << APLL_MODE_SHIFT); 170} 171 172/* Get pll rate by id */ 173static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 174 enum rk_clk_id clk_id) 175{ 176 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 177 uint32_t con; 178 int pll_id = rk_pll_id(clk_id); 179 struct rk3036_pll *pll = &cru->pll[pll_id]; 180 static u8 clk_shift[CLK_COUNT] = { 181 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 182 GPLL_MODE_SHIFT, 0xff 183 }; 184 static u32 clk_mask[CLK_COUNT] = { 185 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, 186 GPLL_MODE_MASK, 0xffffffff 187 }; 188 uint shift; 189 uint mask; 190 191 con = readl(&cru->cru_mode_con); 192 shift = clk_shift[clk_id]; 193 mask = clk_mask[clk_id]; 194 195 switch ((con & mask) >> shift) { 196 case GPLL_MODE_SLOW: 197 return OSC_HZ; 198 case GPLL_MODE_NORM: 199 200 /* normal mode */ 201 con = readl(&pll->con0); 202 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 203 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 204 con = readl(&pll->con1); 205 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 206 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 207 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 208 case GPLL_MODE_DEEP: 209 default: 210 return 32768; 211 } 212} 213 214static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, 215 int periph) 216{ 217 uint src_rate; 218 uint div, mux; 219 u32 con; 220 221 switch (periph) { 222 case HCLK_EMMC: 223 case SCLK_EMMC: 224 con = readl(&cru->cru_clksel_con[12]); 225 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 226 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 227 break; 228 case HCLK_SDIO: 229 case SCLK_SDIO: 230 con = readl(&cru->cru_clksel_con[12]); 231 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 232 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 233 break; 234 default: 235 return -EINVAL; 236 } 237 238 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 239 return DIV_TO_RATE(src_rate, div) / 2; 240} 241 242static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, 243 int periph, uint freq) 244{ 245 int src_clk_div; 246 int mux; 247 248 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 249 250 /* mmc clock auto divide 2 in internal */ 251 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 252 253 if (src_clk_div > 128) { 254 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 255 assert(src_clk_div - 1 < 128); 256 mux = EMMC_SEL_24M; 257 } else { 258 mux = EMMC_SEL_GPLL; 259 } 260 261 switch (periph) { 262 case HCLK_EMMC: 263 case SCLK_EMMC: 264 rk_clrsetreg(&cru->cru_clksel_con[12], 265 EMMC_PLL_MASK | EMMC_DIV_MASK, 266 mux << EMMC_PLL_SHIFT | 267 (src_clk_div - 1) << EMMC_DIV_SHIFT); 268 break; 269 case HCLK_SDIO: 270 case SCLK_SDIO: 271 rk_clrsetreg(&cru->cru_clksel_con[11], 272 MMC0_PLL_MASK | MMC0_DIV_MASK, 273 mux << MMC0_PLL_SHIFT | 274 (src_clk_div - 1) << MMC0_DIV_SHIFT); 275 break; 276 default: 277 return -EINVAL; 278 } 279 280 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 281} 282 283static ulong rk3036_clk_get_rate(struct clk *clk) 284{ 285 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 286 287 switch (clk->id) { 288 case 0 ... 63: 289 return rkclk_pll_get_rate(priv->cru, clk->id); 290 default: 291 return -ENOENT; 292 } 293} 294 295static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate) 296{ 297 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 298 ulong new_rate, gclk_rate; 299 300 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 301 switch (clk->id) { 302 case 0 ... 63: 303 return 0; 304 case HCLK_EMMC: 305 case SCLK_EMMC: 306 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 307 clk->id, rate); 308 break; 309 default: 310 return -ENOENT; 311 } 312 313 return new_rate; 314} 315 316static struct clk_ops rk3036_clk_ops = { 317 .get_rate = rk3036_clk_get_rate, 318 .set_rate = rk3036_clk_set_rate, 319}; 320 321static int rk3036_clk_of_to_plat(struct udevice *dev) 322{ 323 struct rk3036_clk_priv *priv = dev_get_priv(dev); 324 325 priv->cru = dev_read_addr_ptr(dev); 326 327 return 0; 328} 329 330static int rk3036_clk_probe(struct udevice *dev) 331{ 332 struct rk3036_clk_priv *priv = dev_get_priv(dev); 333 334 rkclk_init(priv->cru); 335 336 return 0; 337} 338 339static int rk3036_clk_bind(struct udevice *dev) 340{ 341 int ret; 342 struct udevice *sys_child; 343 struct sysreset_reg *priv; 344 345 /* The reset driver does not have a device node, so bind it here */ 346 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 347 &sys_child); 348 if (ret) { 349 debug("Warning: No sysreset driver: ret=%d\n", ret); 350 } else { 351 priv = malloc(sizeof(struct sysreset_reg)); 352 priv->glb_srst_fst_value = offsetof(struct rk3036_cru, 353 cru_glb_srst_fst_value); 354 priv->glb_srst_snd_value = offsetof(struct rk3036_cru, 355 cru_glb_srst_snd_value); 356 dev_set_priv(sys_child, priv); 357 } 358 359#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) 360 ret = offsetof(struct rk3036_cru, cru_softrst_con[0]); 361 ret = rockchip_reset_bind(dev, ret, 9); 362 if (ret) 363 debug("Warning: software reset driver bind failed\n"); 364#endif 365 366 return 0; 367} 368 369static const struct udevice_id rk3036_clk_ids[] = { 370 { .compatible = "rockchip,rk3036-cru" }, 371 { } 372}; 373 374U_BOOT_DRIVER(rockchip_rk3036_cru) = { 375 .name = "clk_rk3036", 376 .id = UCLASS_CLK, 377 .of_match = rk3036_clk_ids, 378 .priv_auto = sizeof(struct rk3036_clk_priv), 379 .of_to_plat = rk3036_clk_of_to_plat, 380 .ops = &rk3036_clk_ops, 381 .bind = rk3036_clk_bind, 382 .probe = rk3036_clk_probe, 383}; 384