1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7#ifndef _ASM_ARCH_CRU_RV1126_H 8#define _ASM_ARCH_CRU_RV1126_H 9 10#define MHz 1000000 11#define KHz 1000 12#define OSC_HZ (24 * MHz) 13 14#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 15#define APLL_HZ (1008 * MHz) 16#else 17#define APLL_HZ (816 * MHz) 18#endif 19#define GPLL_HZ (1188 * MHz) 20#define CPLL_HZ (500 * MHz) 21#define HPLL_HZ (1400 * MHz) 22#define PCLK_PDPMU_HZ (100 * MHz) 23#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 24#define ACLK_PDBUS_HZ (396 * MHz) 25#else 26#define ACLK_PDBUS_HZ (500 * MHz) 27#endif 28#define HCLK_PDBUS_HZ (200 * MHz) 29#define PCLK_PDBUS_HZ (100 * MHz) 30#define ACLK_PDPHP_HZ (300 * MHz) 31#define HCLK_PDPHP_HZ (200 * MHz) 32#define HCLK_PDCORE_HZ (200 * MHz) 33#define HCLK_PDAUDIO_HZ (150 * MHz) 34#define CLK_OSC0_DIV_HZ (32768) 35#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 36#define ACLK_PDVI_HZ (297 * MHz) 37#define CLK_ISP_HZ (297 * MHz) 38#define ACLK_PDISPP_HZ (297 * MHz) 39#define CLK_ISPP_HZ (237 * MHz) 40#define ACLK_VOP_HZ (300 * MHz) 41#define DCLK_VOP_HZ (65 * MHz) 42#endif 43 44/* RV1126 pll id */ 45enum rv1126_pll_id { 46 APLL, 47 DPLL, 48 CPLL, 49 HPLL, 50 GPLL, 51 PLL_COUNT, 52}; 53 54struct rv1126_clk_info { 55 unsigned long id; 56 char *name; 57 bool is_cru; 58}; 59 60/* Private data for the clock driver - used by rockchip_get_cru() */ 61struct rv1126_pmuclk_priv { 62 struct rv1126_pmucru *pmucru; 63 ulong gpll_hz; 64}; 65 66struct rv1126_clk_priv { 67 struct rv1126_cru *cru; 68 struct rv1126_grf *grf; 69 ulong gpll_hz; 70 ulong cpll_hz; 71 ulong hpll_hz; 72 ulong armclk_hz; 73 ulong armclk_enter_hz; 74 ulong armclk_init_hz; 75 bool sync_kernel; 76 bool set_armclk_rate; 77}; 78 79struct rv1126_pll { 80 unsigned int con0; 81 unsigned int con1; 82 unsigned int con2; 83 unsigned int con3; 84 unsigned int con4; 85 unsigned int con5; 86 unsigned int con6; 87 unsigned int reserved0[1]; 88}; 89 90struct rv1126_pmucru { 91 unsigned int pmu_mode; 92 unsigned int reserved1[3]; 93 struct rv1126_pll pll; 94 unsigned int offsetcal_status; 95 unsigned int reserved2[51]; 96 unsigned int pmu_clksel_con[14]; 97 unsigned int reserved3[18]; 98 unsigned int pmu_clkgate_con[3]; 99 unsigned int reserved4[29]; 100 unsigned int pmu_softrst_con[2]; 101 unsigned int reserved5[14]; 102 unsigned int pmu_autocs_con[2]; 103}; 104 105check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244); 106 107struct rv1126_cru { 108 struct rv1126_pll pll[4]; 109 unsigned int offsetcal_status[4]; 110 unsigned int mode; 111 unsigned int reserved1[27]; 112 unsigned int clksel_con[78]; 113 unsigned int reserved2[18]; 114 unsigned int clkgate_con[25]; 115 unsigned int reserved3[7]; 116 unsigned int softrst_con[15]; 117 unsigned int reserved4[17]; 118 unsigned int ssgtbl[32]; 119 unsigned int glb_cnt_th; 120 unsigned int glb_rst_st; 121 unsigned int glb_srst_fst; 122 unsigned int glb_srst_snd; 123 unsigned int glb_rst_con; 124 unsigned int reserved5[11]; 125 unsigned int sdmmc_con[2]; 126 unsigned int sdio_con[2]; 127 unsigned int emmc_con[2]; 128 unsigned int reserved6[2]; 129 unsigned int gmac_con; 130 unsigned int misc[2]; 131 unsigned int reserved7[45]; 132 unsigned int autocs_con[26]; 133}; 134 135check_member(rv1126_cru, autocs_con[25], 0x584); 136 137struct pll_rate_table { 138 unsigned long rate; 139 unsigned int fbdiv; 140 unsigned int postdiv1; 141 unsigned int refdiv; 142 unsigned int postdiv2; 143 unsigned int dsmpd; 144 unsigned int frac; 145}; 146 147struct cpu_rate_table { 148 unsigned long rate; 149 unsigned int aclk_div; 150 unsigned int pclk_div; 151}; 152 153#define RV1126_PMU_MODE 0x0 154#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) 155#define RV1126_PLL_CON(x) ((x) * 0x4) 156#define RV1126_MODE_CON 0x90 157 158enum { 159 /* CRU_PMU_CLK_SEL0_CON */ 160 RTC32K_SEL_SHIFT = 7, 161 RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, 162 RTC32K_SEL_PMUPVTM = 0, 163 RTC32K_SEL_OSC1_32K, 164 RTC32K_SEL_OSC0_DIV32K, 165 166 /* CRU_PMU_CLK_SEL1_CON */ 167 PCLK_PDPMU_DIV_SHIFT = 0, 168 PCLK_PDPMU_DIV_MASK = 0x1f, 169 170 /* CRU_PMU_CLK_SEL2_CON */ 171 CLK_I2C0_DIV_SHIFT = 0, 172 CLK_I2C0_DIV_MASK = 0x7f, 173 174 /* CRU_PMU_CLK_SEL3_CON */ 175 CLK_I2C2_DIV_SHIFT = 0, 176 CLK_I2C2_DIV_MASK = 0x7f, 177 178 /* CRU_PMU_CLK_SEL6_CON */ 179 CLK_PWM1_SEL_SHIFT = 15, 180 CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT, 181 CLK_PWM1_SEL_XIN24M = 0, 182 CLK_PWM1_SEL_GPLL, 183 CLK_PWM1_DIV_SHIFT = 8, 184 CLK_PWM1_DIV_MASK = 0x7f << CLK_PWM1_DIV_SHIFT, 185 CLK_PWM0_SEL_SHIFT = 7, 186 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 187 CLK_PWM0_SEL_XIN24M = 0, 188 CLK_PWM0_SEL_GPLL, 189 CLK_PWM0_DIV_SHIFT = 0, 190 CLK_PWM0_DIV_MASK = 0x7f, 191 192 /* CRU_PMU_CLK_SEL9_CON */ 193 CLK_SPI0_SEL_SHIFT = 7, 194 CLK_SPI0_SEL_MASK = 1 << CLK_SPI0_SEL_SHIFT, 195 CLK_SPI0_SEL_GPLL = 0, 196 CLK_SPI0_SEL_XIN24M, 197 CLK_SPI0_DIV_SHIFT = 0, 198 CLK_SPI0_DIV_MASK = 0x7f, 199 200 /* CRU_PMU_CLK_SEL13_CON */ 201 CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, 202 CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 203 CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 204 CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 205 206 /* CRU_CLK_SEL0_CON */ 207 CORE_HCLK_DIV_SHIFT = 8, 208 CORE_HCLK_DIV_MASK = 0x1f << CORE_HCLK_DIV_SHIFT, 209 210 /* CRU_CLK_SEL1_CON */ 211 CORE_ACLK_DIV_SHIFT = 4, 212 CORE_ACLK_DIV_MASK = 0xf << CORE_ACLK_DIV_SHIFT, 213 CORE_DBG_DIV_SHIFT = 0, 214 CORE_DBG_DIV_MASK = 0x7, 215 216 /* CRU_CLK_SEL2_CON */ 217 HCLK_PDBUS_SEL_SHIFT = 15, 218 HCLK_PDBUS_SEL_MASK = 1 << HCLK_PDBUS_SEL_SHIFT, 219 HCLK_PDBUS_SEL_GPLL = 0, 220 HCLK_PDBUS_SEL_CPLL, 221 HCLK_PDBUS_DIV_SHIFT = 8, 222 HCLK_PDBUS_DIV_MASK = 0x1f << HCLK_PDBUS_DIV_SHIFT, 223 ACLK_PDBUS_SEL_SHIFT = 6, 224 ACLK_PDBUS_SEL_MASK = 0x3 << ACLK_PDBUS_SEL_SHIFT, 225 ACLK_PDBUS_SEL_GPLL = 0, 226 ACLK_PDBUS_SEL_CPLL, 227 ACLK_PDBUS_SEL_DPLL, 228 ACLK_PDBUS_DIV_SHIFT = 0, 229 ACLK_PDBUS_DIV_MASK = 0x1f, 230 231 /* CRU_CLK_SEL3_CON */ 232 CLK_SCR1_SEL_SHIFT = 15, 233 CLK_SCR1_SEL_MASK = 1 << CLK_SCR1_SEL_SHIFT, 234 CLK_SCR1_SEL_GPLL = 0, 235 CLK_SCR1_SEL_CPLL, 236 CLK_SCR1_DIV_SHIFT = 8, 237 CLK_SCR1_DIV_MASK = 0x1f << CLK_SCR1_DIV_SHIFT, 238 PCLK_PDBUS_SEL_SHIFT = 7, 239 PCLK_PDBUS_SEL_MASK = 1 << PCLK_PDBUS_SEL_SHIFT, 240 PCLK_PDBUS_SEL_GPLL = 0, 241 PCLK_PDBUS_SEL_CPLL, 242 PCLK_PDBUS_DIV_SHIFT = 0, 243 PCLK_PDBUS_DIV_MASK = 0x1f, 244 245 /* CRU_CLK_SEL4_CON */ 246 ACLK_CRYPTO_SEL_SHIFT = 7, 247 ACLK_CRYPTO_SEL_MASK = 1 << ACLK_CRYPTO_SEL_SHIFT, 248 ACLK_CRYPTO_SEL_GPLL = 0, 249 ACLK_CRYPTO_SEL_CPLL, 250 ACLK_CRYPTO_DIV_SHIFT = 0, 251 ACLK_CRYPTO_DIV_MASK = 0x1f, 252 253 /* CRU_CLK_SEL5_CON */ 254 CLK_I2C3_DIV_SHIFT = 8, 255 CLK_I2C3_DIV_MASK = 0x7f << CLK_I2C3_DIV_SHIFT, 256 CLK_I2C1_DIV_SHIFT = 0, 257 CLK_I2C1_DIV_MASK = 0x7f, 258 259 /* CRU_CLK_SEL6_CON */ 260 CLK_I2C5_DIV_SHIFT = 8, 261 CLK_I2C5_DIV_MASK = 0x7f << CLK_I2C5_DIV_SHIFT, 262 CLK_I2C4_DIV_SHIFT = 0, 263 CLK_I2C4_DIV_MASK = 0x7f, 264 265 /* CRU_CLK_SEL7_CON */ 266 CLK_CRYPTO_PKA_SEL_SHIFT = 15, 267 CLK_CRYPTO_PKA_SEL_MASK = 1 << CLK_CRYPTO_PKA_SEL_SHIFT, 268 CLK_CRYPTO_PKA_SEL_GPLL = 0, 269 CLK_CRYPTO_PKA_SEL_CPLL, 270 CLK_CRYPTO_PKA_DIV_SHIFT = 8, 271 CLK_CRYPTO_PKA_DIV_MASK = 0x1f << CLK_CRYPTO_PKA_DIV_SHIFT, 272 CLK_CRYPTO_CORE_SEL_SHIFT = 7, 273 CLK_CRYPTO_CORE_SEL_MASK = 1 << CLK_CRYPTO_CORE_SEL_SHIFT, 274 CLK_CRYPTO_CORE_SEL_GPLL = 0, 275 CLK_CRYPTO_CORE_SEL_CPLL, 276 CLK_CRYPTO_CORE_DIV_SHIFT = 0, 277 CLK_CRYPTO_CORE_DIV_MASK = 0x1f, 278 279 /* CRU_CLK_SEL8_CON */ 280 CLK_SPI1_SEL_SHIFT = 8, 281 CLK_SPI1_SEL_MASK = 1 << CLK_SPI1_SEL_SHIFT, 282 CLK_SPI1_SEL_GPLL = 0, 283 CLK_SPI1_SEL_XIN24M, 284 CLK_SPI1_DIV_SHIFT = 0, 285 CLK_SPI1_DIV_MASK = 0x7f, 286 287 /* CRU_CLK_SEL9_CON */ 288 CLK_PWM2_SEL_SHIFT = 15, 289 CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT, 290 CLK_PWM2_SEL_XIN24M = 0, 291 CLK_PWM2_SEL_GPLL, 292 CLK_PWM2_DIV_SHIFT = 8, 293 CLK_PWM2_DIV_MASK = 0x7f << CLK_PWM2_DIV_SHIFT, 294 295 /* CRU_CLK_SEL20_CON */ 296 CLK_SARADC_DIV_SHIFT = 0, 297 CLK_SARADC_DIV_MASK = 0x7ff, 298 299 /* CRU_CLK_SEL25_CON */ 300 DCLK_DECOM_SEL_SHIFT = 15, 301 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, 302 DCLK_DECOM_SEL_GPLL = 0, 303 DCLK_DECOM_SEL_CPLL, 304 DCLK_DECOM_DIV_SHIFT = 8, 305 DCLK_DECOM_DIV_MASK = 0x7f << DCLK_DECOM_DIV_SHIFT, 306 307 /* CRU_CLK_SEL26_CON */ 308 HCLK_PDAUDIO_DIV_SHIFT = 0, 309 HCLK_PDAUDIO_DIV_MASK = 0x1f, 310 311 /* CRU_CLK_SEL45_CON */ 312 ACLK_PDVO_SEL_SHIFT = 7, 313 ACLK_PDVO_SEL_MASK = 1 << ACLK_PDVO_SEL_SHIFT, 314 ACLK_PDVO_SEL_GPLL = 0, 315 ACLK_PDVO_SEL_CPLL, 316 ACLK_PDVO_DIV_SHIFT = 0, 317 ACLK_PDVO_DIV_MASK = 0x1f, 318 319 /* CRU_CLK_SEL47_CON */ 320 DCLK_VOP_SEL_SHIFT = 8, 321 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 322 DCLK_VOP_SEL_GPLL = 0, 323 DCLK_VOP_SEL_CPLL, 324 DCLK_VOP_DIV_SHIFT = 0, 325 DCLK_VOP_DIV_MASK = 0xff, 326 327#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 328 /* CRU_CLK_SEL49_CON */ 329 ACLK_PDVI_SEL_SHIFT = 6, 330 ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT, 331 ACLK_PDVI_SEL_CPLL = 0, 332 ACLK_PDVI_SEL_GPLL, 333 ACLK_PDVI_SEL_HPLL, 334 ACLK_PDVI_DIV_SHIFT = 0, 335 ACLK_PDVI_DIV_MASK = 0x1f, 336 337 /* CRU_CLK_SEL50_CON */ 338 CLK_ISP_SEL_SHIFT = 6, 339 CLK_ISP_SEL_MASK = 0x3 << CLK_ISP_SEL_SHIFT, 340 CLK_ISP_SEL_GPLL = 0, 341 CLK_ISP_SEL_CPLL, 342 CLK_ISP_SEL_HPLL, 343 CLK_ISP_DIV_SHIFT = 0, 344 CLK_ISP_DIV_MASK = 0x1f, 345#endif 346 347 /* CRU_CLK_SEL53_CON */ 348 HCLK_PDPHP_DIV_SHIFT = 8, 349 HCLK_PDPHP_DIV_MASK = 0x1f << HCLK_PDPHP_DIV_SHIFT, 350 ACLK_PDPHP_SEL_SHIFT = 7, 351 ACLK_PDPHP_SEL_MASK = 1 << ACLK_PDPHP_SEL_SHIFT, 352 ACLK_PDPHP_SEL_GPLL = 0, 353 ACLK_PDPHP_SEL_CPLL, 354 ACLK_PDPHP_DIV_SHIFT = 0, 355 ACLK_PDPHP_DIV_MASK = 0x1f, 356 357 /* CRU_CLK_SEL57_CON */ 358 EMMC_SEL_SHIFT = 14, 359 EMMC_SEL_MASK = 0x3 << EMMC_SEL_SHIFT, 360 EMMC_SEL_GPLL = 0, 361 EMMC_SEL_CPLL, 362 EMMC_SEL_XIN24M, 363 EMMC_DIV_SHIFT = 0, 364 EMMC_DIV_MASK = 0xff, 365 366 /* CRU_CLK_SEL58_CON */ 367 SCLK_SFC_SEL_SHIFT = 15, 368 SCLK_SFC_SEL_MASK = 0x1 << SCLK_SFC_SEL_SHIFT, 369 SCLK_SFC_SEL_CPLL = 0, 370 SCLK_SFC_SEL_GPLL, 371 SCLK_SFC_DIV_SHIFT = 0, 372 SCLK_SFC_DIV_MASK = 0xff, 373 374 /* CRU_CLK_SEL59_CON */ 375 CLK_NANDC_SEL_SHIFT = 15, 376 CLK_NANDC_SEL_MASK = 0x1 << CLK_NANDC_SEL_SHIFT, 377 CLK_NANDC_SEL_GPLL = 0, 378 CLK_NANDC_SEL_CPLL, 379 CLK_NANDC_DIV_SHIFT = 0, 380 CLK_NANDC_DIV_MASK = 0xff, 381 382 /* CRU_CLK_SEL61_CON */ 383 CLK_GMAC_OUT_SEL_SHIFT = 15, 384 CLK_GMAC_OUT_SEL_MASK = 0x1 << CLK_GMAC_OUT_SEL_SHIFT, 385 CLK_GMAC_OUT_SEL_CPLL = 0, 386 CLK_GMAC_OUT_SEL_GPLL, 387 CLK_GMAC_OUT_DIV_SHIFT = 8, 388 CLK_GMAC_OUT_DIV_MASK = 0x1f << CLK_GMAC_OUT_DIV_SHIFT, 389 390 /* CRU_CLK_SEL63_CON */ 391 PCLK_GMAC_DIV_SHIFT = 8, 392 PCLK_GMAC_DIV_MASK = 0x1f << PCLK_GMAC_DIV_SHIFT, 393 CLK_GMAC_SRC_SEL_SHIFT = 7, 394 CLK_GMAC_SRC_SEL_MASK = 0x1 << CLK_GMAC_SRC_SEL_SHIFT, 395 CLK_GMAC_SRC_SEL_CPLL = 0, 396 CLK_GMAC_SRC_SEL_GPLL, 397 CLK_GMAC_SRC_DIV_SHIFT = 0, 398 CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT, 399 400#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) 401 /* CRU_CLK_SEL68_CON */ 402 ACLK_PDISPP_SEL_SHIFT = 6, 403 ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT, 404 ACLK_PDISPP_SEL_CPLL = 0, 405 ACLK_PDISPP_SEL_GPLL, 406 ACLK_PDISPP_SEL_HPLL, 407 ACLK_PDISPP_DIV_SHIFT = 0, 408 ACLK_PDISPP_DIV_MASK = 0x1f, 409 410 /* CRU_CLK_SEL69_CON */ 411 CLK_ISPP_SEL_SHIFT = 6, 412 CLK_ISPP_SEL_MASK = 0x3 << CLK_ISPP_SEL_SHIFT, 413 CLK_ISPP_SEL_CPLL = 0, 414 CLK_ISPP_SEL_GPLL, 415 CLK_ISPP_SEL_HPLL, 416 CLK_ISPP_DIV_SHIFT = 0, 417 CLK_ISPP_DIV_MASK = 0x1f, 418 419 /* CRU_CLK_SEL73_CON */ 420 MIPICSI_OUT_SEL_SHIFT = 10, 421 MIPICSI_OUT_SEL_MASK = 0x3 << MIPICSI_OUT_SEL_SHIFT, 422 MIPICSI_OUT_SEL_XIN24M = 0, 423 MIPICSI_OUT_SEL_DIV, 424 MIPICSI_OUT_SEL_FRACDIV, 425 MIPICSI_OUT_DIV_SHIFT = 0, 426 MIPICSI_OUT_DIV_MASK = 0x1f, 427#endif 428 429 /* CRU_GMAC_CON */ 430 GMAC_SRC_M1_SEL_SHIFT = 5, 431 GMAC_SRC_M1_SEL_MASK = 0x1 << GMAC_SRC_M1_SEL_SHIFT, 432 GMAC_SRC_M1_SEL_INT = 0, 433 GMAC_SRC_M1_SEL_EXT, 434 GMAC_MODE_SEL_SHIFT = 4, 435 GMAC_MODE_SEL_MASK = 0x1 << GMAC_MODE_SEL_SHIFT, 436 GMAC_RGMII_MODE = 0, 437 GMAC_RMII_MODE, 438 RGMII_CLK_SEL_SHIFT = 2, 439 RGMII_CLK_SEL_MASK = 0x3 << RGMII_CLK_SEL_SHIFT, 440 RGMII_CLK_DIV0 = 0, 441 RGMII_CLK_DIV1, 442 RGMII_CLK_DIV50, 443 RGMII_CLK_DIV5, 444 RMII_CLK_SEL_SHIFT = 1, 445 RMII_CLK_SEL_MASK = 0x1 << RMII_CLK_SEL_SHIFT, 446 RMII_CLK_DIV20 = 0, 447 RMII_CLK_DIV2, 448 GMAC_SRC_M0_SEL_SHIFT = 0, 449 GMAC_SRC_M0_SEL_MASK = 0x1, 450 GMAC_SRC_M0_SEL_INT = 0, 451 GMAC_SRC_M0_SEL_EXT, 452 453 /* GRF_IOFUNC_CON1 */ 454 GMAC_SRC_SEL_SHIFT = 12, 455 GMAC_SRC_SEL_MASK = 1 << GMAC_SRC_SEL_SHIFT, 456 GMAC_SRC_SEL_M0 = 0, 457 GMAC_SRC_SEL_M1, 458}; 459#endif 460