1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 4 */ 5 6#ifndef _ASM_ARCH_CRU_RK3128_H 7#define _ASM_ARCH_CRU_RK3128_H 8 9#ifndef __ASSEMBLY__ 10#include <linux/bitops.h> 11#endif 12 13#define MHz 1000000 14#define OSC_HZ (24 * MHz) 15 16#define APLL_HZ (600 * MHz) 17#define GPLL_HZ (594 * MHz) 18 19#define CORE_PERI_HZ 150000000 20#define CORE_ACLK_HZ 300000000 21 22#define BUS_ACLK_HZ 148500000 23#define BUS_HCLK_HZ 148500000 24#define BUS_PCLK_HZ 74250000 25 26#define PERI_ACLK_HZ 148500000 27#define PERI_HCLK_HZ 148500000 28#define PERI_PCLK_HZ 74250000 29 30/* Private data for the clock driver - used by rockchip_get_cru() */ 31struct rk3128_clk_priv { 32 struct rk3128_cru *cru; 33}; 34 35struct rk3128_cru { 36 struct rk3128_pll { 37 unsigned int con0; 38 unsigned int con1; 39 unsigned int con2; 40 unsigned int con3; 41 } pll[4]; 42 unsigned int cru_mode_con; 43 unsigned int cru_clksel_con[35]; 44 unsigned int cru_clkgate_con[11]; 45 unsigned int reserved; 46 unsigned int cru_glb_srst_fst_value; 47 unsigned int cru_glb_srst_snd_value; 48 unsigned int reserved1[2]; 49 unsigned int cru_softrst_con[9]; 50 unsigned int cru_misc_con; 51 unsigned int reserved2[2]; 52 unsigned int cru_glb_cnt_th; 53 unsigned int reserved3[3]; 54 unsigned int cru_glb_rst_st; 55 unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; 56 unsigned int cru_sdmmc_con[2]; 57 unsigned int cru_sdio_con[2]; 58 unsigned int reserved5[2]; 59 unsigned int cru_emmc_con[2]; 60 unsigned int reserved6[4]; 61 unsigned int cru_pll_prg_en; 62}; 63check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); 64 65struct pll_div { 66 u32 refdiv; 67 u32 fbdiv; 68 u32 postdiv1; 69 u32 postdiv2; 70 u32 frac; 71}; 72 73enum { 74 /* PLLCON0*/ 75 PLL_POSTDIV1_SHIFT = 12, 76 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 77 PLL_FBDIV_SHIFT = 0, 78 PLL_FBDIV_MASK = 0xfff, 79 80 /* PLLCON1 */ 81 PLL_RST_SHIFT = 14, 82 PLL_PD_SHIFT = 13, 83 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 84 PLL_DSMPD_SHIFT = 12, 85 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 86 PLL_LOCK_STATUS_SHIFT = 10, 87 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 88 PLL_POSTDIV2_SHIFT = 6, 89 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 90 PLL_REFDIV_SHIFT = 0, 91 PLL_REFDIV_MASK = 0x3f, 92 93 /* CRU_MODE */ 94 GPLL_MODE_SHIFT = 12, 95 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 96 GPLL_MODE_SLOW = 0, 97 GPLL_MODE_NORM, 98 GPLL_MODE_DEEP, 99 CPLL_MODE_SHIFT = 8, 100 CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, 101 CPLL_MODE_SLOW = 0, 102 CPLL_MODE_NORM, 103 DPLL_MODE_SHIFT = 4, 104 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, 105 DPLL_MODE_SLOW = 0, 106 DPLL_MODE_NORM, 107 APLL_MODE_SHIFT = 0, 108 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, 109 APLL_MODE_SLOW = 0, 110 APLL_MODE_NORM, 111 112 /* CRU_CLK_SEL0_CON */ 113 BUS_ACLK_PLL_SEL_SHIFT = 14, 114 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 115 BUS_ACLK_PLL_SEL_CPLL = 0, 116 BUS_ACLK_PLL_SEL_GPLL, 117 BUS_ACLK_PLL_SEL_GPLL_DIV2, 118 BUS_ACLK_PLL_SEL_GPLL_DIV3, 119 BUS_ACLK_DIV_SHIFT = 8, 120 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 121 CORE_CLK_PLL_SEL_SHIFT = 7, 122 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 123 CORE_CLK_PLL_SEL_APLL = 0, 124 CORE_CLK_PLL_SEL_GPLL_DIV2, 125 CORE_DIV_CON_SHIFT = 0, 126 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 127 128 /* CRU_CLK_SEL1_CON */ 129 BUS_PCLK_DIV_SHIFT = 12, 130 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 131 BUS_HCLK_DIV_SHIFT = 8, 132 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 133 CORE_ACLK_DIV_SHIFT = 4, 134 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 135 CORE_PERI_DIV_SHIFT = 0, 136 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 137 138 /* CRU_CLK_SEL2_CON */ 139 NANDC_PLL_SEL_SHIFT = 14, 140 NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, 141 NANDC_PLL_SEL_CPLL = 0, 142 NANDC_PLL_SEL_GPLL, 143 NANDC_CLK_DIV_SHIFT = 8, 144 NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, 145 PVTM_CLK_DIV_SHIFT = 0, 146 PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, 147 148 /* CRU_CLKSEL10_CON */ 149 PERI_PLL_SEL_SHIFT = 14, 150 PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT, 151 PERI_PLL_APLL = 0, 152 PERI_PLL_DPLL, 153 PERI_PLL_GPLL, 154 PERI_PCLK_DIV_SHIFT = 12, 155 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 156 PERI_HCLK_DIV_SHIFT = 8, 157 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 158 PERI_ACLK_DIV_SHIFT = 0, 159 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 160 161 /* CRU_CLKSEL11_CON */ 162 MMC0_PLL_SHIFT = 6, 163 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 164 MMC0_SEL_APLL = 0, 165 MMC0_SEL_GPLL, 166 MMC0_SEL_GPLL_DIV2, 167 MMC0_SEL_24M, 168 MMC0_DIV_SHIFT = 0, 169 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 170 171 /* CRU_CLKSEL12_CON */ 172 EMMC_PLL_SHIFT = 14, 173 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 174 EMMC_SEL_APLL = 0, 175 EMMC_SEL_GPLL, 176 EMMC_SEL_GPLL_DIV2, 177 EMMC_SEL_24M, 178 EMMC_DIV_SHIFT = 8, 179 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 180 181 /* CLKSEL_CON24 */ 182 SARADC_DIV_CON_SHIFT = 8, 183 SARADC_DIV_CON_MASK = GENMASK(15, 8), 184 SARADC_DIV_CON_WIDTH = 8, 185 186 /* CRU_CLKSEL27_CON*/ 187 DCLK_VOP_SEL_SHIFT = 0, 188 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 189 DCLK_VOP_PLL_SEL_CPLL = 0, 190 DCLK_VOP_DIV_CON_SHIFT = 8, 191 DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, 192 193 /* CRU_CLKSEL31_CON */ 194 VIO0_PLL_SHIFT = 5, 195 VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, 196 VI00_SEL_CPLL = 0, 197 VIO0_SEL_GPLL, 198 VIO0_DIV_SHIFT = 0, 199 VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, 200 VIO1_PLL_SHIFT = 13, 201 VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, 202 VI01_SEL_CPLL = 0, 203 VIO1_SEL_GPLL, 204 VIO1_DIV_SHIFT = 8, 205 VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, 206 207 /* CRU_SOFTRST5_CON */ 208 DDRCTRL_PSRST_SHIFT = 11, 209 DDRCTRL_SRST_SHIFT = 10, 210 DDRPHY_PSRST_SHIFT = 9, 211 DDRPHY_SRST_SHIFT = 8, 212}; 213#endif 214