Searched refs:mcr (Results 1 - 25 of 61) sorted by relevance

123

/u-boot/arch/arm/mach-mvebu/
H A Dlowlevel.S23 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
24 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
25 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
26 mcr p15, 0, r0, c7, c10, 4 @ DSB
27 mcr p15, 0, r0, c7, c5, 4 @ ISB
32 mcr p15, 0, r0, c1, c0, 0
52 mcr p15, 4, r0, c15, c0
H A Dlowlevel_spl.S40 mcr p15, 0, r0, c7, c6, 1
56 mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
57 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
58 mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
75 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
/u-boot/arch/arm/include/asm/arch-armv7/
H A Dgenerictimer.h35 mcr p15, 0, \reg, c14, c2, 0
38 mcr p15, 0, \reg, c14, c2, 1
44 mcr p15, 0, \reg, c14, c2, 1
/u-boot/drivers/adc/
H A Dimx93-adc.c70 u32 mcr, msr; local
73 mcr = readl(adc->regs + IMX93_ADC_MCR);
74 mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
75 writel(mcr, adc->regs + IMX93_ADC_MCR);
85 u32 mcr; local
88 mcr = readl(adc->regs + IMX93_ADC_MCR);
89 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
90 writel(mcr, adc->regs + IMX93_ADC_MCR);
95 u32 mcr; local
101 mcr
111 u32 mcr, msr; local
186 u32 imr, mcr; local
[all...]
/u-boot/arch/arm/cpu/armv7/s5p4418/
H A Drelocate.S21 mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-suspend.S19 mcr p15, 2, r0, c0, c0, 0
43 mcr p15, 0, r5, c7, c6, 2
57 mcr p15, 0, r6, c7, c5, 0
58 mcr p15, 0, r6, c7, c5, 6
61 mcr p15, 0, r6, c1, c0, 0
/u-boot/arch/arm/mach-mediatek/mt7623/
H A Dlowlevel_init.S20 mcr p15, 0, r0, c1, c0, 1
/u-boot/arch/arm/cpu/arm11/
H A Dsctlr.S23 mcr p15, 0, r0, c1, c0, 0 @ write system control register
/u-boot/arch/arm/cpu/armv7/
H A Dsctlr.S20 mcr p15, 0, r0, c1, c0, 0 @ write system control register
H A Dstart.S108 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
113 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
136 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
210 mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register
217 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
218 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
219 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
236 mcr p15, 0, r0, c1, c0, 0
241 mcr p15, 0, r0, c1, c0, 0 @ write system control register
247 mcr p1
[all...]
H A Dnonsec_virt.S48 mcr p15, 0, r5, c12, c0, 1
63 mcr p15, 0, r5, c1, c0, 1
70 mcr p15, 0, r5, c1, c0, 1
87 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
184 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
201 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
/u-boot/arch/arm/cpu/arm1136/
H A Dstart.S71 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
72 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
82 mcr p15, 0, r0, c1, c0, 0
/u-boot/arch/arm/cpu/arm946es/
H A Dstart.S79 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
80 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
90 mcr p15, 0, r0, c1, c0, 0
/u-boot/arch/arm/cpu/arm1176/
H A Dstart.S73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
93 mcr p15, 0, r0, c1, c0, 0
/u-boot/arch/arm/cpu/arm920t/
H A Dstart.S73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
84 mcr p15, 0, r0, c1, c0, 0
/u-boot/arch/arm/cpu/arm926ejs/
H A Dstart.S88 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
89 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
107 mcr p15, 0, r0, c1, c0, 0
/u-boot/arch/arm/mach-mediatek/mt7629/
H A Dlowlevel_init.S29 mcr p15, 0, r0, c14, c0, 0
34 mcr p15, 0, r0, c1, c1, 0 @ Set Non Secure bit
39 mcr p15, 0, r1, c1, c1, 0 @ Set Secure bit
46 mcr p15, 0, r0, c1, c0, 1
/u-boot/arch/arm/include/asm/arch-rockchip/
H A Duart.h13 unsigned int mcr; /* Modem control register. */ member in struct:rk_uart
/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dfel_utils.S31 mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
33 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
/u-boot/arch/arm/mach-zynq/
H A Dlowlevel_init.S16 mcr p15, 0, r1, c1, c0, 2
/u-boot/arch/arm/mach-uniphier/arm32/
H A Dlowlevel_init.S25 mcr p15, 0, r0, c1, c0, 0
44 mcr p15, 0, r0, c1, c0, 0
56 mcr p15, 0, r0, c2, c0, 2
59 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
62 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
65 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
76 mcr p15, 0, r0, c1, c0, 0
/u-boot/arch/arm/lib/
H A Drelocate.S44 mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
125 mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
126 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
/u-boot/drivers/i2c/
H A Dimx_lpi2c.c67 val = readl(&regs->mcr);
69 writel(val, &regs->mcr);
297 mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
299 val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
300 writel(val | LPI2C_MCR_MEN(0), &regs->mcr);
342 val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
343 writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
357 writel(LPI2C_MCR_RST_MASK, &regs->mcr);
358 writel(0x0, &regs->mcr);
360 writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
[all...]
/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dstart.S85 mcr p15, 0, r2, c1, c0, 0
/u-boot/arch/arm/cpu/arm926ejs/sunxi/
H A Dfel_utils.S29 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR register

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