/u-boot/arch/arm/mach-mvebu/ |
H A D | lowlevel.S | 23 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 24 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 25 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 26 mcr p15, 0, r0, c7, c10, 4 @ DSB 27 mcr p15, 0, r0, c7, c5, 4 @ ISB 32 mcr p15, 0, r0, c1, c0, 0 52 mcr p15, 4, r0, c15, c0
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H A D | lowlevel_spl.S | 40 mcr p15, 0, r0, c7, c6, 1 56 mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */ 57 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */ 58 mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */ 75 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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/u-boot/arch/arm/include/asm/arch-armv7/ |
H A D | generictimer.h | 35 mcr p15, 0, \reg, c14, c2, 0 38 mcr p15, 0, \reg, c14, c2, 1 44 mcr p15, 0, \reg, c14, c2, 1
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/u-boot/drivers/adc/ |
H A D | imx93-adc.c | 70 u32 mcr, msr; local 73 mcr = readl(adc->regs + IMX93_ADC_MCR); 74 mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); 75 writel(mcr, adc->regs + IMX93_ADC_MCR); 85 u32 mcr; local 88 mcr = readl(adc->regs + IMX93_ADC_MCR); 89 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); 90 writel(mcr, adc->regs + IMX93_ADC_MCR); 95 u32 mcr; local 101 mcr 111 u32 mcr, msr; local 186 u32 imr, mcr; local [all...] |
/u-boot/arch/arm/cpu/armv7/s5p4418/ |
H A D | relocate.S | 21 mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
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/u-boot/arch/arm/mach-imx/mx7/ |
H A D | psci-suspend.S | 19 mcr p15, 2, r0, c0, c0, 0 43 mcr p15, 0, r5, c7, c6, 2 57 mcr p15, 0, r6, c7, c5, 0 58 mcr p15, 0, r6, c7, c5, 6 61 mcr p15, 0, r6, c1, c0, 0
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/u-boot/arch/arm/mach-mediatek/mt7623/ |
H A D | lowlevel_init.S | 20 mcr p15, 0, r0, c1, c0, 1
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/u-boot/arch/arm/cpu/arm11/ |
H A D | sctlr.S | 23 mcr p15, 0, r0, c1, c0, 0 @ write system control register
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/u-boot/arch/arm/cpu/armv7/ |
H A D | sctlr.S | 20 mcr p15, 0, r0, c1, c0, 0 @ write system control register
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H A D | start.S | 108 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register 113 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 136 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 210 mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register 217 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 218 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 219 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 236 mcr p15, 0, r0, c1, c0, 0 241 mcr p15, 0, r0, c1, c0, 0 @ write system control register 247 mcr p1 [all...] |
H A D | nonsec_virt.S | 48 mcr p15, 0, r5, c12, c0, 1 63 mcr p15, 0, r5, c1, c0, 1 70 mcr p15, 0, r5, c1, c0, 1 87 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) 184 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec 201 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
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/u-boot/arch/arm/cpu/arm1136/ |
H A D | start.S | 71 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 72 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 82 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm946es/ |
H A D | start.S | 79 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */ 80 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */ 90 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm1176/ |
H A D | start.S | 73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 93 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm920t/ |
H A D | start.S | 73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 84 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm926ejs/ |
H A D | start.S | 88 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 89 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 107 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/mach-mediatek/mt7629/ |
H A D | lowlevel_init.S | 29 mcr p15, 0, r0, c14, c0, 0 34 mcr p15, 0, r0, c1, c1, 0 @ Set Non Secure bit 39 mcr p15, 0, r1, c1, c1, 0 @ Set Secure bit 46 mcr p15, 0, r0, c1, c0, 1
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/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | uart.h | 13 unsigned int mcr; /* Modem control register. */ member in struct:rk_uart
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/u-boot/arch/arm/cpu/armv7/sunxi/ |
H A D | fel_utils.S | 31 mcr p15, 0, r1, c12, c0, 0 @ Write VBAR 33 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
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/u-boot/arch/arm/mach-zynq/ |
H A D | lowlevel_init.S | 16 mcr p15, 0, r1, c1, c0, 2
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/u-boot/arch/arm/mach-uniphier/arm32/ |
H A D | lowlevel_init.S | 25 mcr p15, 0, r0, c1, c0, 0 44 mcr p15, 0, r0, c1, c0, 0 56 mcr p15, 0, r0, c2, c0, 2 59 mcr p15, 0, r0, c2, c0, 0 @ TTBR0 62 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 65 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register) 76 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/lib/ |
H A D | relocate.S | 44 mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */ 125 mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ 126 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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/u-boot/drivers/i2c/ |
H A D | imx_lpi2c.c | 67 val = readl(®s->mcr); 69 writel(val, ®s->mcr); 297 mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; 299 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK; 300 writel(val | LPI2C_MCR_MEN(0), ®s->mcr); 342 val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK; 343 writel(val | LPI2C_MCR_MEN(1), ®s->mcr); 357 writel(LPI2C_MCR_RST_MASK, ®s->mcr); 358 writel(0x0, ®s->mcr); 360 writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr); [all...] |
/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
H A D | start.S | 85 mcr p15, 0, r2, c1, c0, 0
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/u-boot/arch/arm/cpu/arm926ejs/sunxi/ |
H A D | fel_utils.S | 29 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR register
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