/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | cru_rk3399.h | 68 #define OSC_HZ (24*MHz) 69 #define LPLL_HZ (600*MHz) 70 #define BPLL_HZ (600*MHz) 71 #define GPLL_HZ (594*MHz) 72 #define CPLL_HZ (384*MHz) 73 #define PPLL_HZ (676*MHz) 75 #define PMU_PCLK_HZ (48*MHz) 77 #define ACLKM_CORE_L_HZ (300*MHz) 78 #define ATCLK_CORE_L_HZ (300*MHz) 79 #define PCLK_DBG_L_HZ (100*MHz) [all...] |
H A D | cru_rk3328.h | 45 #define MHz 1000000 macro 47 #define OSC_HZ (24 * MHz) 48 #define APLL_HZ (600 * MHz) 49 #define GPLL_HZ (576 * MHz) 50 #define CPLL_HZ (594 * MHz) 52 #define CLK_CORE_HZ (600 * MHz) 53 #define ACLKM_CORE_HZ (300 * MHz) 54 #define PCLK_DBG_HZ (300 * MHz) 60 #define PWM_CLOCK_HZ (74 * MHz)
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H A D | cru_rv1126.h | 10 #define MHz 1000000 macro 12 #define OSC_HZ (24 * MHz) 15 #define APLL_HZ (1008 * MHz) 17 #define APLL_HZ (816 * MHz) 19 #define GPLL_HZ (1188 * MHz) 20 #define CPLL_HZ (500 * MHz) 21 #define HPLL_HZ (1400 * MHz) 22 #define PCLK_PDPMU_HZ (100 * MHz) 24 #define ACLK_PDBUS_HZ (396 * MHz) 26 #define ACLK_PDBUS_HZ (500 * MHz) [all...] |
H A D | cru.h | 33 #define MHz 1000000 macro
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H A D | cru_px30.h | 8 #define MHz 1000000 macro 10 #define OSC_HZ (24 * MHz) 12 #define APLL_HZ (600 * MHz) 13 #define GPLL_HZ (1200 * MHz) 14 #define NPLL_HZ (1188 * MHz) 15 #define ACLK_BUS_HZ (200 * MHz) 16 #define HCLK_BUS_HZ (150 * MHz) 17 #define PCLK_BUS_HZ (100 * MHz) 18 #define ACLK_PERI_HZ (200 * MHz) 19 #define HCLK_PERI_HZ (150 * MHz) [all...] |
H A D | cru_rk322x.h | 8 #define MHz 1000000 macro 9 #define OSC_HZ (24 * MHz) 11 #define APLL_HZ (600 * MHz) 12 #define GPLL_HZ (594 * MHz)
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H A D | cru_rk3128.h | 13 #define MHz 1000000 macro 14 #define OSC_HZ (24 * MHz) 16 #define APLL_HZ (600 * MHz) 17 #define GPLL_HZ (594 * MHz)
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H A D | cru_rk3588.h | 10 #define MHz 1000000 macro 12 #define OSC_HZ (24 * MHz) 14 #define LPLL_HZ (816 * MHz) 15 #define GPLL_HZ (1188 * MHz) 16 #define CPLL_HZ (1500 * MHz) 17 #define NPLL_HZ (850 * MHz) 18 #define PPLL_HZ (1100 * MHz) 19 #define SPLL_HZ (702 * MHz)
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H A D | cru_rk3568.h | 10 #define MHz 1000000 macro 12 #define OSC_HZ (24 * MHz) 14 #define APLL_HZ (816 * MHz) 15 #define GPLL_HZ (1188 * MHz) 16 #define CPLL_HZ (1000 * MHz) 17 #define PPLL_HZ (200 * MHz)
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/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3568.c | 723 rate = 200 * MHz; 725 rate = 150 * MHz; 727 rate = 100 * MHz; 736 rate = 100 * MHz; 738 rate = 75 * MHz; 740 rate = 50 * MHz; 759 if (rate == 200 * MHz) 761 else if (rate == 150 * MHz) 763 else if (rate == 100 * MHz) 773 if (rate == 100 * MHz) [all...] |
H A D | clk_rk3588.c | 144 rate = 702 * MHz; 146 rate = 396 * MHz; 148 rate = 200 * MHz; 157 rate = 500 * MHz; 159 rate = 250 * MHz; 161 rate = 100 * MHz; 170 rate = 396 * MHz; 172 rate = 200 * MHz; 174 rate = 100 * MHz; 183 rate = 200 * MHz; [all...] |
H A D | clk_rk3399.c | 63 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1); 64 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1); 71 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1); 298 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 299 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 300 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 301 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 320 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 423 if (best_diff_khz > 4 * (MHz / KHz)) { 685 int aclk_vop = 198 * MHz; [all...] |
H A D | clk_rk3368.c | 210 const ulong MHz = 1000000; local 217 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz } 290 const ulong MHz = 1000000; local 293 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); 294 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); 295 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); 298 case 1200*MHz: 301 case 1332*MHz: 304 case 1600*MHz:
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/u-boot/board/samsung/smdkc100/ |
H A D | lowlevel_init.S | 91 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz) 94 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) 97 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
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/u-boot/drivers/video/rockchip/ |
H A D | rk3288_mipi.c | 26 #define MHz 1000000 macro 91 priv->ref_clk = 24 * MHz; 96 priv->txesc_clk = 20 * MHz;
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H A D | rk_mipi.c | 232 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; 243 if (ddr_clk / (MHz) <= freq_rang[i][0]) 257 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz 260 max_prediv = (refclk / (5 * MHz)); 261 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
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/u-boot/drivers/ram/rockchip/ |
H A D | sdram-rv1126-ddr3-detect-1056.inc | 27 .ddr_freq = 1056, /* clock rate(MHz) */
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H A D | sdram-rv1126-ddr3-detect-328.inc | 27 .ddr_freq = 328, /* clock rate(MHz) */
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H A D | sdram-rv1126-ddr3-detect-396.inc | 27 .ddr_freq = 396, /* clock rate(MHz) */
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H A D | sdram-rv1126-ddr3-detect-528.inc | 27 .ddr_freq = 528, /* clock rate(MHz) */
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H A D | sdram-rv1126-ddr3-detect-664.inc | 27 .ddr_freq = 664, /* clock rate(MHz) */
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H A D | sdram-rv1126-ddr3-detect-784.inc | 27 .ddr_freq = 784, /* clock rate(MHz) */
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H A D | sdram-rv1126-ddr3-detect-924.inc | 27 .ddr_freq = 924, /* clock rate(MHz) */
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H A D | sdram-rv1126-lpddr4-detect-1056.inc | 27 .ddr_freq = 1056, /* clock rate(MHz) */
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H A D | sdram-rv1126-lpddr4-detect-328.inc | 27 .ddr_freq = 328, /* clock rate(MHz) */
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