1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __ASM_ARCH_CRU_RK3399_H_
7#define __ASM_ARCH_CRU_RK3399_H_
8
9/* Private data for the clock driver - used by rockchip_get_cru() */
10struct rk3399_clk_priv {
11	struct rockchip_cru *cru;
12};
13
14struct rk3399_pmuclk_priv {
15	struct rk3399_pmucru *pmucru;
16};
17
18struct rk3399_pmucru {
19	u32 ppll_con[6];
20	u32 reserved[0x1a];
21	u32 pmucru_clksel[6];
22	u32 pmucru_clkfrac_con[2];
23	u32 reserved2[0x18];
24	u32 pmucru_clkgate_con[3];
25	u32 reserved3;
26	u32 pmucru_softrst_con[2];
27	u32 reserved4[2];
28	u32 pmucru_rstnhold_con[2];
29	u32 reserved5[2];
30	u32 pmucru_gatedis_con[2];
31};
32check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
33
34struct rockchip_cru {
35	u32 apll_l_con[6];
36	u32 reserved[2];
37	u32 apll_b_con[6];
38	u32 reserved1[2];
39	u32 dpll_con[6];
40	u32 reserved2[2];
41	u32 cpll_con[6];
42	u32 reserved3[2];
43	u32 gpll_con[6];
44	u32 reserved4[2];
45	u32 npll_con[6];
46	u32 reserved5[2];
47	u32 vpll_con[6];
48	u32 reserved6[0x0a];
49	u32 clksel_con[108];
50	u32 reserved7[0x14];
51	u32 clkgate_con[35];
52	u32 reserved8[0x1d];
53	u32 softrst_con[21];
54	u32 reserved9[0x2b];
55	u32 glb_srst_fst_value;
56	u32 glb_srst_snd_value;
57	u32 glb_cnt_th;
58	u32 misc_con;
59	u32 glb_rst_con;
60	u32 glb_rst_st;
61	u32 reserved10[0x1a];
62	u32 sdmmc_con[2];
63	u32 sdio0_con[2];
64	u32 sdio1_con[2];
65};
66check_member(rockchip_cru, sdio1_con[1], 0x594);
67#define KHz		1000
68#define OSC_HZ		(24*MHz)
69#define LPLL_HZ		(600*MHz)
70#define BPLL_HZ		(600*MHz)
71#define GPLL_HZ		(594*MHz)
72#define CPLL_HZ		(384*MHz)
73#define PPLL_HZ		(676*MHz)
74
75#define PMU_PCLK_HZ	(48*MHz)
76
77#define ACLKM_CORE_L_HZ	(300*MHz)
78#define ATCLK_CORE_L_HZ	(300*MHz)
79#define PCLK_DBG_L_HZ	(100*MHz)
80
81#define ACLKM_CORE_B_HZ	(300*MHz)
82#define ATCLK_CORE_B_HZ	(300*MHz)
83#define PCLK_DBG_B_HZ	(100*MHz)
84
85#define PERIHP_ACLK_HZ	(148500*KHz)
86#define PERIHP_HCLK_HZ	(148500*KHz)
87#define PERIHP_PCLK_HZ	(37125*KHz)
88
89#define PERILP0_ACLK_HZ	(99000*KHz)
90#define PERILP0_HCLK_HZ	(99000*KHz)
91#define PERILP0_PCLK_HZ	(49500*KHz)
92
93#define PERILP1_HCLK_HZ	(99000*KHz)
94#define PERILP1_PCLK_HZ	(49500*KHz)
95
96#define PWM_CLOCK_HZ    PMU_PCLK_HZ
97
98enum apll_l_frequencies {
99	APLL_L_1600_MHZ,
100	APLL_L_600_MHZ,
101};
102
103enum apll_b_frequencies {
104	APLL_B_600_MHZ,
105};
106
107void rk3399_configure_cpu_l(struct rockchip_cru *cru,
108			    enum apll_l_frequencies apll_l_freq);
109void rk3399_configure_cpu_b(struct rockchip_cru *cru,
110			    enum apll_b_frequencies apll_b_freq);
111
112#endif	/* __ASM_ARCH_CRU_RK3399_H_ */
113