#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
80274d1b |
|
22-Apr-2024 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add REF_CLK_USB3OTGx support The REF_CLK_USB3OTGx clocks is used as reference clock for USB3 block. Add simple support to get rate of REF_CLK_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
9f5df9a3 |
|
11-Mar-2024 |
Quentin Schulz <quentin.schulz@theobroma-systems.com> |
rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> |
#
e4916e2c |
|
12-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent Optimize setting process. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
cdf21a86 |
|
11-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: support aclk_top_root set 750M aclk_top_root choose a parent clock that does not change. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
39fb8aca |
|
11-Oct-2023 |
Guochun Huang <hero.huang@rock-chips.com> |
clk: rk3588: Add 742.5M parameter for PLL For a specific frequency. Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bb52f1c6 |
|
15-May-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
reset: rockchip: implement rk3588 lookup table The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> |
#
716ed2a8 |
|
13-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: rk3588: add hardcoded assigned clocks values The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
30850b69 |
|
11-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: correct trivial typo in debug message s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bdbfd589 |
|
18-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67377716 |
|
17-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
rockchip: rk3588: Add support for sdmmc clocks in SPL Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67a1d773 |
|
13-Mar-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
7a474df7 |
|
30-Jan-2023 |
Jagan Teki <jagan@edgeble.ai> |
clk: rockchip: Add rk3588 clk support Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> |
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
80274d1b |
|
22-Apr-2024 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add REF_CLK_USB3OTGx support The REF_CLK_USB3OTGx clocks is used as reference clock for USB3 block. Add simple support to get rate of REF_CLK_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
9f5df9a3 |
|
11-Mar-2024 |
Quentin Schulz <quentin.schulz@theobroma-systems.com> |
rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> |
#
e4916e2c |
|
12-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent Optimize setting process. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
cdf21a86 |
|
11-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: support aclk_top_root set 750M aclk_top_root choose a parent clock that does not change. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
39fb8aca |
|
11-Oct-2023 |
Guochun Huang <hero.huang@rock-chips.com> |
clk: rk3588: Add 742.5M parameter for PLL For a specific frequency. Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bb52f1c6 |
|
15-May-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
reset: rockchip: implement rk3588 lookup table The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> |
#
716ed2a8 |
|
13-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: rk3588: add hardcoded assigned clocks values The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
30850b69 |
|
11-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: correct trivial typo in debug message s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bdbfd589 |
|
18-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67377716 |
|
17-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
rockchip: rk3588: Add support for sdmmc clocks in SPL Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67a1d773 |
|
13-Mar-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
7a474df7 |
|
30-Jan-2023 |
Jagan Teki <jagan@edgeble.ai> |
clk: rockchip: Add rk3588 clk support Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> |
#
80274d1b |
|
22-Apr-2024 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add REF_CLK_USB3OTGx support The REF_CLK_USB3OTGx clocks is used as reference clock for USB3 block. Add simple support to get rate of REF_CLK_USB3OTGx clocks to fix reference clock period configuration. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
9f5df9a3 |
|
11-Mar-2024 |
Quentin Schulz <quentin.schulz@theobroma-systems.com> |
rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> |
#
e4916e2c |
|
12-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent Optimize setting process. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
cdf21a86 |
|
11-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: support aclk_top_root set 750M aclk_top_root choose a parent clock that does not change. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
39fb8aca |
|
11-Oct-2023 |
Guochun Huang <hero.huang@rock-chips.com> |
clk: rk3588: Add 742.5M parameter for PLL For a specific frequency. Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bb52f1c6 |
|
15-May-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
reset: rockchip: implement rk3588 lookup table The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> |
#
716ed2a8 |
|
13-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: rk3588: add hardcoded assigned clocks values The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
30850b69 |
|
11-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: correct trivial typo in debug message s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bdbfd589 |
|
18-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67377716 |
|
17-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
rockchip: rk3588: Add support for sdmmc clocks in SPL Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67a1d773 |
|
13-Mar-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
7a474df7 |
|
30-Jan-2023 |
Jagan Teki <jagan@edgeble.ai> |
clk: rockchip: Add rk3588 clk support Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> |
#
9f5df9a3 |
|
11-Mar-2024 |
Quentin Schulz <quentin.schulz@theobroma-systems.com> |
rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> |
#
e4916e2c |
|
12-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent Optimize setting process. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
cdf21a86 |
|
11-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: support aclk_top_root set 750M aclk_top_root choose a parent clock that does not change. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
39fb8aca |
|
11-Oct-2023 |
Guochun Huang <hero.huang@rock-chips.com> |
clk: rk3588: Add 742.5M parameter for PLL For a specific frequency. Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bb52f1c6 |
|
15-May-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
reset: rockchip: implement rk3588 lookup table The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> |
#
716ed2a8 |
|
13-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: rk3588: add hardcoded assigned clocks values The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
30850b69 |
|
11-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: correct trivial typo in debug message s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bdbfd589 |
|
18-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67377716 |
|
17-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
rockchip: rk3588: Add support for sdmmc clocks in SPL Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67a1d773 |
|
13-Mar-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
7a474df7 |
|
30-Jan-2023 |
Jagan Teki <jagan@edgeble.ai> |
clk: rockchip: Add rk3588 clk support Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> |
#
e4916e2c |
|
12-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent Optimize setting process. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
cdf21a86 |
|
11-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3588: support aclk_top_root set 750M aclk_top_root choose a parent clock that does not change. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
39fb8aca |
|
11-Oct-2023 |
Guochun Huang <hero.huang@rock-chips.com> |
clk: rk3588: Add 742.5M parameter for PLL For a specific frequency. Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bb52f1c6 |
|
15-May-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
reset: rockchip: implement rk3588 lookup table The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> |
#
716ed2a8 |
|
13-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: rk3588: add hardcoded assigned clocks values The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
30850b69 |
|
11-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: correct trivial typo in debug message s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bdbfd589 |
|
18-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67377716 |
|
17-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
rockchip: rk3588: Add support for sdmmc clocks in SPL Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67a1d773 |
|
13-Mar-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
7a474df7 |
|
30-Jan-2023 |
Jagan Teki <jagan@edgeble.ai> |
clk: rockchip: Add rk3588 clk support Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> |
#
bb52f1c6 |
|
15-May-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
reset: rockchip: implement rk3588 lookup table The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> |
#
716ed2a8 |
|
13-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: rk3588: add hardcoded assigned clocks values The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
30850b69 |
|
11-Apr-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
clk: rockchip: correct trivial typo in debug message s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
bdbfd589 |
|
18-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67377716 |
|
17-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
rockchip: rk3588: Add support for sdmmc clocks in SPL Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67a1d773 |
|
13-Mar-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
7a474df7 |
|
30-Jan-2023 |
Jagan Teki <jagan@edgeble.ai> |
clk: rockchip: Add rk3588 clk support Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> |
#
bdbfd589 |
|
18-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67377716 |
|
17-Apr-2023 |
Jonas Karlman <jonas@kwiboo.se> |
rockchip: rk3588: Add support for sdmmc clocks in SPL Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
67a1d773 |
|
13-Mar-2023 |
Jonas Karlman <jonas@kwiboo.se> |
clk: rockchip: rk3588: Fix clk_aux16m in clock driver The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
#
7a474df7 |
|
30-Jan-2023 |
Jagan Teki <jagan@edgeble.ai> |
clk: rockchip: Add rk3588 clk support Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> |
#
7a474df7 |
|
30-Jan-2023 |
Jagan Teki <jagan@edgeble.ai> |
clk: rockchip: Add rk3588 clk support Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> |