/seL4-refos-master/projects/util_libs/libutils/include/utils/ |
H A D | frequency.h | 19 #define MHZ (1000 * KHZ) macro 20 #define GHZ (1000 * MHZ) 28 } else if (hz % MHZ == 0) { 29 return ncycles * MS_IN_S / (hz / MHZ);
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/seL4-refos-master/libs/libutils/include/utils/ |
H A D | frequency.h | 19 #define MHZ (1000 * KHZ) macro 20 #define GHZ (1000 * MHZ) 28 } else if (hz % MHZ == 0) { 29 return ncycles * MS_IN_S / (hz / MHZ);
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/seL4-refos-master/libs/libplatsupport/src/plat/bcm2837/ |
H A D | clock.c | 49 [CLK_MASTER] = 0 * MHZ, 50 [CLK_SP804] = 250 * MHZ,
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H A D | spt.c | 129 uint64_t ticks = ns / (NS_IN_US / (spt->freq / MHZ)); 184 uint64_t ns = (value * MHZ / spt->freq) * NS_IN_US;
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/bcm2837/ |
H A D | clock.c | 49 [CLK_MASTER] = 0 * MHZ, 50 [CLK_SP804] = 250 * MHZ,
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/seL4-refos-master/libs/libplatsupport/src/plat/zynqmp/ |
H A D | clock.c | 38 [CLK_CPU_1X] = 1100 * MHZ,
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/zynqmp/ |
H A D | clock.c | 38 [CLK_CPU_1X] = 1100 * MHZ,
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/seL4-refos-master/libs/libplatsupport/src/plat/exynos4/ |
H A D | clock.c | 388 [CLK_MOUTAPLL] = 1000 * MHZ, 389 [CLK_MUXHPM] = 1000 * MHZ, 390 [CLK_DIVCOPY] = 200 * MHZ, 391 [CLK_SCLKHPM] = 200 * MHZ, 392 [CLK_MUXCORE] = 1000 * MHZ, 393 [CLK_ATCLK] = 200 * MHZ, 394 [CLK_PCLK_DBG] = 100 * MHZ, 395 [CLK_DIVCORE] = 1000 * MHZ, 396 [CLK_DIVCORE2] = 1000 * MHZ, 397 [CLK_PERIPHCLK] = 125 * MHZ, [all...] |
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos4/ |
H A D | clock.c | 388 [CLK_MOUTAPLL] = 1000 * MHZ, 389 [CLK_MUXHPM] = 1000 * MHZ, 390 [CLK_DIVCOPY] = 200 * MHZ, 391 [CLK_SCLKHPM] = 200 * MHZ, 392 [CLK_MUXCORE] = 1000 * MHZ, 393 [CLK_ATCLK] = 200 * MHZ, 394 [CLK_PCLK_DBG] = 100 * MHZ, 395 [CLK_DIVCORE] = 1000 * MHZ, 396 [CLK_DIVCORE2] = 1000 * MHZ, 397 [CLK_PERIPHCLK] = 125 * MHZ, [all...] |
/seL4-refos-master/libs/libsel4utils/arch_include/x86/sel4utils/arch/ |
H A D | tsc.h | 32 return freq * MHZ;
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/seL4-refos-master/projects/seL4_libs/libsel4utils/arch_include/x86/sel4utils/arch/ |
H A D | tsc.h | 32 return freq * MHZ;
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/seL4-refos-master/libs/libplatsupport/src/plat/exynos5/ |
H A D | clock.c | 392 [CLK_MASTER ] = 24 * MHZ, 393 [CLK_SCLKVPLL] = 24 * MHZ, 394 [CLK_SCLKGPLL] = 1056 * MHZ, 395 [CLK_SCLKBPLL] = 800 * MHZ, 396 [CLK_PWM ] = 24 * MHZ, 397 [CLK_SCLKCPLL] = 640 * MHZ, 398 [CLK_UART3 ] = 64 * MHZ, 399 [CLK_UART2 ] = 64 * MHZ, 400 [CLK_UART1 ] = 64 * MHZ, 401 [CLK_UART0 ] = 64 * MHZ, [all...] |
/seL4-refos-master/libs/libplatsupport/src/plat/imx31/ |
H A D | clock.c | 51 [CLK_MASTER] = 24 * MHZ,
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/seL4-refos-master/libs/libplatsupport/src/plat/omap3/ |
H A D | clock.c | 51 [CLK_MASTER] = 24 * MHZ,
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos5/ |
H A D | clock.c | 392 [CLK_MASTER ] = 24 * MHZ, 393 [CLK_SCLKVPLL] = 24 * MHZ, 394 [CLK_SCLKGPLL] = 1056 * MHZ, 395 [CLK_SCLKBPLL] = 800 * MHZ, 396 [CLK_PWM ] = 24 * MHZ, 397 [CLK_SCLKCPLL] = 640 * MHZ, 398 [CLK_UART3 ] = 64 * MHZ, 399 [CLK_UART2 ] = 64 * MHZ, 400 [CLK_UART1 ] = 64 * MHZ, 401 [CLK_UART0 ] = 64 * MHZ, [all...] |
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/imx31/ |
H A D | clock.c | 51 [CLK_MASTER] = 24 * MHZ,
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/omap3/ |
H A D | clock.c | 51 [CLK_MASTER] = 24 * MHZ,
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/seL4-refos-master/libs/libplatsupport/src/plat/zynq7000/ |
H A D | clock.c | 1041 [CLK_ARM_PLL] = 1333 * MHZ, 1042 [CLK_DDR_PLL] = 1067 * MHZ, 1043 [CLK_IO_PLL] = 1000 * MHZ, 1044 [CLK_CPU_6OR4X] = 667 * MHZ, 1045 [CLK_CPU_3OR2X] = 333 * MHZ, 1046 [CLK_CPU_2X] = 222 * MHZ, 1047 [CLK_CPU_1X] = 111 * MHZ, 1048 [CLK_DDR_2X] = 356 * MHZ, 1049 [CLK_DDR_3X] = 533 * MHZ, 1050 [CLK_DCI] = 10 * MHZ, [all...] |
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/zynq7000/ |
H A D | clock.c | 1041 [CLK_ARM_PLL] = 1333 * MHZ, 1042 [CLK_DDR_PLL] = 1067 * MHZ, 1043 [CLK_IO_PLL] = 1000 * MHZ, 1044 [CLK_CPU_6OR4X] = 667 * MHZ, 1045 [CLK_CPU_3OR2X] = 333 * MHZ, 1046 [CLK_CPU_2X] = 222 * MHZ, 1047 [CLK_CPU_1X] = 111 * MHZ, 1048 [CLK_DDR_2X] = 356 * MHZ, 1049 [CLK_DDR_3X] = 533 * MHZ, 1050 [CLK_DCI] = 10 * MHZ, [all...] |
/seL4-refos-master/libs/libplatsupport/plat_include/bcm2837/platsupport/plat/ |
H A D | system_timer.h | 23 #define SYSTEM_TIMER_FREQ (1 * MHZ)
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/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/bcm2837/platsupport/plat/ |
H A D | system_timer.h | 23 #define SYSTEM_TIMER_FREQ (1 * MHZ)
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/seL4-refos-master/libs/libplatsupport/src/plat/imx6/ |
H A D | clock.c | 305 printf("Set ENET frequency to %ld Mhz... ", (long int)clk_get_freq(clk) / MHZ); 358 assert(hz == 528 * MHZ); 392 assert(hz == 528 * MHZ); 692 [CLK_MASTER] = 24 * MHZ, 693 [CLK_PLL2 ] = 528 * MHZ, 694 [CLK_MMDC_CH0] = 528 * MHZ, 695 [CLK_AHB] = 132 * MHZ, 696 [CLK_IPG] = 66 * MHZ, 697 [CLK_ARM] = 792 * MHZ, 698 [CLK_ENET] = 48 * MHZ, [all...] |
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/imx6/ |
H A D | clock.c | 305 printf("Set ENET frequency to %ld Mhz... ", (long int)clk_get_freq(clk) / MHZ); 358 assert(hz == 528 * MHZ); 392 assert(hz == 528 * MHZ); 692 [CLK_MASTER] = 24 * MHZ, 693 [CLK_PLL2 ] = 528 * MHZ, 694 [CLK_MMDC_CH0] = 528 * MHZ, 695 [CLK_AHB] = 132 * MHZ, 696 [CLK_IPG] = 66 * MHZ, 697 [CLK_ARM] = 792 * MHZ, 698 [CLK_ENET] = 48 * MHZ, [all...] |
/seL4-refos-master/libs/libplatsupport/src/plat/apq8064/ |
H A D | clock.c | 176 [CLK_MASTER] = 24 * MHZ, 177 [CLK_PXO ] = 27 * MHZ, 178 [CLK_WCNXO ] = 48 * MHZ,
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/apq8064/ |
H A D | clock.c | 176 [CLK_MASTER] = 24 * MHZ, 177 [CLK_PXO ] = 27 * MHZ, 178 [CLK_WCNXO ] = 48 * MHZ,
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