Lines Matching refs:MHZ
388 [CLK_MOUTAPLL] = 1000 * MHZ,
389 [CLK_MUXHPM] = 1000 * MHZ,
390 [CLK_DIVCOPY] = 200 * MHZ,
391 [CLK_SCLKHPM] = 200 * MHZ,
392 [CLK_MUXCORE] = 1000 * MHZ,
393 [CLK_ATCLK] = 200 * MHZ,
394 [CLK_PCLK_DBG] = 100 * MHZ,
395 [CLK_DIVCORE] = 1000 * MHZ,
396 [CLK_DIVCORE2] = 1000 * MHZ,
397 [CLK_PERIPHCLK] = 125 * MHZ,
398 [CLK_ACLK_COREM1] = 167 * MHZ,
399 [CLK_ACLK_CORES] = 250 * MHZ,
400 [CLK_ACLK_COREM0] = 333 * MHZ,
401 [CLK_UART0] = 0 * MHZ,
402 [CLK_UART1] = 0 * MHZ,
403 [CLK_UART2] = 0 * MHZ,
404 [CLK_UART3] = 0 * MHZ,
405 [CLK_SCLKAPLL] = 500 * MHZ,
406 [CLK_SCLKVPLL] = 108 * MHZ,
407 [CLK_SCLKEPLL] = 96 * MHZ,
408 [CLK_SCLKMPLL] = 800 * MHZ,
409 [CLK_SCLKMPLL_USERC] = 800 * MHZ,
411 [CLK_SPI0] = 0 * MHZ,
412 [CLK_SPI1] = 0 * MHZ,
413 [CLK_SPI2] = 0 * MHZ,
414 [CLK_SPI0_ISP] = 0 * MHZ,
415 [CLK_SPI1_ISP] = 0 * MHZ,