Lines Matching refs:MHZ
392 [CLK_MASTER ] = 24 * MHZ,
393 [CLK_SCLKVPLL] = 24 * MHZ,
394 [CLK_SCLKGPLL] = 1056 * MHZ,
395 [CLK_SCLKBPLL] = 800 * MHZ,
396 [CLK_PWM ] = 24 * MHZ,
397 [CLK_SCLKCPLL] = 640 * MHZ,
398 [CLK_UART3 ] = 64 * MHZ,
399 [CLK_UART2 ] = 64 * MHZ,
400 [CLK_UART1 ] = 64 * MHZ,
401 [CLK_UART0 ] = 64 * MHZ,
402 [CLK_SPI1_ISP] = 24 * MHZ,
403 [CLK_SPI0_ISP] = 24 * MHZ,
404 [CLK_SCLKMPLL] = 532 * MHZ,
406 [CLK_SCLKEPLL] = 24 * MHZ,
407 [CLK_SPI2 ] = 6 * MHZ,
408 [CLK_SPI0 ] = 6 * MHZ,