1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12#include <platsupport/i2c.h>
13
14#include "../../arch/arm/clock.h"
15#include "../../services.h"
16#include <assert.h>
17#include <string.h>
18#include <utils/util.h>
19
20#define CCM_PADDR        0x020C4000
21#define CCM_SIZE             0x1000
22
23#define CCM_ANALOG_PADDR 0x020C8000
24#define CCM_ANALOG_SIZE      0x1000
25
26/* Generic PLL */
27#define PLL_LOCK          BIT(31)
28#define PLL_BYPASS        BIT(16)
29
30/* SYS PLL */
31#define PLL_ARM_DIV_MASK  0x7F
32#define PLL_ARM_ENABLE    BIT(13)
33
34/* ENET PLL */
35#define PLL_ENET_DIV_MASK 0x3
36#define PLL_ENET_ENABLE   BIT(13)
37
38/* USB */
39#define PLL_USB_DIV_MASK  0x3
40#define PLL_EN_USB_CLKS   BIT(6)
41#define PLL_USB_ENABLE    BIT(13)
42#define PLL_USB_POWER     BIT(12)
43
44/* Also known as PLL_SYS */
45#define PLL2_PADDR 0x020C8030
46
47#define PLL2_CTRL_LOCK          BIT(31)
48#define PLL2_CTRL_PDFOFFSET_EN  BIT(18)
49#define PLL2_CTRL_BYPASS        BIT(16)
50#define PLL2_CTRL_BYPASS_SRC(x) ((x) << 14)
51#define PLL2_CTRL_ENABLE        BIT(13)
52#define PLL2_CTRL_PWR_DOWN      BIT(12)
53#define PLL2_CTRL_DIVSEL        BIT(0)
54#define PLL2_SS_STOP(x)         ((x) << 16)
55#define PLL2_SS_EN              BIT(15)
56#define PLL2_SS_STEP(x)         ((x) <<  0)
57
58#define PLL_CLKGATE BIT(31)
59#define PLL_STABLE  BIT(30)
60#define PLL_FRAC(x) ((x) << 24)
61
62#define CLKGATE_OFF    0x0
63#define CLKGATE_ON_RUN 0x2
64#define CLKGATE_ON_ALL 0x3
65#define CLKGATE_MASK   CLKGATE_ON_ALL
66
67#define CLKO1_SRC_AHB       (0xBU << 0)
68#define CLKO1_SRC_IPG       (0xCU << 0)
69#define CLKO1_SRC_MASK      (0xFU << 0)
70#define CLKO1_ENABLE        (1U << 7)
71
72#define CLKO2_SRC_MMDC_CH0  (0U << 21)
73#define CLKO2_SRC_MASK      (0x1FU << 16)
74#define CLKO2_ENABLE        (1U << 24)
75#define CLKO_SEL            (1U << 8)
76
77struct ccm_regs {
78    uint32_t ccr;      /* 0x000 */
79    uint32_t ccdr;     /* 0x004 */
80    uint32_t csr;      /* 0x008 */
81    uint32_t ccsr;     /* 0x00C */
82    uint32_t cacrr;    /* 0x010 */
83    uint32_t cbcdr;    /* 0x014 */
84    uint32_t cbcmr;    /* 0x018 */
85    uint32_t cscmr1;   /* 0x01C */
86    uint32_t cscmr2;   /* 0x020 */
87    uint32_t cscdr1;   /* 0x024 */
88    uint32_t cs1cdr;   /* 0x028 */
89    uint32_t cs2cdr;   /* 0x02C */
90    uint32_t cdcdr;    /* 0x030 */
91    uint32_t chsccdr;  /* 0x034 */
92    uint32_t cscdr2;   /* 0x038 */
93    uint32_t cscdr3;   /* 0x03C */
94    uint32_t res0[2];
95    uint32_t cdhipr;   /* 0x048 */
96    uint32_t res1[1];
97    uint32_t ctor;     /* 0x050 */
98    uint32_t clpcr;    /* 0x054 */
99    uint32_t cisr;     /* 0x058 */
100    uint32_t cimr;     /* 0x05C */
101    uint32_t ccosr;    /* 0x060 */
102    uint32_t cgpr;     /* 0x064 */
103    uint32_t ccgr[7];  /* 0x068 */
104    uint32_t res2[1];
105    uint32_t cmeor;    /* 0x088 */
106};
107
108typedef struct {
109    uint32_t val;
110    uint32_t set;
111    uint32_t clr;
112    uint32_t tog;
113} alg_sct_t;
114
115struct ccm_alg_usbphy_regs {
116    alg_sct_t vbus_detect;           /* +0x00 */
117    alg_sct_t chrg_detect;           /* +0x10 */
118    uint32_t vbus_detect_stat;       /* +0x20 */
119    uint32_t res0[3];
120    uint32_t chrg_detect_stat;       /* +0x30 */
121    uint32_t res1[3];
122    uint32_t res2[4];
123    alg_sct_t misc;                  /* +0x50 */
124};
125
126struct ccm_alg_regs {
127    /* PLL_ARM */
128    alg_sct_t pll_arm;               /* 0x000 */
129    /* PLL_USB * 2 */
130    alg_sct_t pll_usb[2];            /* 0x010 */
131    /* PLL_SYS */
132    alg_sct_t pll_sys;               /* 0x030 */
133    uint32_t  pll_sys_ss;            /* 0x040 */
134    uint32_t  res0[3];
135    uint32_t  pll_sys_num;           /* 0x050 */
136    uint32_t  res1[3];
137    uint32_t  pll_sys_denom;         /* 0x060 */
138    uint32_t  res2[3];
139    /* PLL_AUDIO */
140    alg_sct_t pll_audio;             /* 0x070 */
141    uint32_t  pll_audio_num;         /* 0x080 */
142    uint32_t  res3[3];
143    uint32_t  pll_audio_denom;       /* 0x090 */
144    uint32_t  res4[3];
145    /* PLL_VIDIO */
146    alg_sct_t pll_video;             /* 0x0A0 */
147    uint32_t  pll_video_num;         /* 0x0B0 */
148    uint32_t  res5[3];
149    uint32_t  pll_video_denom;       /* 0x0C0 */
150    uint32_t  res6[3];
151    /* PLL_MLB */
152    alg_sct_t pll_mlb;               /* 0x0D0 */
153    /* PLL_ENET */
154    alg_sct_t pll_enet;              /* 0x0E0 */
155    /* PDF_480 */
156    alg_sct_t pfd_480;               /* 0x0F0 */
157    /* PDF_528 */
158    alg_sct_t pfd_528;               /* 0x100 */
159    uint32_t  res7[16];
160    /* MISC0 */
161    alg_sct_t misc0;                 /* 0x150 */
162    uint32_t  res8[4];
163    /* MISC2 */
164    alg_sct_t misc2;                 /* 0x170 */
165    uint32_t  res9[11];
166    /* USB phy control - Implemented here for the sake of
167     * componentisation since it shares the same register space */
168    struct ccm_alg_usbphy_regs phy1; /* 0x1a0 */
169    struct ccm_alg_usbphy_regs phy2; /* 0x200 */
170    uint32_t digprog;                /* 0x260 */
171};
172
173static volatile struct clock_regs {
174    struct ccm_regs     * ccm;
175    struct ccm_alg_regs * alg;
176} clk_regs = {.ccm = NULL, .alg = NULL};
177
178struct pll2_regs {
179    uint32_t ctrl;
180    uint32_t ctrl_s;
181    uint32_t ctrl_c;
182    uint32_t ctrl_t;
183    uint32_t ss;
184    uint32_t res0[3];
185    uint32_t num;
186    uint32_t res1[3];
187    uint32_t denom;
188    uint32_t res2[3];
189};
190
191static struct clock master_clk = { CLK_OPS_DEFAULT(MASTER) };
192
193/* ARM_CLK */
194static freq_t
195_arm_get_freq(clk_t* clk)
196{
197    uint32_t div;
198    uint32_t fout, fin;
199    div = clk_regs.alg->pll_arm.val;
200    div &= PLL_ARM_DIV_MASK;
201    fin = clk_get_freq(clk->parent);
202    fout = fin * div / 2;
203    return fout;
204}
205
206static freq_t
207_arm_set_freq(clk_t* clk, freq_t hz)
208{
209    uint32_t div;
210    uint32_t fin;
211    uint32_t v;
212
213    fin = clk_get_freq(clk->parent);
214    div = 2 * hz / fin;
215    div = INRANGE(54, div, 108);
216    /* bypass on during clock manipulation */
217    clk_regs.alg->pll_arm.set = PLL_BYPASS;
218    /* Set the divisor */
219    v = clk_regs.alg->pll_arm.val & ~(PLL_ARM_DIV_MASK);
220    v |= div;
221    clk_regs.alg->pll_arm.val = v;
222    /* wait for lock */
223    while (!(clk_regs.alg->pll_arm.val & PLL_LOCK));
224    /* bypass off */
225    clk_regs.alg->pll_arm.clr = PLL_BYPASS;
226    return clk_get_freq(clk);
227}
228
229static void
230_arm_recal(clk_t* clk UNUSED)
231{
232    assert(0);
233}
234
235static clk_t*
236_arm_init(clk_t* clk)
237{
238    if (clk->priv == NULL) {
239        clk_t* parent;
240        parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER);
241        clk_register_child(parent, clk);
242        clk->priv = (void*)&clk_regs;
243    }
244    return clk;
245}
246
247static struct clock arm_clk = { CLK_OPS(ARM, arm, NULL) };
248
249/* ENET_CLK */
250
251static freq_t
252_enet_get_freq(clk_t* clk)
253{
254    uint32_t div;
255    uint32_t fin;
256
257    fin = clk_get_freq(clk->parent);
258    div = clk_regs.alg->pll_enet.val;
259    div &= PLL_ENET_DIV_MASK;
260    switch (div) {
261    case 3:
262        return 5 * fin;
263    case 2:
264        return 4 * fin;
265    case 1:
266        return 2 * fin;
267    case 0:
268        return 1 * fin;
269    default:
270        return 0 * fin;
271    }
272}
273
274static freq_t
275_enet_set_freq(clk_t* clk, freq_t hz)
276{
277    uint32_t div, fin;
278    uint32_t v;
279    if (clk_regs.alg == NULL) {
280        return clk_get_freq(clk);
281    }
282    fin = clk_get_freq(clk->parent);
283    if (hz >= 5 * fin) {
284        div = 3;
285    } else if (hz >= 4 * fin) {
286        div = 2;
287    } else if (hz >= 2 * fin) {
288        div = 1;
289    } else if (hz >= 1 * fin) {
290        div = 0;
291    } else {
292        div = 0;
293    }
294    /* bypass on */
295    clk_regs.alg->pll_enet.set = PLL_BYPASS;
296    v = PLL_ENET_ENABLE | PLL_BYPASS;
297    clk_regs.alg->pll_enet.val = v;
298    /* Change the frequency */
299    v = clk_regs.alg->pll_enet.val & ~(PLL_ENET_DIV_MASK);
300    v |= div;
301    clk_regs.alg->pll_enet.val = v;
302    while (!(clk_regs.alg->pll_enet.val & PLL_LOCK));
303    /* bypass off */
304    clk_regs.alg->pll_enet.clr = PLL_BYPASS;
305    printf("Set ENET frequency to %ld Mhz... ", (long int)clk_get_freq(clk) / MHZ);
306    return clk_get_freq(clk);
307}
308
309static void
310_enet_recal(clk_t* clk UNUSED)
311{
312    assert(0);
313}
314
315static clk_t*
316_enet_init(clk_t* clk)
317{
318    if (clk->priv == NULL) {
319        clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER);
320        clk_register_child(parent, clk);
321        clk->priv = (void*)&clk_regs;
322    }
323    return clk;
324}
325
326static struct clock enet_clk = { CLK_OPS(ENET, enet, NULL) };
327
328/* PLL2_CLK */
329static freq_t
330_pll2_get_freq(clk_t* clk)
331{
332    uint32_t p, s;
333    struct pll2_regs *regs;
334    regs = (struct pll2_regs*)((uint32_t)clk_regs.alg + (PLL2_PADDR & 0xfff));
335    assert((regs->ctrl & PLL2_CTRL_LOCK) != 0);
336    assert((regs->ctrl & PLL2_CTRL_BYPASS) == 0);
337    assert((regs->ctrl & PLL2_CTRL_PWR_DOWN) == 0);
338    /* pdf offset? */
339
340    p = clk_get_freq(clk->parent);
341    if (regs->ctrl & PLL2_CTRL_DIVSEL) {
342        s = 22;
343    } else {
344        s = 20;
345    }
346    return p * s;
347}
348
349static freq_t
350_pll2_set_freq(clk_t* clk, freq_t hz)
351{
352    uint32_t s;
353    if (clk_regs.alg == NULL) {
354        return clk_get_freq(clk);
355    }
356    s = hz / clk_get_freq(clk->parent);
357    (void)s; /* TODO implement */
358    assert(hz == 528 * MHZ);
359    return clk_get_freq(clk);
360}
361
362static void
363_pll2_recal(clk_t* clk UNUSED)
364{
365    assert(0);
366}
367
368static clk_t*
369_pll2_init(clk_t* clk)
370{
371    if (clk->parent == NULL) {
372        clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER);
373        clk_register_child(parent, clk);
374        clk->priv = (void*)&clk_regs;
375    }
376    return clk;
377}
378
379static struct clock pll2_clk = { CLK_OPS(PLL2, pll2, NULL) };
380
381/* MMDC_CH0_CLK */
382static freq_t
383_mmdc_ch0_get_freq(clk_t* clk)
384{
385    return clk_get_freq(clk->parent);
386}
387
388static freq_t
389_mmdc_ch0_set_freq(clk_t* clk, freq_t hz)
390{
391    /* TODO there is a mux here */
392    assert(hz == 528 * MHZ);
393    return clk_set_freq(clk->parent, hz);
394}
395
396static void
397_mmdc_ch0_recal(clk_t* clk UNUSED)
398{
399    assert(0);
400}
401
402static clk_t*
403_mmdc_ch0_init(clk_t* clk)
404{
405    if (clk->parent == NULL) {
406        clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_PLL2);
407        clk_register_child(parent, clk);
408        clk->priv = (void*)&clk_regs;
409    }
410    return clk;
411}
412
413static struct clock mmdc_ch0_clk = { CLK_OPS(MMDC_CH0, mmdc_ch0, NULL) };
414
415/* AHB_CLK_ROOT */
416static freq_t
417_ahb_get_freq(clk_t* clk)
418{
419    return clk_get_freq(clk->parent) / 4;
420}
421
422static freq_t
423_ahb_set_freq(clk_t* clk, freq_t hz)
424{
425    return clk_set_freq(clk->parent, hz * 4);
426}
427
428static void
429_ahb_recal(clk_t* clk UNUSED)
430{
431    assert(0);
432}
433
434static clk_t*
435_ahb_init(clk_t* clk)
436{
437    if (clk->parent == NULL) {
438        clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MMDC_CH0);
439        clk_register_child(parent, clk);
440        clk->priv = (void*)&clk_regs;
441    }
442    return clk;
443}
444
445static struct clock ahb_clk = { CLK_OPS(AHB, ahb, NULL) };
446
447/* IPG_CLK_ROOT */
448static freq_t
449_ipg_get_freq(clk_t* clk)
450{
451    return clk_get_freq(clk->parent) / 2;
452};
453
454static freq_t
455_ipg_set_freq(clk_t* clk, freq_t hz)
456{
457    return clk_set_freq(clk->parent, hz * 2);
458};
459
460static void
461_ipg_recal(clk_t* clk UNUSED)
462{
463    assert(0);
464}
465
466static clk_t*
467_ipg_init(clk_t* clk)
468{
469    if (clk->parent == NULL) {
470        clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_AHB);
471        clk_register_child(parent, clk);
472        clk->priv = (void*)&clk_regs;
473    }
474    return clk;
475}
476
477static struct clock ipg_clk = { CLK_OPS(IPG, ipg, NULL) };
478
479/* USB_CLK */
480static freq_t
481_usb_get_freq(clk_t* clk)
482{
483    volatile alg_sct_t* pll_usb;
484    pll_usb = clk_regs.alg->pll_usb;
485    if (clk->id == CLK_USB2) {
486        pll_usb++;
487    } else if (clk->id != CLK_USB1) {
488        assert(0);
489        return 0;
490    }
491    if (pll_usb->val & ~PLL_BYPASS) {
492        if (pll_usb->val & (PLL_USB_ENABLE | PLL_USB_POWER | PLL_EN_USB_CLKS)) {
493            uint32_t div = (pll_usb->val & PLL_USB_DIV_MASK) ? 22 : 20;
494            return clk_get_freq(clk->parent) * div;
495        }
496    }
497    /* Not enabled or in bypass mode...
498     * We should only be in bypass when changing Fout */
499    return 0;
500}
501
502static freq_t
503_usb_set_freq(clk_t* clk, freq_t hz UNUSED)
504{
505    assert(!"Not implemented");
506    return clk_get_freq(clk);
507}
508
509static void
510_usb_recal(clk_t* clk UNUSED)
511{
512    assert(0);
513}
514
515static clk_t*
516_usb_init(clk_t* clk)
517{
518    volatile alg_sct_t* pll_usb;
519    if (clk->parent == NULL) {
520        clk_t* parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MASTER);
521        clk_register_child(parent, clk);
522        clk->priv = (void*)&clk_regs;
523    }
524    if (clk_regs.alg == NULL) {
525        ZF_LOGF("clk_regs.alg is NULL: Clocks likely not initialised properly");
526        return NULL;
527    }
528    /* While we are here, gate the clocks */
529    pll_usb = clk_regs.alg->pll_usb;
530    if (clk->id == CLK_USB2) {
531        pll_usb++;
532    } else if (clk->id != CLK_USB1) {
533        assert(0);
534        return NULL;
535    }
536    pll_usb->clr = PLL_BYPASS;
537    pll_usb->set = PLL_USB_ENABLE | PLL_USB_POWER | PLL_EN_USB_CLKS;
538    clk_gate_enable(clk_get_clock_sys(clk), usboh3, CLKGATE_ON);
539    return clk;
540}
541
542static struct clock usb1_clk = { CLK_OPS(USB1, usb, NULL) };
543static struct clock usb2_clk = { CLK_OPS(USB2, usb, NULL) };
544
545/* clkox */
546static freq_t
547_clko_get_freq(clk_t* clk)
548{
549    uint32_t fin = clk_get_freq(clk->parent);
550    uint32_t div;
551    switch (clk->id) {
552    case CLK_CLKO1:
553        div = (clk_regs.ccm->ccosr >> 4) & 0x7;
554        break;
555    case CLK_CLKO2:
556        div = (clk_regs.ccm->ccosr >> 21) & 0x7;
557        break;
558    default:
559        assert(!"Invalid clock");
560        return -1;
561    }
562    return fin / (div + 1);
563}
564
565static freq_t
566_clko_set_freq(clk_t* clk, freq_t hz)
567{
568    uint32_t fin = clk_get_freq(clk->parent);
569    uint32_t div = (fin / hz) + 1;
570    uint32_t v = clk_regs.ccm->ccosr;
571    if (div > 0x7) {
572        div = 0x7;
573    }
574    switch (clk->id) {
575    case CLK_CLKO1:
576        v &= ~(0x7U << 4);
577        v |= div << 4;
578        break;
579    case CLK_CLKO2:
580        v &= ~(0x7U << 21);
581        v |= div << 21;
582        break;
583    default:
584        assert(!"Invalid clock");
585        return -1;
586    }
587    clk_regs.ccm->ccosr = v;
588    return clk_get_freq(clk);
589}
590
591static void
592_clko_recal(clk_t* clk UNUSED)
593{
594    assert(0);
595}
596
597static clk_t*
598_clko_init(clk_t* clk)
599{
600    assert(clk_get_clock_sys(clk));
601    if (clk->parent == NULL) {
602        /* We currently only support 1 src, but there are many to choose from */
603        clk_t* parent;
604        uint32_t v = clk_regs.ccm->ccosr;
605        switch (clk->id) {
606        case CLK_CLKO1:
607            parent = clk_get_clock(clk_get_clock_sys(clk), CLK_IPG);
608            /* set source */
609            v &= ~CLKO1_SRC_MASK;
610            v |= CLKO1_SRC_IPG;
611            /* Enable */
612            v |= CLKO1_ENABLE;
613            /* Output to CCM_CLKO1 output */
614            v &= ~CLKO_SEL;
615            break;
616        case CLK_CLKO2:
617            /* set source */
618            parent = clk_get_clock(clk_get_clock_sys(clk), CLK_MMDC_CH0);
619            v &= ~CLKO2_SRC_MASK;
620            v |= CLKO2_SRC_MMDC_CH0;
621            /* Enable */
622            v |= CLKO2_ENABLE;
623            break;
624        default:
625            assert(!"Invalid clock for operation");
626            return NULL;
627        }
628        clk_regs.ccm->ccosr = v;
629        clk_register_child(parent, clk);
630    }
631    return clk;
632}
633
634static struct clock clko1_clk = { CLK_OPS(CLKO1, clko, NULL) };
635static struct clock clko2_clk = { CLK_OPS(CLKO2, clko, NULL) };
636
637static int
638imx6_gate_enable(clock_sys_t* clock_sys, enum clock_gate gate, enum clock_gate_mode mode)
639{
640    assert(clk_regs.ccm);
641    assert(mode == CLKGATE_ON);
642    (void)assert(gate >= 0);
643    assert(gate < 112);
644
645    uint32_t v;
646    uint32_t reg = gate / 16;
647    uint32_t shift = (gate & 0xf) * 2;
648    v = clk_regs.ccm->ccgr[reg];
649    v &= ~(CLKGATE_MASK << shift);
650    v |= (CLKGATE_ON_ALL << shift);
651    clk_regs.ccm->ccgr[reg] = v;
652    return 0;
653}
654
655int
656clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys)
657{
658    MAP_IF_NULL(o, CCM       , clk_regs.ccm);
659    MAP_IF_NULL(o, CCM_ANALOG, clk_regs.alg);
660    clock_sys->priv = (void*)&clk_regs;
661    clock_sys->get_clock = &ps_get_clock;
662    clock_sys->gate_enable = &imx6_gate_enable;
663    return 0;
664}
665
666void
667clk_print_clock_tree(clock_sys_t* sys)
668{
669    clk_t *clk = clk_get_clock(sys, CLK_MASTER);
670    clk_print_tree(clk, "");
671}
672
673clk_t* ps_clocks[] = {
674    [CLK_MASTER]   = &master_clk,
675    [CLK_PLL2  ]   = &pll2_clk,
676    [CLK_MMDC_CH0] = &mmdc_ch0_clk,
677    [CLK_AHB]      = &ahb_clk,
678    [CLK_IPG]      = &ipg_clk,
679    [CLK_ARM]      = &arm_clk,
680    [CLK_ENET]     = &enet_clk,
681    [CLK_USB1]     = &usb1_clk,
682    [CLK_USB2]     = &usb2_clk,
683    [CLK_CLKO1]    = &clko1_clk,
684    [CLK_CLKO2]    = &clko2_clk,
685};
686
687/* These frequencies are NOT the recommended
688 * frequencies. They are to be used when we
689 * need to make assumptions about what u-boot
690 * has left us with. */
691freq_t ps_freq_default[] = {
692    [CLK_MASTER]   =  24 * MHZ,
693    [CLK_PLL2  ]   = 528 * MHZ,
694    [CLK_MMDC_CH0] = 528 * MHZ,
695    [CLK_AHB]      = 132 * MHZ,
696    [CLK_IPG]      =  66 * MHZ,
697    [CLK_ARM]      = 792 * MHZ,
698    [CLK_ENET]     =  48 * MHZ,
699    [CLK_USB1]     = 480 * MHZ,
700    [CLK_USB2]     = 480 * MHZ,
701    [CLK_CLKO1]    =  66 * MHZ,
702    [CLK_CLKO2]    = 528 * MHZ,
703};
704