Searched refs:mcr (Results 1 - 25 of 168) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-msm/
H A Didle.S11 mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
14 mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
15 mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
16 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
18 mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/
H A Dtlb-fa.S42 mcr p15, 0, r3, c7, c10, 4 @ drain WB
45 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
49 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
56 mcr p15, 0, r3, c7, c10, 4 @ drain WB
59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
63 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
64 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
65 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush
H A Dproc-fa526.S45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
72 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
82 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
87 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
91 mcr p15, 0, r0, c7, c10, 4 @ drain WB
108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
110 mcr p1
[all...]
H A Dproc-arm940.S43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
53 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
54 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
55 mcr p15, 0, ip, c7, c10, 4 @ drain WB
59 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
67 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
98 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
102 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
152 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
157 mcr p1
[all...]
H A Dproc-mohawk.S57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
74 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
75 mcr p15, 0, ip, c7, c10, 4 @ drain WB
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
92 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
113 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
137 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
140 mcr p1
[all...]
H A Dtlb-v6.S39 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
57 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
86 mcr p1
[all...]
H A Dproc-arm920.S75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
194 mcr p1
[all...]
H A Dproc-arm922.S77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
195 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
196 mcr p1
[all...]
H A Dproc-sa110.S40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
67 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
68 mcr p15, 0, ip, c7, c10, 4 @ drain WB
70 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
75 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
92 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
98 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
102 mcr p1
[all...]
H A Dcache-v6.S29 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
30 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
31 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
32 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
50 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
52 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
57 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
120 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
128 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
130 mcr p1
[all...]
H A Dproc-arm1020e.S85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
140 mcr p15, 0, ip, c7, c10, 4 @ drain WB
143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
212 mcr p1
[all...]
H A Dproc-arm1020.S85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
140 mcr p15, 0, ip, c7, c10, 4 @ drain WB
143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
144 mcr p15, 0, ip, c7, c10, 4 @ drain WB
174 mcr p1
[all...]
H A Dproc-arm925.S49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
71 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
72 mcr p15, 0, ip, c7, c10, 4 @ drain WB
74 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
79 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
93 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
94 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
95 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
117 mcr p1
[all...]
H A Dproc-arm946.S50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
60 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
61 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
62 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
93 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
97 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
127 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
130 mcr p1
[all...]
H A Dproc-arm1022.S74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
90 mcr p15, 0, ip, c7, c10, 4 @ drain WB
92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
131 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
201 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
204 mcr p1
[all...]
H A Dproc-arm1026.S74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
90 mcr p15, 0, ip, c7, c10, 4 @ drain WB
92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
156 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
195 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
198 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 mcr p1
[all...]
H A Dcache-fa.S56 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
82 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
117 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
118 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
123 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
124 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
125 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
139 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
144 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
145 mcr p1
[all...]
H A Dproc-v6.S48 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
74 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
79 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
101 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
102 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
103 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
104 mcr p15, 0, r1, c13, c0, 1 @ set context ID
161 mcr p15, 0, r0, c1, c0, 1
165 mcr p1
[all...]
H A Dtlb-v7.S45 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
47 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
54 mcr p15, 0, ip, c7, c1, 6 @ flush BTAC/BTB Inner Shareable
56 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
78 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
87 mcr p15, 0, r2, c7, c1, 6 @ flush BTAC/BTB Inner Shareable
89 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
H A Dproc-arm926.S67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
102 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
107 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
109 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
132 mcr p1
[all...]
H A Dtlb-v4wb.S38 mcr p15, 0, r3, c7, c10, 4 @ drain WB
43 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
60 mcr p15, 0, r3, c7, c10, 4 @ drain WB
63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dtlb-v4wbi.S37 mcr p15, 0, r3, c7, c10, 4 @ drain WB
43 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
51 mcr p15, 0, r3, c7, c10, 4 @ drain WB
54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/timemachine/openssl-0.9.8e/test/
H A Dtests.com70 $ mcr 'texe_dir''evptest' evptests.txt
73 $ mcr 'texe_dir''destest'
76 $ mcr 'texe_dir''ideatest'
79 $ mcr 'texe_dir''shatest'
80 $ mcr 'texe_dir''sha1test'
83 $ mcr 'texe_dir''mdc2test'
86 $ mcr 'texe_dir''md5test'
89 $ mcr 'texe_dir''md4test'
92 $ mcr 'texe_dir''hmactest'
95 $ mcr 'texe_di
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/drivers/pci/
H A Dfixups-rts7751r2d.c44 unsigned long bcr1, mcr; local
57 mcr = __raw_readl(SH7751_MCR);
58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
59 pci_write_reg(chan, mcr, SH4_PCIMCR);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/boot/compressed/
H A Dbig-endian.S12 mcr p15, 0, r0, c1, c0, 0 @ write control reg

Completed in 207 milliseconds

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