Lines Matching refs:mcr
77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
195 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
196 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
200 mcr p15, 0, r0, c7, c10, 4 @ drain WB
214 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
219 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
242 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
265 mcr p15, 0, r0, c7, c10, 4 @ drain WB
278 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
325 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
346 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
354 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
360 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
361 mcr p15, 0, ip, c7, c10, 4 @ drain WB
362 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
363 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
377 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
378 mcr p15, 0, r0, c7, c10, 4 @ drain WB
387 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
388 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
390 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4