Lines Matching refs:mcr
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
198 mcr p15, 0, r0, c7, c10, 4 @ drain WB
212 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
217 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
218 mcr p15, 0, r0, c7, c10, 4 @ drain WB
240 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
244 mcr p15, 0, r0, c7, c10, 4 @ drain WB
259 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
263 mcr p15, 0, r0, c7, c10, 4 @ drain WB
276 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
280 mcr p15, 0, r0, c7, c10, 4 @ drain WB
322 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
342 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
350 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
356 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
357 mcr p15, 0, ip, c7, c10, 4 @ drain WB
358 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
359 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
373 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374 mcr p15, 0, r0, c7, c10, 4 @ drain WB
383 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
384 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
386 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4