1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv6 processor support. 12 */ 13#include <linux/init.h> 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/hwcap.h> 18#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable.h> 20 21#include "proc-macros.S" 22 23#define D_CACHE_LINE_SIZE 32 24 25#define TTB_C (1 << 0) 26#define TTB_S (1 << 1) 27#define TTB_IMP (1 << 2) 28#define TTB_RGN_NC (0 << 3) 29#define TTB_RGN_WBWA (1 << 3) 30#define TTB_RGN_WT (2 << 3) 31#define TTB_RGN_WB (3 << 3) 32 33#ifndef CONFIG_SMP 34#define TTB_FLAGS TTB_RGN_WBWA 35#define PMD_FLAGS PMD_SECT_WB 36#else 37#define TTB_FLAGS TTB_RGN_WBWA|TTB_S 38#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S 39#endif 40 41ENTRY(cpu_v6_proc_init) 42 mov pc, lr 43 44ENTRY(cpu_v6_proc_fin) 45 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 bic r0, r0, #0x1000 @ ...i............ 47 bic r0, r0, #0x0006 @ .............ca. 48 mcr p15, 0, r0, c1, c0, 0 @ disable caches 49 mov pc, lr 50 51/* 52 * cpu_v6_reset(loc) 53 * 54 * Perform a soft reset of the system. Put the CPU into the 55 * same state as it would be if it had been reset, and branch 56 * to what would be the reset vector. 57 * 58 * - loc - location to jump to for soft reset 59 */ 60 .align 5 61ENTRY(cpu_v6_reset) 62 mov pc, r0 63 64/* 65 * cpu_v6_do_idle() 66 * 67 * Idle the processor (eg, wait for interrupt). 68 * 69 * IRQs are already disabled. 70 */ 71ENTRY(cpu_v6_do_idle) 72 mov r1, #0 73 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 74 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 75 mov pc, lr 76 77ENTRY(cpu_v6_dcache_clean_area) 78#ifndef TLB_CAN_READ_FROM_L1_CACHE 791: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 80 add r0, r0, #D_CACHE_LINE_SIZE 81 subs r1, r1, #D_CACHE_LINE_SIZE 82 bhi 1b 83#endif 84 mov pc, lr 85 86/* 87 * cpu_arm926_switch_mm(pgd_phys, tsk) 88 * 89 * Set the translation table base pointer to be pgd_phys 90 * 91 * - pgd_phys - physical address of new TTB 92 * 93 * It is assumed that: 94 * - we are not using split page tables 95 */ 96ENTRY(cpu_v6_switch_mm) 97#ifdef CONFIG_MMU 98 mov r2, #0 99 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 100 orr r0, r0, #TTB_FLAGS 101 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 102 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 103 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 104 mcr p15, 0, r1, c13, c0, 1 @ set context ID 105#endif 106 mov pc, lr 107 108/* 109 * cpu_v6_set_pte_ext(ptep, pte, ext) 110 * 111 * Set a level 2 translation table entry. 112 * 113 * - ptep - pointer to level 2 translation table entry 114 * (hardware version is stored at -1024 bytes) 115 * - pte - PTE value to store 116 * - ext - value for extended PTE bits 117 */ 118 armv6_mt_table cpu_v6 119 120ENTRY(cpu_v6_set_pte_ext) 121#ifdef CONFIG_MMU 122 armv6_set_pte_ext cpu_v6 123#endif 124 mov pc, lr 125 126 127 128 .type cpu_v6_name, #object 129cpu_v6_name: 130 .asciz "ARMv6-compatible processor" 131 .size cpu_v6_name, . - cpu_v6_name 132 133 .type cpu_pj4_name, #object 134cpu_pj4_name: 135 .asciz "Marvell PJ4 processor" 136 .size cpu_pj4_name, . - cpu_pj4_name 137 138 .align 139 140 __INIT 141 142/* 143 * __v6_setup 144 * 145 * Initialise TLB, Caches, and MMU state ready to switch the MMU 146 * on. Return in r0 the new CP15 C1 control register setting. 147 * 148 * We automatically detect if we have a Harvard cache, and use the 149 * Harvard cache control instructions insead of the unified cache 150 * control instructions. 151 * 152 * This should be able to cover all ARMv6 cores. 153 * 154 * It is assumed that: 155 * - cache type register is implemented 156 */ 157__v6_setup: 158#ifdef CONFIG_SMP 159 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 160 orr r0, r0, #0x20 161 mcr p15, 0, r0, c1, c0, 1 162#endif 163 164 mov r0, #0 165 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 166 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 167 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 168 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 169#ifdef CONFIG_MMU 170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 172 orr r4, r4, #TTB_FLAGS 173 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 174#endif /* CONFIG_MMU */ 175 adr r5, v6_crval 176 ldmia r5, {r5, r6} 177#ifdef CONFIG_CPU_ENDIAN_BE8 178 orr r6, r6, #1 << 25 @ big-endian page tables 179#endif 180 mrc p15, 0, r0, c1, c0, 0 @ read control register 181 bic r0, r0, r5 @ clear bits them 182 orr r0, r0, r6 @ set them 183 mov pc, lr @ return to head.S:__ret 184 185 .type v6_crval, #object 186v6_crval: 187 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c 188 189 .type v6_processor_functions, #object 190ENTRY(v6_processor_functions) 191 .word v6_early_abort 192 .word v6_pabort 193 .word cpu_v6_proc_init 194 .word cpu_v6_proc_fin 195 .word cpu_v6_reset 196 .word cpu_v6_do_idle 197 .word cpu_v6_dcache_clean_area 198 .word cpu_v6_switch_mm 199 .word cpu_v6_set_pte_ext 200 .size v6_processor_functions, . - v6_processor_functions 201 202 .type cpu_arch_name, #object 203cpu_arch_name: 204 .asciz "armv6" 205 .size cpu_arch_name, . - cpu_arch_name 206 207 .type cpu_elf_name, #object 208cpu_elf_name: 209 .asciz "v6" 210 .size cpu_elf_name, . - cpu_elf_name 211 .align 212 213 .section ".proc.info.init", #alloc, #execinstr 214 215 /* 216 * Match any ARMv6 processor core. 217 */ 218 .type __v6_proc_info, #object 219__v6_proc_info: 220 .long 0x0007b000 221 .long 0x0007f000 222 .long PMD_TYPE_SECT | \ 223 PMD_SECT_AP_WRITE | \ 224 PMD_SECT_AP_READ | \ 225 PMD_FLAGS 226 .long PMD_TYPE_SECT | \ 227 PMD_SECT_XN | \ 228 PMD_SECT_AP_WRITE | \ 229 PMD_SECT_AP_READ 230 b __v6_setup 231 .long cpu_arch_name 232 .long cpu_elf_name 233 /* See also feat_v6_fixup() for HWCAP_TLS */ 234 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS 235 .long cpu_v6_name 236 .long v6_processor_functions 237 .long v6wbi_tlb_fns 238 .long v6_user_fns 239 .long v6_cache_fns 240 .size __v6_proc_info, . - __v6_proc_info 241 242 .type __pj4_v6_proc_info, #object 243__pj4_v6_proc_info: 244 .long 0x560f5810 245 .long 0xff0ffff0 246 .long PMD_TYPE_SECT | \ 247 PMD_SECT_AP_WRITE | \ 248 PMD_SECT_AP_READ | \ 249 PMD_FLAGS 250 .long PMD_TYPE_SECT | \ 251 PMD_SECT_XN | \ 252 PMD_SECT_AP_WRITE | \ 253 PMD_SECT_AP_READ 254 b __v6_setup 255 .long cpu_arch_name 256 .long cpu_elf_name 257 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS 258 .long cpu_pj4_name 259 .long v6_processor_functions 260 .long v6wbi_tlb_fns 261 .long v6_user_fns 262 .long v6_cache_fns 263 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info 264