Lines Matching refs:mcr
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
71 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
72 mcr p15, 0, ip, c7, c10, 4 @ drain WB
74 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
79 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
93 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
94 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
95 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
117 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
121 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
147 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
150 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
157 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
192 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
193 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
197 mcr p15, 0, r0, c7, c10, 4 @ drain WB
211 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
216 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
217 mcr p15, 0, r0, c7, c10, 4 @ drain WB
241 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
245 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
266 mcr p15, 0, r0, c7, c10, 4 @ drain WB
281 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
283 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
288 mcr p15, 0, r0, c7, c10, 4 @ drain WB
328 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
333 mcr p15, 0, r0, c7, c10, 4 @ drain WB
350 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
354 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
358 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
359 mcr p15, 0, ip, c7, c10, 4 @ drain WB
360 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
361 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
376 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
378 mcr p15, 0, r0, c7, c10, 4 @ drain WB
393 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
396 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
397 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
399 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
404 mcr p15, 7, r0, c15, c0, 0