Lines Matching refs:mcr
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
72 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
82 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
87 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
91 mcr p15, 0, r0, c7, c10, 4 @ drain WB
108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
113 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
114 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
115 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
116 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
117 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
131 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
133 mcr p15, 0, r0, c7, c10, 4 @ drain WB
143 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
146 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
148 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
151 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
154 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
155 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
156 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
159 mcr p15, 0, r0, c3, c0 @ load domain access register