Searched refs:SRL (Results 1 - 25 of 34) sorted by relevance

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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr;
H A DARMISelLowering.cpp129 setOperationAction(ISD::SRL, VT, Custom);
545 setTargetDAGCombine(ISD::SRL);
612 setOperationAction(ISD::SRL, MVT::i64, Custom);
805 setTargetDAGCombine(ISD::SRL);
3433 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3439 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3473 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3503 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3539 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3565 assert((N->getOpcode() == ISD::SRL ||
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DISDOpcodes.h316 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430ISelLowering.h64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon10421
H A DMSP430ISelLowering.cpp97 setOperationAction(ISD::SRL, MVT::i8, Custom);
100 setOperationAction(ISD::SRL, MVT::i16, Custom);
184 case ISD::SRL:
607 case ISD::SRL:
608 return DAG.getNode(MSP430ISD::SRL, dl,
619 if (Opc == ISD::SRL && ShiftAmount) {
823 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp367 } else if (Opcode == ISD::SRL) {
414 Op0.getOperand(0).getOpcode() == ISD::SRL) {
416 Op1.getOperand(0).getOpcode() != ISD::SRL) {
422 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
424 Op1.getOperand(0).getOpcode() != ISD::SRL) {
435 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
442 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
1047 case ISD::SRL: {
H A DPPCISelLowering.h91 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
H A DPPCISelLowering.cpp508 case PPCISD::SRL: return "PPCISD::SRL";
1346 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
4008 DAG.getNode(ISD::SRL, dl, MVT::i32,
4040 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
4057 "Unexpected SRL!");
4068 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4073 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
4075 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
4096 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, d
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
666 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
796 case ISD::SRL:
1162 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1301 DAG.getNode(ISD::SRL, DL, NVT, InL,
1307 if (N->getOpcode() == ISD::SRL) {
1312 Lo = DAG.getNode(ISD::SRL, DL,
1320 DAG.getNode(ISD::SRL, D
[all...]
H A DTargetLowering.cpp1434 if (InOp.getOpcode() == ISD::SRL &&
1442 Opc = ISD::SRL;
1484 case ISD::SRL:
1502 unsigned Opc = ISD::SRL;
1535 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1567 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1731 case ISD::SRL:
1732 // Shrink SRL by a constant if none of the high bits shifted in are
1735 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1759 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, d
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H A DLegalizeDAG.cpp397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
789 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
800 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
1270 case ISD::SRL:
2177 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2198 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2232 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2385 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2390 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2391 Tmp1 = DAG.getNode(ISD::SRL, d
[all...]
H A DDAGCombiner.cpp879 else if (Opc == ISD::SRL)
1120 case ISD::SRL: return visitSRL(N);
1203 case ISD::SRL:
1888 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, local
1891 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1892 AddToWorkList(SRL.getNode());
1942 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1956 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
2100 N1 = DAG.getNode(ISD::SRL, D
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H A DLegalizeVectorOps.cpp189 case ISD::SRL:
548 // Make sure that the SINT_TO_FP and SRL instructions are available.
550 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
570 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
H A DFastISel.cpp972 return SelectBinaryOp(I, ISD::SRL);
1133 Opcode = ISD::SRL;
1139 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
H A DSelectionDAGBuilder.h490 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
H A DSelectionDAGDumper.cpp173 case ISD::SRL: return "srl";
H A DSelectionDAG.cpp1842 case ISD::SRL:
2728 case ISD::SRL: return getConstant(C1.lshr(C2), VT);
2854 case ISD::SRL:
3120 case ISD::SRL:
3159 case ISD::SRL:
6022 case ISD::SRL:
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsISelLowering.cpp690 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
1971 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1972 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2018 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2019 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2059 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2084 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2163 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2165 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2204 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, D
2295 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUISelLowering.cpp243 setOperationAction(ISD::SRL, MVT::i8, Custom);
248 setOperationAction(ISD::SRL, MVT::i64, Legal);
2255 case ISD::SRL:
2399 DAG.getNode(ISD::SRL, dl, MVT::i16,
2430 DAG.getNode(ISD::SRL, dl, MVT::i32,
2442 DAG.getNode(ISD::SRL, dl, MVT::i32,
2535 DAG.getNode(ISD::SRL, dl, IntVT,
2569 DAG.getNode(ISD::SRL, dl, IntVT,
2815 case ISD::SRL:
H A DSPUISelDAGToDAG.cpp742 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
764 if (Op0.getOpcode() == ISD::SRL)
778 } else if (Opc == ISD::SRL) {
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86ISelLowering.cpp762 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
993 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
994 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1003 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1004 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1011 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1012 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1057 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1058 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1107 setOperationAction(ISD::SRL, MV
10844 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, local
10888 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, local
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H A DX86ISelDAGToDAG.cpp769 if (Shift.getOpcode() != ISD::SRL ||
783 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
879 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
936 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
1045 case ISD::SRL: {
1235 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
/macosx-10.9.5/llvmCore-3425.0.33/lib/TableGen/
H A DRecord.cpp922 case SRL: {
932 case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
957 case SRL: Result = "!srl"; break;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp123 case 0x41: return MBlaze::SRL;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/
H A DXCoreISelLowering.cpp450 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
523 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,

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