1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARMISelLowering.h" 17#include "ARM.h" 18#include "ARMCallingConv.h" 19#include "ARMConstantPoolValue.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMPerfectShuffle.h" 22#include "ARMSubtarget.h" 23#include "ARMTargetMachine.h" 24#include "ARMTargetObjectFile.h" 25#include "MCTargetDesc/ARMAddressingModes.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/Function.h" 29#include "llvm/GlobalValue.h" 30#include "llvm/Instruction.h" 31#include "llvm/Instructions.h" 32#include "llvm/Intrinsics.h" 33#include "llvm/Type.h" 34#include "llvm/CodeGen/CallingConvLower.h" 35#include "llvm/CodeGen/IntrinsicLowering.h" 36#include "llvm/CodeGen/MachineBasicBlock.h" 37#include "llvm/CodeGen/MachineFrameInfo.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineInstrBuilder.h" 40#include "llvm/CodeGen/MachineModuleInfo.h" 41#include "llvm/CodeGen/MachineRegisterInfo.h" 42#include "llvm/CodeGen/SelectionDAG.h" 43#include "llvm/MC/MCSectionMachO.h" 44#include "llvm/Target/TargetOptions.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/Statistic.h" 47#include "llvm/Support/CommandLine.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Support/raw_ostream.h" 51using namespace llvm; 52 53STATISTIC(NumTailCalls, "Number of tail calls"); 54STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt"); 55STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments"); 56 57// This option should go away when tail calls fully work. 58static cl::opt<bool> 59EnableARMTailCalls("arm-tail-calls", cl::Hidden, 60 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 61 cl::init(false)); 62 63cl::opt<bool> 64EnableARMLongCalls("arm-long-calls", cl::Hidden, 65 cl::desc("Generate calls via indirect call instructions"), 66 cl::init(false)); 67 68static cl::opt<bool> 69ARMInterworking("arm-interworking", cl::Hidden, 70 cl::desc("Enable / disable ARM interworking (for debugging only)"), 71 cl::init(true)); 72 73namespace { 74 class ARMCCState : public CCState { 75 public: 76 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 77 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, 78 LLVMContext &C, ParmContext PC) 79 : CCState(CC, isVarArg, MF, TM, locs, C) { 80 assert(((PC == Call) || (PC == Prologue)) && 81 "ARMCCState users must specify whether their context is call" 82 "or prologue generation."); 83 CallOrPrologue = PC; 84 } 85 }; 86} 87 88// The APCS parameter registers. 89static const uint16_t GPRArgRegs[] = { 90 ARM::R0, ARM::R1, ARM::R2, ARM::R3 91}; 92 93void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, 94 MVT PromotedBitwiseVT) { 95 if (VT != PromotedLdStVT) { 96 setOperationAction(ISD::LOAD, VT, Promote); 97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); 98 99 setOperationAction(ISD::STORE, VT, Promote); 100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); 101 } 102 103 MVT ElemTy = VT.getVectorElementType(); 104 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 105 setOperationAction(ISD::SETCC, VT, Custom); 106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 108 if (ElemTy == MVT::i32) { 109 setOperationAction(ISD::SINT_TO_FP, VT, Custom); 110 setOperationAction(ISD::UINT_TO_FP, VT, Custom); 111 setOperationAction(ISD::FP_TO_SINT, VT, Custom); 112 setOperationAction(ISD::FP_TO_UINT, VT, Custom); 113 } else { 114 setOperationAction(ISD::SINT_TO_FP, VT, Expand); 115 setOperationAction(ISD::UINT_TO_FP, VT, Expand); 116 setOperationAction(ISD::FP_TO_SINT, VT, Expand); 117 setOperationAction(ISD::FP_TO_UINT, VT, Expand); 118 } 119 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 120 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 121 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); 122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); 123 setOperationAction(ISD::SELECT, VT, Expand); 124 setOperationAction(ISD::SELECT_CC, VT, Expand); 125 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 126 if (VT.isInteger()) { 127 setOperationAction(ISD::SHL, VT, Custom); 128 setOperationAction(ISD::SRA, VT, Custom); 129 setOperationAction(ISD::SRL, VT, Custom); 130 } 131 132 // Promote all bit-wise operations. 133 if (VT.isInteger() && VT != PromotedBitwiseVT) { 134 setOperationAction(ISD::AND, VT, Promote); 135 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT); 136 setOperationAction(ISD::OR, VT, Promote); 137 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT); 138 setOperationAction(ISD::XOR, VT, Promote); 139 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT); 140 } 141 142 // Neon does not support vector divide/remainder operations. 143 setOperationAction(ISD::SDIV, VT, Expand); 144 setOperationAction(ISD::UDIV, VT, Expand); 145 setOperationAction(ISD::FDIV, VT, Expand); 146 setOperationAction(ISD::SREM, VT, Expand); 147 setOperationAction(ISD::UREM, VT, Expand); 148 setOperationAction(ISD::FREM, VT, Expand); 149} 150 151void ARMTargetLowering::addDRTypeForNEON(MVT VT) { 152 addRegisterClass(VT, &ARM::DPRRegClass); 153 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 154} 155 156void ARMTargetLowering::addQRTypeForNEON(MVT VT) { 157 addRegisterClass(VT, &ARM::QPRRegClass); 158 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 159} 160 161static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 162 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 163 return new TargetLoweringObjectFileMachO(); 164 165 return new ARMElfTargetObjectFile(); 166} 167 168ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 169 : TargetLowering(TM, createTLOF(TM)) { 170 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 171 RegInfo = TM.getRegisterInfo(); 172 Itins = TM.getInstrItineraryData(); 173 174 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 175 176 if (Subtarget->isTargetDarwin()) { 177 // Uses VFP for Thumb libfuncs if available. 178 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 179 // Single-precision floating-point arithmetic. 180 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 181 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 182 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 183 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 184 185 // Double-precision floating-point arithmetic. 186 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 187 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 188 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 189 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 190 191 // Single-precision comparisons. 192 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 193 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 194 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 195 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 196 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 197 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 198 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 199 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 200 201 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 202 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 203 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 204 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 205 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 206 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 207 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 208 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 209 210 // Double-precision comparisons. 211 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 212 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 213 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 214 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 215 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 216 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 217 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 218 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 219 220 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 221 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 222 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 223 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 224 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 225 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 226 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 227 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 228 229 // Floating-point to integer conversions. 230 // i64 conversions are done via library routines even when generating VFP 231 // instructions, so use the same ones. 232 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 233 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 234 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 235 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 236 237 // Conversions between floating types. 238 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 239 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 240 241 // Integer to floating-point conversions. 242 // i64 conversions are done via library routines even when generating VFP 243 // instructions, so use the same ones. 244 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 245 // e.g., __floatunsidf vs. __floatunssidfvfp. 246 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 247 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 248 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 249 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 250 } 251 } 252 253 // These libcalls are not available in 32-bit. 254 setLibcallName(RTLIB::SHL_I128, 0); 255 setLibcallName(RTLIB::SRL_I128, 0); 256 setLibcallName(RTLIB::SRA_I128, 0); 257 258 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetDarwin()) { 259 // Double-precision floating-point arithmetic helper functions 260 // RTABI chapter 4.1.2, Table 2 261 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 262 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 263 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 264 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 265 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 266 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 267 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 268 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 269 270 // Double-precision floating-point comparison helper functions 271 // RTABI chapter 4.1.2, Table 3 272 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 273 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 274 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 275 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 276 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 277 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 278 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 279 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 280 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 281 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 282 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 283 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 284 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 285 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 286 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 287 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 288 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 289 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 290 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 291 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 292 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 293 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 294 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 295 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 296 297 // Single-precision floating-point arithmetic helper functions 298 // RTABI chapter 4.1.2, Table 4 299 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 300 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 301 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 302 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 303 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 304 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 305 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 306 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 307 308 // Single-precision floating-point comparison helper functions 309 // RTABI chapter 4.1.2, Table 5 310 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 311 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 312 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 313 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 314 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 315 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 316 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 317 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 318 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 319 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 320 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 321 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 322 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 323 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 324 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 325 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 326 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 327 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 328 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 329 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 330 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 331 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 332 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 333 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 334 335 // Floating-point to integer conversions. 336 // RTABI chapter 4.1.2, Table 6 337 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 338 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 339 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 340 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 341 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 342 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 343 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 344 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 345 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 346 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 347 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 348 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 349 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 350 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 351 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 352 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 353 354 // Conversions between floating types. 355 // RTABI chapter 4.1.2, Table 7 356 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 357 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 358 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 359 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 360 361 // Integer to floating-point conversions. 362 // RTABI chapter 4.1.2, Table 8 363 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 364 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 365 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 366 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 367 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 368 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 369 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 370 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 371 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 372 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 373 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 374 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 375 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 376 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 377 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 378 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 379 380 // Long long helper functions 381 // RTABI chapter 4.2, Table 9 382 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 383 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 384 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 385 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 386 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 387 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 388 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 389 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 390 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 391 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 392 393 // Integer division functions 394 // RTABI chapter 4.3.1 395 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 396 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 397 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 398 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 399 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 400 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 401 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 402 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 403 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 404 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 405 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 406 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 407 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 408 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 409 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 410 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 411 412 // Memory operations 413 // RTABI chapter 4.3.4 414 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); 415 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); 416 setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); 417 setLibcallCallingConv(RTLIB::MEMCPY, CallingConv::ARM_AAPCS); 418 setLibcallCallingConv(RTLIB::MEMMOVE, CallingConv::ARM_AAPCS); 419 setLibcallCallingConv(RTLIB::MEMSET, CallingConv::ARM_AAPCS); 420 } 421 422 // Use divmod compiler-rt calls for iOS 5.0 and later. 423 if (Subtarget->getTargetTriple().getOS() == Triple::IOS && 424 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) { 425 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 426 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 427 } 428 429 if (Subtarget->isThumb1Only()) 430 addRegisterClass(MVT::i32, &ARM::tGPRRegClass); 431 else 432 addRegisterClass(MVT::i32, &ARM::GPRRegClass); 433 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() && 434 !Subtarget->isThumb1Only()) { 435 addRegisterClass(MVT::f32, &ARM::SPRRegClass); 436 if (!Subtarget->isFPOnlySP()) 437 addRegisterClass(MVT::f64, &ARM::DPRRegClass); 438 439 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 440 } 441 442 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 443 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 444 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 445 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 446 setTruncStoreAction((MVT::SimpleValueType)VT, 447 (MVT::SimpleValueType)InnerVT, Expand); 448 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 449 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 450 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 451 } 452 453 setOperationAction(ISD::ConstantFP, MVT::f32, Custom); 454 455 if (Subtarget->hasNEON()) { 456 addDRTypeForNEON(MVT::v2f32); 457 addDRTypeForNEON(MVT::v8i8); 458 addDRTypeForNEON(MVT::v4i16); 459 addDRTypeForNEON(MVT::v2i32); 460 addDRTypeForNEON(MVT::v1i64); 461 462 addQRTypeForNEON(MVT::v4f32); 463 addQRTypeForNEON(MVT::v2f64); 464 addQRTypeForNEON(MVT::v16i8); 465 addQRTypeForNEON(MVT::v8i16); 466 addQRTypeForNEON(MVT::v4i32); 467 addQRTypeForNEON(MVT::v2i64); 468 469 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 470 // neither Neon nor VFP support any arithmetic operations on it. 471 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively 472 // supported for v4f32. 473 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 474 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 475 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 476 // FIXME: Code duplication: FDIV and FREM are expanded always, see 477 // ARMTargetLowering::addTypeForNEON method for details. 478 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 479 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 480 // FIXME: Create unittest. 481 // In another words, find a way when "copysign" appears in DAG with vector 482 // operands. 483 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 484 // FIXME: Code duplication: SETCC has custom operation action, see 485 // ARMTargetLowering::addTypeForNEON method for details. 486 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 487 // FIXME: Create unittest for FNEG and for FABS. 488 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 489 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 490 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 491 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 492 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 493 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 494 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 495 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 496 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 497 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 498 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 499 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 500 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR. 501 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 502 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 503 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 504 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 505 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 506 507 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); 508 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); 509 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); 510 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand); 511 setOperationAction(ISD::FPOW, MVT::v4f32, Expand); 512 setOperationAction(ISD::FLOG, MVT::v4f32, Expand); 513 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); 514 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand); 515 setOperationAction(ISD::FEXP, MVT::v4f32, Expand); 516 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); 517 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand); 518 519 // Neon does not support some operations on v1i64 and v2i64 types. 520 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 521 // Custom handling for some quad-vector types to detect VMULL. 522 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 523 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 524 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 525 // Custom handling for some vector types to avoid expensive expansions 526 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 527 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 528 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 529 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); 530 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 531 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 532 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 533 // a destination type that is wider than the source, and nor does 534 // it have a FP_TO_[SU]INT instruction with a narrower destination than 535 // source. 536 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 537 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 538 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); 539 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); 540 541 setTargetDAGCombine(ISD::INTRINSIC_VOID); 542 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 543 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 544 setTargetDAGCombine(ISD::SHL); 545 setTargetDAGCombine(ISD::SRL); 546 setTargetDAGCombine(ISD::SRA); 547 setTargetDAGCombine(ISD::SIGN_EXTEND); 548 setTargetDAGCombine(ISD::ZERO_EXTEND); 549 setTargetDAGCombine(ISD::ANY_EXTEND); 550 setTargetDAGCombine(ISD::SELECT_CC); 551 setTargetDAGCombine(ISD::BUILD_VECTOR); 552 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 553 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 554 setTargetDAGCombine(ISD::STORE); 555 setTargetDAGCombine(ISD::FP_TO_SINT); 556 setTargetDAGCombine(ISD::FP_TO_UINT); 557 setTargetDAGCombine(ISD::FDIV); 558 559 // It is legal to extload from v4i8 to v4i16 or v4i32. 560 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8, 561 MVT::v4i16, MVT::v2i16, 562 MVT::v2i32}; 563 for (unsigned i = 0; i < 6; ++i) { 564 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal); 565 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal); 566 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal); 567 } 568 } 569 570 // ARM and Thumb2 support UMLAL/SMLAL. 571 if (!Subtarget->isThumb1Only()) 572 setTargetDAGCombine(ISD::ADDC); 573 574 575 computeRegisterProperties(); 576 577 // ARM does not have f32 extending load. 578 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 579 580 // ARM does not have i1 sign extending load. 581 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 582 583 // ARM supports all 4 flavors of integer indexed load / store. 584 if (!Subtarget->isThumb1Only()) { 585 for (unsigned im = (unsigned)ISD::PRE_INC; 586 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 587 setIndexedLoadAction(im, MVT::i1, Legal); 588 setIndexedLoadAction(im, MVT::i8, Legal); 589 setIndexedLoadAction(im, MVT::i16, Legal); 590 setIndexedLoadAction(im, MVT::i32, Legal); 591 setIndexedStoreAction(im, MVT::i1, Legal); 592 setIndexedStoreAction(im, MVT::i8, Legal); 593 setIndexedStoreAction(im, MVT::i16, Legal); 594 setIndexedStoreAction(im, MVT::i32, Legal); 595 } 596 } 597 598 // i64 operation support. 599 setOperationAction(ISD::MUL, MVT::i64, Expand); 600 setOperationAction(ISD::MULHU, MVT::i32, Expand); 601 if (Subtarget->isThumb1Only()) { 602 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 603 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 604 } 605 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() 606 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP())) 607 setOperationAction(ISD::MULHS, MVT::i32, Expand); 608 609 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 610 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 611 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 612 setOperationAction(ISD::SRL, MVT::i64, Custom); 613 setOperationAction(ISD::SRA, MVT::i64, Custom); 614 615 if (!Subtarget->isThumb1Only()) { 616 // FIXME: We should do this for Thumb1 as well. 617 setOperationAction(ISD::ADDC, MVT::i32, Custom); 618 setOperationAction(ISD::ADDE, MVT::i32, Custom); 619 setOperationAction(ISD::SUBC, MVT::i32, Custom); 620 setOperationAction(ISD::SUBE, MVT::i32, Custom); 621 } 622 623 // ARM does not have ROTL. 624 setOperationAction(ISD::ROTL, MVT::i32, Expand); 625 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 626 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 627 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 628 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 629 630 // These just redirect to CTTZ and CTLZ on ARM. 631 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand); 632 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand); 633 634 // Only ARMv6 has BSWAP. 635 if (!Subtarget->hasV6Ops()) 636 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 637 638 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) && 639 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) { 640 // These are expanded into libcalls if the cpu doesn't have HW divider. 641 setOperationAction(ISD::SDIV, MVT::i32, Expand); 642 setOperationAction(ISD::UDIV, MVT::i32, Expand); 643 } 644 setOperationAction(ISD::SREM, MVT::i32, Expand); 645 setOperationAction(ISD::UREM, MVT::i32, Expand); 646 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 647 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 648 649 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 650 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 651 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 652 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 653 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 654 655 setOperationAction(ISD::TRAP, MVT::Other, Legal); 656 657 // Use the default implementation. 658 setOperationAction(ISD::VASTART, MVT::Other, Custom); 659 setOperationAction(ISD::VAARG, MVT::Other, Expand); 660 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 661 setOperationAction(ISD::VAEND, MVT::Other, Expand); 662 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 663 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 664 665 if (!Subtarget->isTargetDarwin()) { 666 // Non-Darwin platforms may return values in these registers via the 667 // personality function. 668 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 669 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 670 setExceptionPointerRegister(ARM::R0); 671 setExceptionSelectorRegister(ARM::R1); 672 } 673 674 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 675 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 676 // the default expansion. 677 // FIXME: This should be checking for v6k, not just v6. 678 if (Subtarget->hasDataBarrier() || 679 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { 680 // membarrier needs custom lowering; the rest are legal and handled 681 // normally. 682 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 683 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 684 // Custom lowering for 64-bit ops 685 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 686 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 687 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 688 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 689 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 690 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 691 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 692 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. 693 setInsertFencesForAtomic(true); 694 } else { 695 // Set them all for expansion, which will force libcalls. 696 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 697 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 698 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 699 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 700 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 701 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 702 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 703 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 704 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 705 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 706 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 707 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 708 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 709 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 710 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the 711 // Unordered/Monotonic case. 712 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 713 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 714 // Since the libcalls include locking, fold in the fences 715 setShouldFoldAtomicFences(true); 716 } 717 718 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 719 720 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 721 if (!Subtarget->hasV6Ops()) { 722 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 723 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 724 } 725 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 726 727 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() && 728 !Subtarget->isThumb1Only()) { 729 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 730 // iff target supports vfp2. 731 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 732 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 733 } 734 735 // We want to custom lower some of our intrinsics. 736 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 737 if (Subtarget->isTargetDarwin()) { 738 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 739 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 740 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); 741 } 742 743 setOperationAction(ISD::SETCC, MVT::i32, Expand); 744 setOperationAction(ISD::SETCC, MVT::f32, Expand); 745 setOperationAction(ISD::SETCC, MVT::f64, Expand); 746 setOperationAction(ISD::SELECT, MVT::i32, Custom); 747 setOperationAction(ISD::SELECT, MVT::f32, Custom); 748 setOperationAction(ISD::SELECT, MVT::f64, Custom); 749 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 750 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 751 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 752 753 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 754 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 755 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 756 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 757 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 758 759 // We don't support sin/cos/fmod/copysign/pow 760 setOperationAction(ISD::FSIN, MVT::f64, Expand); 761 setOperationAction(ISD::FSIN, MVT::f32, Expand); 762 setOperationAction(ISD::FCOS, MVT::f32, Expand); 763 setOperationAction(ISD::FCOS, MVT::f64, Expand); 764 setOperationAction(ISD::FREM, MVT::f64, Expand); 765 setOperationAction(ISD::FREM, MVT::f32, Expand); 766 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() && 767 !Subtarget->isThumb1Only()) { 768 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 769 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 770 } 771 setOperationAction(ISD::FPOW, MVT::f64, Expand); 772 setOperationAction(ISD::FPOW, MVT::f32, Expand); 773 774 if (!Subtarget->hasVFP4()) { 775 setOperationAction(ISD::FMA, MVT::f64, Expand); 776 setOperationAction(ISD::FMA, MVT::f32, Expand); 777 } 778 779 // Various VFP goodness 780 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) { 781 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 782 if (Subtarget->hasVFP2()) { 783 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 784 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 785 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 786 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 787 } 788 // Special handling for half-precision FP. 789 if (!Subtarget->hasFP16()) { 790 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 791 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 792 } 793 } 794 795 // We have target-specific dag combine patterns for the following nodes: 796 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 797 setTargetDAGCombine(ISD::ADD); 798 setTargetDAGCombine(ISD::SUB); 799 setTargetDAGCombine(ISD::MUL); 800 setTargetDAGCombine(ISD::AND); 801 setTargetDAGCombine(ISD::OR); 802 setTargetDAGCombine(ISD::XOR); 803 804 if (Subtarget->hasV6Ops()) 805 setTargetDAGCombine(ISD::SRL); 806 807 setStackPointerRegisterToSaveRestore(ARM::SP); 808 809 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() || 810 !Subtarget->hasVFP2()) 811 setSchedulingPreference(Sched::RegPressure); 812 else 813 setSchedulingPreference(Sched::Hybrid); 814 815 //// temporary - rewrite interface to use type 816 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1; 817 maxStoresPerMemset = 16; 818 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 819 820 // On ARM arguments smaller than 4 bytes are extended, so all arguments 821 // are at least 4 bytes aligned. 822 setMinStackArgumentAlignment(4); 823 824 benefitFromCodePlacementOpt = true; 825 826 // Prefer likely predicted branches to selects on out-of-order cores. 827 predictableSelectIsExpensive = Subtarget->isLikeA9(); 828 829 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); 830} 831 832// FIXME: It might make sense to define the representative register class as the 833// nearest super-register that has a non-null superset. For example, DPR_VFP2 is 834// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, 835// SPR's representative would be DPR_VFP2. This should work well if register 836// pressure tracking were modified such that a register use would increment the 837// pressure of the register class's representative and all of it's super 838// classes' representatives transitively. We have not implemented this because 839// of the difficulty prior to coalescing of modeling operand register classes 840// due to the common occurrence of cross class copies and subregister insertions 841// and extractions. 842std::pair<const TargetRegisterClass*, uint8_t> 843ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 844 const TargetRegisterClass *RRC = 0; 845 uint8_t Cost = 1; 846 switch (VT.getSimpleVT().SimpleTy) { 847 default: 848 return TargetLowering::findRepresentativeClass(VT); 849 // Use DPR as representative register class for all floating point 850 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 851 // the cost is 1 for both f32 and f64. 852 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 853 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 854 RRC = &ARM::DPRRegClass; 855 // When NEON is used for SP, only half of the register file is available 856 // because operations that define both SP and DP results will be constrained 857 // to the VFP2 class (D0-D15). We currently model this constraint prior to 858 // coalescing by double-counting the SP regs. See the FIXME above. 859 if (Subtarget->useNEONForSinglePrecisionFP()) 860 Cost = 2; 861 break; 862 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 863 case MVT::v4f32: case MVT::v2f64: 864 RRC = &ARM::DPRRegClass; 865 Cost = 2; 866 break; 867 case MVT::v4i64: 868 RRC = &ARM::DPRRegClass; 869 Cost = 4; 870 break; 871 case MVT::v8i64: 872 RRC = &ARM::DPRRegClass; 873 Cost = 8; 874 break; 875 } 876 return std::make_pair(RRC, Cost); 877} 878 879const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 880 switch (Opcode) { 881 default: return 0; 882 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 883 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN"; 884 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; 885 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 886 case ARMISD::CALL: return "ARMISD::CALL"; 887 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 888 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 889 case ARMISD::tCALL: return "ARMISD::tCALL"; 890 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 891 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 892 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 893 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 894 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 895 case ARMISD::CMP: return "ARMISD::CMP"; 896 case ARMISD::CMN: return "ARMISD::CMN"; 897 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 898 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 899 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 900 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 901 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 902 903 case ARMISD::CMOV: return "ARMISD::CMOV"; 904 905 case ARMISD::RBIT: return "ARMISD::RBIT"; 906 907 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 908 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 909 case ARMISD::SITOF: return "ARMISD::SITOF"; 910 case ARMISD::UITOF: return "ARMISD::UITOF"; 911 912 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 913 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 914 case ARMISD::RRX: return "ARMISD::RRX"; 915 916 case ARMISD::ADDC: return "ARMISD::ADDC"; 917 case ARMISD::ADDE: return "ARMISD::ADDE"; 918 case ARMISD::SUBC: return "ARMISD::SUBC"; 919 case ARMISD::SUBE: return "ARMISD::SUBE"; 920 921 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 922 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 923 924 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 925 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 926 927 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 928 929 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 930 931 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 932 933 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 934 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; 935 936 case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; 937 938 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 939 case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; 940 case ARMISD::VCGE: return "ARMISD::VCGE"; 941 case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; 942 case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; 943 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 944 case ARMISD::VCGT: return "ARMISD::VCGT"; 945 case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; 946 case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; 947 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 948 case ARMISD::VTST: return "ARMISD::VTST"; 949 950 case ARMISD::VSHL: return "ARMISD::VSHL"; 951 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 952 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 953 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 954 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 955 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 956 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 957 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 958 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 959 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 960 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 961 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 962 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 963 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 964 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 965 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 966 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 967 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 968 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 969 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 970 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 971 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 972 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 973 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM"; 974 case ARMISD::VDUP: return "ARMISD::VDUP"; 975 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 976 case ARMISD::VEXT: return "ARMISD::VEXT"; 977 case ARMISD::VREV64: return "ARMISD::VREV64"; 978 case ARMISD::VREV32: return "ARMISD::VREV32"; 979 case ARMISD::VREV16: return "ARMISD::VREV16"; 980 case ARMISD::VZIP: return "ARMISD::VZIP"; 981 case ARMISD::VUZP: return "ARMISD::VUZP"; 982 case ARMISD::VTRN: return "ARMISD::VTRN"; 983 case ARMISD::VTBL1: return "ARMISD::VTBL1"; 984 case ARMISD::VTBL2: return "ARMISD::VTBL2"; 985 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 986 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 987 case ARMISD::UMLAL: return "ARMISD::UMLAL"; 988 case ARMISD::SMLAL: return "ARMISD::SMLAL"; 989 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 990 case ARMISD::FMAX: return "ARMISD::FMAX"; 991 case ARMISD::FMIN: return "ARMISD::FMIN"; 992 case ARMISD::BFI: return "ARMISD::BFI"; 993 case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; 994 case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; 995 case ARMISD::VBSL: return "ARMISD::VBSL"; 996 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; 997 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; 998 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; 999 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; 1000 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; 1001 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; 1002 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; 1003 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; 1004 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; 1005 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; 1006 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; 1007 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; 1008 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; 1009 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; 1010 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; 1011 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; 1012 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; 1013 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; 1014 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; 1015 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; 1016 } 1017} 1018 1019EVT ARMTargetLowering::getSetCCResultType(EVT VT) const { 1020 if (!VT.isVector()) return getPointerTy(); 1021 return VT.changeVectorElementTypeToInteger(); 1022} 1023 1024/// getRegClassFor - Return the register class that should be used for the 1025/// specified value type. 1026const TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 1027 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 1028 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 1029 // load / store 4 to 8 consecutive D registers. 1030 if (Subtarget->hasNEON()) { 1031 if (VT == MVT::v4i64) 1032 return &ARM::QQPRRegClass; 1033 if (VT == MVT::v8i64) 1034 return &ARM::QQQQPRRegClass; 1035 } 1036 return TargetLowering::getRegClassFor(VT); 1037} 1038 1039// Create a fast isel object. 1040FastISel * 1041ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 1042 const TargetLibraryInfo *libInfo) const { 1043 return ARM::createFastISel(funcInfo, libInfo); 1044} 1045 1046/// getMaximalGlobalOffset - Returns the maximal possible offset which can 1047/// be used for loads / stores from the global. 1048unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 1049 return (Subtarget->isThumb1Only() ? 127 : 4095); 1050} 1051 1052Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 1053 unsigned NumVals = N->getNumValues(); 1054 if (!NumVals) 1055 return Sched::RegPressure; 1056 1057 for (unsigned i = 0; i != NumVals; ++i) { 1058 EVT VT = N->getValueType(i); 1059 if (VT == MVT::Glue || VT == MVT::Other) 1060 continue; 1061 if (VT.isFloatingPoint() || VT.isVector()) 1062 return Sched::ILP; 1063 } 1064 1065 if (!N->isMachineOpcode()) 1066 return Sched::RegPressure; 1067 1068 // Load are scheduled for latency even if there instruction itinerary 1069 // is not available. 1070 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1071 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 1072 1073 if (MCID.getNumDefs() == 0) 1074 return Sched::RegPressure; 1075 if (!Itins->isEmpty() && 1076 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) 1077 return Sched::ILP; 1078 1079 return Sched::RegPressure; 1080} 1081 1082//===----------------------------------------------------------------------===// 1083// Lowering Code 1084//===----------------------------------------------------------------------===// 1085 1086/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1087static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1088 switch (CC) { 1089 default: llvm_unreachable("Unknown condition code!"); 1090 case ISD::SETNE: return ARMCC::NE; 1091 case ISD::SETEQ: return ARMCC::EQ; 1092 case ISD::SETGT: return ARMCC::GT; 1093 case ISD::SETGE: return ARMCC::GE; 1094 case ISD::SETLT: return ARMCC::LT; 1095 case ISD::SETLE: return ARMCC::LE; 1096 case ISD::SETUGT: return ARMCC::HI; 1097 case ISD::SETUGE: return ARMCC::HS; 1098 case ISD::SETULT: return ARMCC::LO; 1099 case ISD::SETULE: return ARMCC::LS; 1100 } 1101} 1102 1103/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1104static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 1105 ARMCC::CondCodes &CondCode2) { 1106 CondCode2 = ARMCC::AL; 1107 switch (CC) { 1108 default: llvm_unreachable("Unknown FP condition!"); 1109 case ISD::SETEQ: 1110 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1111 case ISD::SETGT: 1112 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1113 case ISD::SETGE: 1114 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1115 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1116 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1117 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 1118 case ISD::SETO: CondCode = ARMCC::VC; break; 1119 case ISD::SETUO: CondCode = ARMCC::VS; break; 1120 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 1121 case ISD::SETUGT: CondCode = ARMCC::HI; break; 1122 case ISD::SETUGE: CondCode = ARMCC::PL; break; 1123 case ISD::SETLT: 1124 case ISD::SETULT: CondCode = ARMCC::LT; break; 1125 case ISD::SETLE: 1126 case ISD::SETULE: CondCode = ARMCC::LE; break; 1127 case ISD::SETNE: 1128 case ISD::SETUNE: CondCode = ARMCC::NE; break; 1129 } 1130} 1131 1132//===----------------------------------------------------------------------===// 1133// Calling Convention Implementation 1134//===----------------------------------------------------------------------===// 1135 1136#include "ARMGenCallingConv.inc" 1137 1138/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1139/// given CallingConvention value. 1140CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 1141 bool Return, 1142 bool isVarArg) const { 1143 switch (CC) { 1144 default: 1145 llvm_unreachable("Unsupported calling convention"); 1146 case CallingConv::Fast: 1147 if (Subtarget->hasVFP2() && !isVarArg) { 1148 if (!Subtarget->isAAPCS_ABI()) 1149 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1150 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1151 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1152 } 1153 // Fallthrough 1154 case CallingConv::C: { 1155 // Use target triple & subtarget features to do actual dispatch. 1156 if (!Subtarget->isAAPCS_ABI()) 1157 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1158 else if (Subtarget->hasVFP2() && 1159 getTargetMachine().Options.FloatABIType == FloatABI::Hard && 1160 !isVarArg) 1161 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1162 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1163 } 1164 case CallingConv::ARM_AAPCS_VFP: 1165 if (!isVarArg) 1166 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1167 // Fallthrough 1168 case CallingConv::ARM_AAPCS: 1169 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1170 case CallingConv::ARM_APCS: 1171 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1172 case CallingConv::GHC: 1173 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC); 1174 } 1175} 1176 1177/// LowerCallResult - Lower the result values of a call into the 1178/// appropriate copies out of appropriate physical registers. 1179SDValue 1180ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1181 CallingConv::ID CallConv, bool isVarArg, 1182 const SmallVectorImpl<ISD::InputArg> &Ins, 1183 DebugLoc dl, SelectionDAG &DAG, 1184 SmallVectorImpl<SDValue> &InVals) const { 1185 1186 // Assign locations to each value returned by this call. 1187 SmallVector<CCValAssign, 16> RVLocs; 1188 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1189 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1190 CCInfo.AnalyzeCallResult(Ins, 1191 CCAssignFnForNode(CallConv, /* Return*/ true, 1192 isVarArg)); 1193 1194 // Copy all of the result registers out of their specified physreg. 1195 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1196 CCValAssign VA = RVLocs[i]; 1197 1198 SDValue Val; 1199 if (VA.needsCustom()) { 1200 // Handle f64 or half of a v2f64. 1201 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1202 InFlag); 1203 Chain = Lo.getValue(1); 1204 InFlag = Lo.getValue(2); 1205 VA = RVLocs[++i]; // skip ahead to next loc 1206 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1207 InFlag); 1208 Chain = Hi.getValue(1); 1209 InFlag = Hi.getValue(2); 1210 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1211 1212 if (VA.getLocVT() == MVT::v2f64) { 1213 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1214 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1215 DAG.getConstant(0, MVT::i32)); 1216 1217 VA = RVLocs[++i]; // skip ahead to next loc 1218 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1219 Chain = Lo.getValue(1); 1220 InFlag = Lo.getValue(2); 1221 VA = RVLocs[++i]; // skip ahead to next loc 1222 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1223 Chain = Hi.getValue(1); 1224 InFlag = Hi.getValue(2); 1225 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1226 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1227 DAG.getConstant(1, MVT::i32)); 1228 } 1229 } else { 1230 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1231 InFlag); 1232 Chain = Val.getValue(1); 1233 InFlag = Val.getValue(2); 1234 } 1235 1236 switch (VA.getLocInfo()) { 1237 default: llvm_unreachable("Unknown loc info!"); 1238 case CCValAssign::Full: break; 1239 case CCValAssign::BCvt: 1240 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1241 break; 1242 } 1243 1244 InVals.push_back(Val); 1245 } 1246 1247 return Chain; 1248} 1249 1250/// LowerMemOpCallTo - Store the argument to the stack. 1251SDValue 1252ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1253 SDValue StackPtr, SDValue Arg, 1254 DebugLoc dl, SelectionDAG &DAG, 1255 const CCValAssign &VA, 1256 ISD::ArgFlagsTy Flags) const { 1257 unsigned LocMemOffset = VA.getLocMemOffset(); 1258 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1259 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1260 return DAG.getStore(Chain, dl, Arg, PtrOff, 1261 MachinePointerInfo::getStack(LocMemOffset), 1262 false, false, 0); 1263} 1264 1265void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1266 SDValue Chain, SDValue &Arg, 1267 RegsToPassVector &RegsToPass, 1268 CCValAssign &VA, CCValAssign &NextVA, 1269 SDValue &StackPtr, 1270 SmallVector<SDValue, 8> &MemOpChains, 1271 ISD::ArgFlagsTy Flags) const { 1272 1273 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1274 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1275 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1276 1277 if (NextVA.isRegLoc()) 1278 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1279 else { 1280 assert(NextVA.isMemLoc()); 1281 if (StackPtr.getNode() == 0) 1282 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1283 1284 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1285 dl, DAG, NextVA, 1286 Flags)); 1287 } 1288} 1289 1290/// LowerCall - Lowering a call into a callseq_start <- 1291/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1292/// nodes. 1293SDValue 1294ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 1295 SmallVectorImpl<SDValue> &InVals) const { 1296 SelectionDAG &DAG = CLI.DAG; 1297 DebugLoc &dl = CLI.DL; 1298 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 1299 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 1300 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 1301 SDValue Chain = CLI.Chain; 1302 SDValue Callee = CLI.Callee; 1303 bool &isTailCall = CLI.IsTailCall; 1304 CallingConv::ID CallConv = CLI.CallConv; 1305 bool doesNotRet = CLI.DoesNotReturn; 1306 bool isVarArg = CLI.IsVarArg; 1307 1308 MachineFunction &MF = DAG.getMachineFunction(); 1309 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1310 bool IsSibCall = false; 1311 // Disable tail calls if they're not supported. 1312 if (!EnableARMTailCalls && !Subtarget->supportsTailCall()) 1313 isTailCall = false; 1314 if (isTailCall) { 1315 // Check if it's really possible to do a tail call. 1316 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1317 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1318 Outs, OutVals, Ins, DAG); 1319 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1320 // detected sibcalls. 1321 if (isTailCall) { 1322 ++NumTailCalls; 1323 IsSibCall = true; 1324 } 1325 } 1326 1327 // Analyze operands of the call, assigning locations to each operand. 1328 SmallVector<CCValAssign, 16> ArgLocs; 1329 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1330 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1331 CCInfo.AnalyzeCallOperands(Outs, 1332 CCAssignFnForNode(CallConv, /* Return*/ false, 1333 isVarArg)); 1334 1335 // Get a count of how many bytes are to be pushed on the stack. 1336 unsigned NumBytes = CCInfo.getNextStackOffset(); 1337 1338 // For tail calls, memory operands are available in our caller's stack. 1339 if (IsSibCall) 1340 NumBytes = 0; 1341 1342 // Adjust the stack pointer for the new arguments... 1343 // These operations are automatically eliminated by the prolog/epilog pass 1344 if (!IsSibCall) 1345 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1346 1347 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1348 1349 RegsToPassVector RegsToPass; 1350 SmallVector<SDValue, 8> MemOpChains; 1351 1352 // Walk the register/memloc assignments, inserting copies/loads. In the case 1353 // of tail call optimization, arguments are handled later. 1354 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1355 i != e; 1356 ++i, ++realArgIdx) { 1357 CCValAssign &VA = ArgLocs[i]; 1358 SDValue Arg = OutVals[realArgIdx]; 1359 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1360 bool isByVal = Flags.isByVal(); 1361 1362 // Promote the value if needed. 1363 switch (VA.getLocInfo()) { 1364 default: llvm_unreachable("Unknown loc info!"); 1365 case CCValAssign::Full: break; 1366 case CCValAssign::SExt: 1367 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1368 break; 1369 case CCValAssign::ZExt: 1370 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1371 break; 1372 case CCValAssign::AExt: 1373 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1374 break; 1375 case CCValAssign::BCvt: 1376 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1377 break; 1378 } 1379 1380 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1381 if (VA.needsCustom()) { 1382 if (VA.getLocVT() == MVT::v2f64) { 1383 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1384 DAG.getConstant(0, MVT::i32)); 1385 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1386 DAG.getConstant(1, MVT::i32)); 1387 1388 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1389 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1390 1391 VA = ArgLocs[++i]; // skip ahead to next loc 1392 if (VA.isRegLoc()) { 1393 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1394 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1395 } else { 1396 assert(VA.isMemLoc()); 1397 1398 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1399 dl, DAG, VA, Flags)); 1400 } 1401 } else { 1402 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1403 StackPtr, MemOpChains, Flags); 1404 } 1405 } else if (VA.isRegLoc()) { 1406 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1407 } else if (isByVal) { 1408 assert(VA.isMemLoc()); 1409 unsigned offset = 0; 1410 1411 // True if this byval aggregate will be split between registers 1412 // and memory. 1413 if (CCInfo.isFirstByValRegValid()) { 1414 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1415 unsigned int i, j; 1416 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) { 1417 SDValue Const = DAG.getConstant(4*i, MVT::i32); 1418 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1419 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 1420 MachinePointerInfo(), 1421 false, false, false, 0); 1422 MemOpChains.push_back(Load.getValue(1)); 1423 RegsToPass.push_back(std::make_pair(j, Load)); 1424 } 1425 offset = ARM::R4 - CCInfo.getFirstByValReg(); 1426 CCInfo.clearFirstByValReg(); 1427 } 1428 1429 if (Flags.getByValSize() - 4*offset > 0) { 1430 unsigned LocMemOffset = VA.getLocMemOffset(); 1431 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); 1432 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1433 StkPtrOff); 1434 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); 1435 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 1436 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, 1437 MVT::i32); 1438 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32); 1439 1440 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 1441 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode}; 1442 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs, 1443 Ops, array_lengthof(Ops))); 1444 } 1445 } else if (!IsSibCall) { 1446 assert(VA.isMemLoc()); 1447 1448 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1449 dl, DAG, VA, Flags)); 1450 } 1451 } 1452 1453 if (!MemOpChains.empty()) 1454 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1455 &MemOpChains[0], MemOpChains.size()); 1456 1457 // Build a sequence of copy-to-reg nodes chained together with token chain 1458 // and flag operands which copy the outgoing args into the appropriate regs. 1459 SDValue InFlag; 1460 // Tail call byval lowering might overwrite argument registers so in case of 1461 // tail call optimization the copies to registers are lowered later. 1462 if (!isTailCall) 1463 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1464 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1465 RegsToPass[i].second, InFlag); 1466 InFlag = Chain.getValue(1); 1467 } 1468 1469 // For tail calls lower the arguments to the 'real' stack slot. 1470 if (isTailCall) { 1471 // Force all the incoming stack arguments to be loaded from the stack 1472 // before any new outgoing arguments are stored to the stack, because the 1473 // outgoing stack slots may alias the incoming argument stack slots, and 1474 // the alias isn't otherwise explicit. This is slightly more conservative 1475 // than necessary, because it means that each store effectively depends 1476 // on every argument instead of just those arguments it would clobber. 1477 1478 // Do not flag preceding copytoreg stuff together with the following stuff. 1479 InFlag = SDValue(); 1480 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1481 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1482 RegsToPass[i].second, InFlag); 1483 InFlag = Chain.getValue(1); 1484 } 1485 InFlag =SDValue(); 1486 } 1487 1488 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1489 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1490 // node so that legalize doesn't hack it. 1491 bool isDirect = false; 1492 bool isARMFunc = false; 1493 bool isLocalARMFunc = false; 1494 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1495 1496 if (EnableARMLongCalls) { 1497 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1498 && "long-calls with non-static relocation model!"); 1499 // Handle a global address or an external symbol. If it's not one of 1500 // those, the target's already in a register, so we don't need to do 1501 // anything extra. 1502 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1503 const GlobalValue *GV = G->getGlobal(); 1504 // Create a constant pool entry for the callee address 1505 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1506 ARMConstantPoolValue *CPV = 1507 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0); 1508 1509 // Get the address of the callee into a register 1510 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1511 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1512 Callee = DAG.getLoad(getPointerTy(), dl, 1513 DAG.getEntryNode(), CPAddr, 1514 MachinePointerInfo::getConstantPool(), 1515 false, false, false, 0); 1516 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1517 const char *Sym = S->getSymbol(); 1518 1519 // Create a constant pool entry for the callee address 1520 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1521 ARMConstantPoolValue *CPV = 1522 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1523 ARMPCLabelIndex, 0); 1524 // Get the address of the callee into a register 1525 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1526 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1527 Callee = DAG.getLoad(getPointerTy(), dl, 1528 DAG.getEntryNode(), CPAddr, 1529 MachinePointerInfo::getConstantPool(), 1530 false, false, false, 0); 1531 } 1532 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1533 const GlobalValue *GV = G->getGlobal(); 1534 isDirect = true; 1535 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1536 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1537 getTargetMachine().getRelocationModel() != Reloc::Static; 1538 isARMFunc = !Subtarget->isThumb() || isStub; 1539 // ARM call to a local ARM function is predicable. 1540 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1541 // tBX takes a register source operand. 1542 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1543 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1544 ARMConstantPoolValue *CPV = 1545 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4); 1546 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1547 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1548 Callee = DAG.getLoad(getPointerTy(), dl, 1549 DAG.getEntryNode(), CPAddr, 1550 MachinePointerInfo::getConstantPool(), 1551 false, false, false, 0); 1552 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1553 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1554 getPointerTy(), Callee, PICLabel); 1555 } else { 1556 // On ELF targets for PIC code, direct calls should go through the PLT 1557 unsigned OpFlags = 0; 1558 if (Subtarget->isTargetELF() && 1559 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1560 OpFlags = ARMII::MO_PLT; 1561 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1562 } 1563 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1564 isDirect = true; 1565 bool isStub = Subtarget->isTargetDarwin() && 1566 getTargetMachine().getRelocationModel() != Reloc::Static; 1567 isARMFunc = !Subtarget->isThumb() || isStub; 1568 // tBX takes a register source operand. 1569 const char *Sym = S->getSymbol(); 1570 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1571 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1572 ARMConstantPoolValue *CPV = 1573 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1574 ARMPCLabelIndex, 4); 1575 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1576 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1577 Callee = DAG.getLoad(getPointerTy(), dl, 1578 DAG.getEntryNode(), CPAddr, 1579 MachinePointerInfo::getConstantPool(), 1580 false, false, false, 0); 1581 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1582 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1583 getPointerTy(), Callee, PICLabel); 1584 } else { 1585 unsigned OpFlags = 0; 1586 // On ELF targets for PIC code, direct calls should go through the PLT 1587 if (Subtarget->isTargetELF() && 1588 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1589 OpFlags = ARMII::MO_PLT; 1590 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1591 } 1592 } 1593 1594 // FIXME: handle tail calls differently. 1595 unsigned CallOpc; 1596 if (Subtarget->isThumb()) { 1597 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1598 CallOpc = ARMISD::CALL_NOLINK; 1599 else 1600 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1601 } else { 1602 if (!isDirect && !Subtarget->hasV5TOps()) 1603 CallOpc = ARMISD::CALL_NOLINK; 1604 else if (doesNotRet && isDirect && Subtarget->hasRAS()) 1605 // "mov lr, pc; b _foo" to avoid confusing the RSP 1606 CallOpc = ARMISD::CALL_NOLINK; 1607 else 1608 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL; 1609 } 1610 1611 std::vector<SDValue> Ops; 1612 Ops.push_back(Chain); 1613 Ops.push_back(Callee); 1614 1615 // Add argument registers to the end of the list so that they are known live 1616 // into the call. 1617 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1618 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1619 RegsToPass[i].second.getValueType())); 1620 1621 // Add a register mask operand representing the call-preserved registers. 1622 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 1623 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 1624 assert(Mask && "Missing call preserved mask for calling convention"); 1625 Ops.push_back(DAG.getRegisterMask(Mask)); 1626 1627 if (InFlag.getNode()) 1628 Ops.push_back(InFlag); 1629 1630 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1631 if (isTailCall) 1632 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1633 1634 // Returns a chain and a flag for retval copy to use. 1635 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1636 InFlag = Chain.getValue(1); 1637 1638 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1639 DAG.getIntPtrConstant(0, true), InFlag); 1640 if (!Ins.empty()) 1641 InFlag = Chain.getValue(1); 1642 1643 // Handle result values, copying them out of physregs into vregs that we 1644 // return. 1645 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1646 dl, DAG, InVals); 1647} 1648 1649/// HandleByVal - Every parameter *after* a byval parameter is passed 1650/// on the stack. Remember the next parameter register to allocate, 1651/// and then confiscate the rest of the parameter registers to insure 1652/// this. 1653void 1654ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const { 1655 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1656 assert((State->getCallOrPrologue() == Prologue || 1657 State->getCallOrPrologue() == Call) && 1658 "unhandled ParmContext"); 1659 if ((!State->isFirstByValRegValid()) && 1660 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 1661 State->setFirstByValReg(reg); 1662 // At a call site, a byval parameter that is split between 1663 // registers and memory needs its size truncated here. In a 1664 // function prologue, such byval parameters are reassembled in 1665 // memory, and are not truncated. 1666 if (State->getCallOrPrologue() == Call) { 1667 unsigned excess = 4 * (ARM::R4 - reg); 1668 assert(size >= excess && "expected larger existing stack allocation"); 1669 size -= excess; 1670 } 1671 } 1672 // Confiscate any remaining parameter registers to preclude their 1673 // assignment to subsequent parameters. 1674 while (State->AllocateReg(GPRArgRegs, 4)) 1675 ; 1676} 1677 1678/// MatchingStackOffset - Return true if the given stack call argument is 1679/// already available in the same position (relatively) of the caller's 1680/// incoming argument stack. 1681static 1682bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1683 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1684 const TargetInstrInfo *TII) { 1685 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1686 int FI = INT_MAX; 1687 if (Arg.getOpcode() == ISD::CopyFromReg) { 1688 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1689 if (!TargetRegisterInfo::isVirtualRegister(VR)) 1690 return false; 1691 MachineInstr *Def = MRI->getVRegDef(VR); 1692 if (!Def) 1693 return false; 1694 if (!Flags.isByVal()) { 1695 if (!TII->isLoadFromStackSlot(Def, FI)) 1696 return false; 1697 } else { 1698 return false; 1699 } 1700 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1701 if (Flags.isByVal()) 1702 // ByVal argument is passed in as a pointer but it's now being 1703 // dereferenced. e.g. 1704 // define @foo(%struct.X* %A) { 1705 // tail call @bar(%struct.X* byval %A) 1706 // } 1707 return false; 1708 SDValue Ptr = Ld->getBasePtr(); 1709 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1710 if (!FINode) 1711 return false; 1712 FI = FINode->getIndex(); 1713 } else 1714 return false; 1715 1716 assert(FI != INT_MAX); 1717 if (!MFI->isFixedObjectIndex(FI)) 1718 return false; 1719 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1720} 1721 1722/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1723/// for tail call optimization. Targets which want to do tail call 1724/// optimization should implement this function. 1725bool 1726ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1727 CallingConv::ID CalleeCC, 1728 bool isVarArg, 1729 bool isCalleeStructRet, 1730 bool isCallerStructRet, 1731 const SmallVectorImpl<ISD::OutputArg> &Outs, 1732 const SmallVectorImpl<SDValue> &OutVals, 1733 const SmallVectorImpl<ISD::InputArg> &Ins, 1734 SelectionDAG& DAG) const { 1735 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1736 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1737 bool CCMatch = CallerCC == CalleeCC; 1738 1739 // Look for obvious safe cases to perform tail call optimization that do not 1740 // require ABI changes. This is what gcc calls sibcall. 1741 1742 // Do not sibcall optimize vararg calls unless the call site is not passing 1743 // any arguments. 1744 if (isVarArg && !Outs.empty()) 1745 return false; 1746 1747 // Also avoid sibcall optimization if either caller or callee uses struct 1748 // return semantics. 1749 if (isCalleeStructRet || isCallerStructRet) 1750 return false; 1751 1752 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1753 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 1754 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 1755 // support in the assembler and linker to be used. This would need to be 1756 // fixed to fully support tail calls in Thumb1. 1757 // 1758 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1759 // LR. This means if we need to reload LR, it takes an extra instructions, 1760 // which outweighs the value of the tail call; but here we don't know yet 1761 // whether LR is going to be used. Probably the right approach is to 1762 // generate the tail call here and turn it back into CALL/RET in 1763 // emitEpilogue if LR is used. 1764 1765 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1766 // but we need to make sure there are enough registers; the only valid 1767 // registers are the 4 used for parameters. We don't currently do this 1768 // case. 1769 if (Subtarget->isThumb1Only()) 1770 return false; 1771 1772 // If the calling conventions do not match, then we'd better make sure the 1773 // results are returned in the same way as what the caller expects. 1774 if (!CCMatch) { 1775 SmallVector<CCValAssign, 16> RVLocs1; 1776 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1777 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); 1778 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1779 1780 SmallVector<CCValAssign, 16> RVLocs2; 1781 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1782 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); 1783 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1784 1785 if (RVLocs1.size() != RVLocs2.size()) 1786 return false; 1787 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1788 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1789 return false; 1790 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1791 return false; 1792 if (RVLocs1[i].isRegLoc()) { 1793 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1794 return false; 1795 } else { 1796 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1797 return false; 1798 } 1799 } 1800 } 1801 1802 // If Caller's vararg or byval argument has been split between registers and 1803 // stack, do not perform tail call, since part of the argument is in caller's 1804 // local frame. 1805 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction(). 1806 getInfo<ARMFunctionInfo>(); 1807 if (AFI_Caller->getVarArgsRegSaveSize()) 1808 return false; 1809 1810 // If the callee takes no arguments then go on to check the results of the 1811 // call. 1812 if (!Outs.empty()) { 1813 // Check if stack adjustment is needed. For now, do not do this if any 1814 // argument is passed on the stack. 1815 SmallVector<CCValAssign, 16> ArgLocs; 1816 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 1817 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1818 CCInfo.AnalyzeCallOperands(Outs, 1819 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1820 if (CCInfo.getNextStackOffset()) { 1821 MachineFunction &MF = DAG.getMachineFunction(); 1822 1823 // Check if the arguments are already laid out in the right way as 1824 // the caller's fixed stack objects. 1825 MachineFrameInfo *MFI = MF.getFrameInfo(); 1826 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1827 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1828 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1829 i != e; 1830 ++i, ++realArgIdx) { 1831 CCValAssign &VA = ArgLocs[i]; 1832 EVT RegVT = VA.getLocVT(); 1833 SDValue Arg = OutVals[realArgIdx]; 1834 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1835 if (VA.getLocInfo() == CCValAssign::Indirect) 1836 return false; 1837 if (VA.needsCustom()) { 1838 // f64 and vector types are split into multiple registers or 1839 // register/stack-slot combinations. The types will not match 1840 // the registers; give up on memory f64 refs until we figure 1841 // out what to do about this. 1842 if (!VA.isRegLoc()) 1843 return false; 1844 if (!ArgLocs[++i].isRegLoc()) 1845 return false; 1846 if (RegVT == MVT::v2f64) { 1847 if (!ArgLocs[++i].isRegLoc()) 1848 return false; 1849 if (!ArgLocs[++i].isRegLoc()) 1850 return false; 1851 } 1852 } else if (!VA.isRegLoc()) { 1853 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1854 MFI, MRI, TII)) 1855 return false; 1856 } 1857 } 1858 } 1859 } 1860 1861 return true; 1862} 1863 1864SDValue 1865ARMTargetLowering::LowerReturn(SDValue Chain, 1866 CallingConv::ID CallConv, bool isVarArg, 1867 const SmallVectorImpl<ISD::OutputArg> &Outs, 1868 const SmallVectorImpl<SDValue> &OutVals, 1869 DebugLoc dl, SelectionDAG &DAG) const { 1870 1871 // CCValAssign - represent the assignment of the return value to a location. 1872 SmallVector<CCValAssign, 16> RVLocs; 1873 1874 // CCState - Info about the registers and stack slots. 1875 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1876 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1877 1878 // Analyze outgoing return values. 1879 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1880 isVarArg)); 1881 1882 // If this is the first return lowered for this function, add 1883 // the regs to the liveout set for the function. 1884 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1885 for (unsigned i = 0; i != RVLocs.size(); ++i) 1886 if (RVLocs[i].isRegLoc()) 1887 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1888 } 1889 1890 SDValue Flag; 1891 1892 // Copy the result values into the output registers. 1893 for (unsigned i = 0, realRVLocIdx = 0; 1894 i != RVLocs.size(); 1895 ++i, ++realRVLocIdx) { 1896 CCValAssign &VA = RVLocs[i]; 1897 assert(VA.isRegLoc() && "Can only return in registers!"); 1898 1899 SDValue Arg = OutVals[realRVLocIdx]; 1900 1901 switch (VA.getLocInfo()) { 1902 default: llvm_unreachable("Unknown loc info!"); 1903 case CCValAssign::Full: break; 1904 case CCValAssign::BCvt: 1905 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1906 break; 1907 } 1908 1909 if (VA.needsCustom()) { 1910 if (VA.getLocVT() == MVT::v2f64) { 1911 // Extract the first half and return it in two registers. 1912 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1913 DAG.getConstant(0, MVT::i32)); 1914 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1915 DAG.getVTList(MVT::i32, MVT::i32), Half); 1916 1917 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1918 Flag = Chain.getValue(1); 1919 VA = RVLocs[++i]; // skip ahead to next loc 1920 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1921 HalfGPRs.getValue(1), Flag); 1922 Flag = Chain.getValue(1); 1923 VA = RVLocs[++i]; // skip ahead to next loc 1924 1925 // Extract the 2nd half and fall through to handle it as an f64 value. 1926 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1927 DAG.getConstant(1, MVT::i32)); 1928 } 1929 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1930 // available. 1931 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1932 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1933 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1934 Flag = Chain.getValue(1); 1935 VA = RVLocs[++i]; // skip ahead to next loc 1936 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1937 Flag); 1938 } else 1939 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1940 1941 // Guarantee that all emitted copies are 1942 // stuck together, avoiding something bad. 1943 Flag = Chain.getValue(1); 1944 } 1945 1946 SDValue result; 1947 if (Flag.getNode()) 1948 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1949 else // Return Void 1950 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1951 1952 return result; 1953} 1954 1955bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1956 if (N->getNumValues() != 1) 1957 return false; 1958 if (!N->hasNUsesOfValue(1, 0)) 1959 return false; 1960 1961 SDValue TCChain = Chain; 1962 SDNode *Copy = *N->use_begin(); 1963 if (Copy->getOpcode() == ISD::CopyToReg) { 1964 // If the copy has a glue operand, we conservatively assume it isn't safe to 1965 // perform a tail call. 1966 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1967 return false; 1968 TCChain = Copy->getOperand(0); 1969 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { 1970 SDNode *VMov = Copy; 1971 // f64 returned in a pair of GPRs. 1972 SmallPtrSet<SDNode*, 2> Copies; 1973 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end(); 1974 UI != UE; ++UI) { 1975 if (UI->getOpcode() != ISD::CopyToReg) 1976 return false; 1977 Copies.insert(*UI); 1978 } 1979 if (Copies.size() > 2) 1980 return false; 1981 1982 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end(); 1983 UI != UE; ++UI) { 1984 SDValue UseChain = UI->getOperand(0); 1985 if (Copies.count(UseChain.getNode())) 1986 // Second CopyToReg 1987 Copy = *UI; 1988 else 1989 // First CopyToReg 1990 TCChain = UseChain; 1991 } 1992 } else if (Copy->getOpcode() == ISD::BITCAST) { 1993 // f32 returned in a single GPR. 1994 if (!Copy->hasOneUse()) 1995 return false; 1996 Copy = *Copy->use_begin(); 1997 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0)) 1998 return false; 1999 Chain = Copy->getOperand(0); 2000 } else { 2001 return false; 2002 } 2003 2004 bool HasRet = false; 2005 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 2006 UI != UE; ++UI) { 2007 if (UI->getOpcode() != ARMISD::RET_FLAG) 2008 return false; 2009 HasRet = true; 2010 } 2011 2012 if (!HasRet) 2013 return false; 2014 2015 Chain = TCChain; 2016 return true; 2017} 2018 2019bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 2020 if (!EnableARMTailCalls && !Subtarget->supportsTailCall()) 2021 return false; 2022 2023 if (!CI->isTailCall()) 2024 return false; 2025 2026 return !Subtarget->isThumb1Only(); 2027} 2028 2029// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 2030// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 2031// one of the above mentioned nodes. It has to be wrapped because otherwise 2032// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 2033// be used to form addressing mode. These wrapped nodes will be selected 2034// into MOVi. 2035static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 2036 EVT PtrVT = Op.getValueType(); 2037 // FIXME there is no actual debug info here 2038 DebugLoc dl = Op.getDebugLoc(); 2039 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 2040 SDValue Res; 2041 if (CP->isMachineConstantPoolEntry()) 2042 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 2043 CP->getAlignment()); 2044 else 2045 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 2046 CP->getAlignment()); 2047 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 2048} 2049 2050unsigned ARMTargetLowering::getJumpTableEncoding() const { 2051 return MachineJumpTableInfo::EK_Inline; 2052} 2053 2054SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 2055 SelectionDAG &DAG) const { 2056 MachineFunction &MF = DAG.getMachineFunction(); 2057 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2058 unsigned ARMPCLabelIndex = 0; 2059 DebugLoc DL = Op.getDebugLoc(); 2060 EVT PtrVT = getPointerTy(); 2061 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 2062 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2063 SDValue CPAddr; 2064 if (RelocM == Reloc::Static) { 2065 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 2066 } else { 2067 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2068 ARMPCLabelIndex = AFI->createPICLabelUId(); 2069 ARMConstantPoolValue *CPV = 2070 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex, 2071 ARMCP::CPBlockAddress, PCAdj); 2072 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2073 } 2074 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 2075 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 2076 MachinePointerInfo::getConstantPool(), 2077 false, false, false, 0); 2078 if (RelocM == Reloc::Static) 2079 return Result; 2080 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2081 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 2082} 2083 2084// Lower ISD::GlobalTLSAddress using the "general dynamic" model 2085SDValue 2086ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 2087 SelectionDAG &DAG) const { 2088 DebugLoc dl = GA->getDebugLoc(); 2089 EVT PtrVT = getPointerTy(); 2090 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2091 MachineFunction &MF = DAG.getMachineFunction(); 2092 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2093 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2094 ARMConstantPoolValue *CPV = 2095 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2096 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); 2097 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2098 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 2099 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 2100 MachinePointerInfo::getConstantPool(), 2101 false, false, false, 0); 2102 SDValue Chain = Argument.getValue(1); 2103 2104 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2105 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 2106 2107 // call __tls_get_addr. 2108 ArgListTy Args; 2109 ArgListEntry Entry; 2110 Entry.Node = Argument; 2111 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 2112 Args.push_back(Entry); 2113 // FIXME: is there useful debug info available here? 2114 TargetLowering::CallLoweringInfo CLI(Chain, 2115 (Type *) Type::getInt32Ty(*DAG.getContext()), 2116 false, false, false, false, 2117 0, CallingConv::C, /*isTailCall=*/false, 2118 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 2119 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 2120 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2121 return CallResult.first; 2122} 2123 2124// Lower ISD::GlobalTLSAddress using the "initial exec" or 2125// "local exec" model. 2126SDValue 2127ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 2128 SelectionDAG &DAG, 2129 TLSModel::Model model) const { 2130 const GlobalValue *GV = GA->getGlobal(); 2131 DebugLoc dl = GA->getDebugLoc(); 2132 SDValue Offset; 2133 SDValue Chain = DAG.getEntryNode(); 2134 EVT PtrVT = getPointerTy(); 2135 // Get the Thread Pointer 2136 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2137 2138 if (model == TLSModel::InitialExec) { 2139 MachineFunction &MF = DAG.getMachineFunction(); 2140 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2141 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2142 // Initial exec model. 2143 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2144 ARMConstantPoolValue *CPV = 2145 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2146 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, 2147 true); 2148 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2149 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2150 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2151 MachinePointerInfo::getConstantPool(), 2152 false, false, false, 0); 2153 Chain = Offset.getValue(1); 2154 2155 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2156 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 2157 2158 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2159 MachinePointerInfo::getConstantPool(), 2160 false, false, false, 0); 2161 } else { 2162 // local exec model 2163 assert(model == TLSModel::LocalExec); 2164 ARMConstantPoolValue *CPV = 2165 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF); 2166 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2167 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2168 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2169 MachinePointerInfo::getConstantPool(), 2170 false, false, false, 0); 2171 } 2172 2173 // The address of the thread local variable is the add of the thread 2174 // pointer with the offset of the variable. 2175 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2176} 2177 2178SDValue 2179ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 2180 // TODO: implement the "local dynamic" model 2181 assert(Subtarget->isTargetELF() && 2182 "TLS not implemented for non-ELF targets"); 2183 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2184 2185 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal()); 2186 2187 switch (model) { 2188 case TLSModel::GeneralDynamic: 2189 case TLSModel::LocalDynamic: 2190 return LowerToTLSGeneralDynamicModel(GA, DAG); 2191 case TLSModel::InitialExec: 2192 case TLSModel::LocalExec: 2193 return LowerToTLSExecModels(GA, DAG, model); 2194 } 2195 llvm_unreachable("bogus TLS model"); 2196} 2197 2198SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 2199 SelectionDAG &DAG) const { 2200 EVT PtrVT = getPointerTy(); 2201 DebugLoc dl = Op.getDebugLoc(); 2202 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2203 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2204 if (RelocM == Reloc::PIC_) { 2205 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2206 ARMConstantPoolValue *CPV = 2207 ARMConstantPoolConstant::Create(GV, 2208 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2209 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2210 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2211 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 2212 CPAddr, 2213 MachinePointerInfo::getConstantPool(), 2214 false, false, false, 0); 2215 SDValue Chain = Result.getValue(1); 2216 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 2217 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2218 if (!UseGOTOFF) 2219 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 2220 MachinePointerInfo::getGOT(), 2221 false, false, false, 0); 2222 return Result; 2223 } 2224 2225 // If we have T2 ops, we can materialize the address directly via movt/movw 2226 // pair. This is always cheaper. 2227 if (Subtarget->useMovt()) { 2228 ++NumMovwMovt; 2229 // FIXME: Once remat is capable of dealing with instructions with register 2230 // operands, expand this into two nodes. 2231 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2232 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2233 } else { 2234 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2235 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2236 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2237 MachinePointerInfo::getConstantPool(), 2238 false, false, false, 0); 2239 } 2240} 2241 2242SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 2243 SelectionDAG &DAG) const { 2244 EVT PtrVT = getPointerTy(); 2245 DebugLoc dl = Op.getDebugLoc(); 2246 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2247 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2248 MachineFunction &MF = DAG.getMachineFunction(); 2249 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2250 2251 // FIXME: Enable this for static codegen when tool issues are fixed. Also 2252 // update ARMFastISel::ARMMaterializeGV. 2253 if (Subtarget->useMovt() && RelocM != Reloc::Static) { 2254 ++NumMovwMovt; 2255 // FIXME: Once remat is capable of dealing with instructions with register 2256 // operands, expand this into two nodes. 2257 if (RelocM == Reloc::Static) 2258 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2259 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2260 2261 unsigned Wrapper = (RelocM == Reloc::PIC_) 2262 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN; 2263 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, 2264 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2265 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2266 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, 2267 MachinePointerInfo::getGOT(), 2268 false, false, false, 0); 2269 return Result; 2270 } 2271 2272 unsigned ARMPCLabelIndex = 0; 2273 SDValue CPAddr; 2274 if (RelocM == Reloc::Static) { 2275 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2276 } else { 2277 ARMPCLabelIndex = AFI->createPICLabelUId(); 2278 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 2279 ARMConstantPoolValue *CPV = 2280 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 2281 PCAdj); 2282 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2283 } 2284 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2285 2286 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2287 MachinePointerInfo::getConstantPool(), 2288 false, false, false, 0); 2289 SDValue Chain = Result.getValue(1); 2290 2291 if (RelocM == Reloc::PIC_) { 2292 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2293 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2294 } 2295 2296 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2297 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 2298 false, false, false, 0); 2299 2300 return Result; 2301} 2302 2303SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 2304 SelectionDAG &DAG) const { 2305 assert(Subtarget->isTargetELF() && 2306 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 2307 MachineFunction &MF = DAG.getMachineFunction(); 2308 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2309 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2310 EVT PtrVT = getPointerTy(); 2311 DebugLoc dl = Op.getDebugLoc(); 2312 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2313 ARMConstantPoolValue *CPV = 2314 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_", 2315 ARMPCLabelIndex, PCAdj); 2316 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2317 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2318 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2319 MachinePointerInfo::getConstantPool(), 2320 false, false, false, 0); 2321 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2322 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2323} 2324 2325SDValue 2326ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 2327 DebugLoc dl = Op.getDebugLoc(); 2328 SDValue Val = DAG.getConstant(0, MVT::i32); 2329 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, 2330 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), 2331 Op.getOperand(1), Val); 2332} 2333 2334SDValue 2335ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 2336 DebugLoc dl = Op.getDebugLoc(); 2337 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 2338 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 2339} 2340 2341SDValue 2342ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 2343 const ARMSubtarget *Subtarget) const { 2344 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2345 DebugLoc dl = Op.getDebugLoc(); 2346 switch (IntNo) { 2347 default: return SDValue(); // Don't custom lower most intrinsics. 2348 case Intrinsic::arm_thread_pointer: { 2349 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2350 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2351 } 2352 case Intrinsic::eh_sjlj_lsda: { 2353 MachineFunction &MF = DAG.getMachineFunction(); 2354 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2355 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2356 EVT PtrVT = getPointerTy(); 2357 DebugLoc dl = Op.getDebugLoc(); 2358 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2359 SDValue CPAddr; 2360 unsigned PCAdj = (RelocM != Reloc::PIC_) 2361 ? 0 : (Subtarget->isThumb() ? 4 : 8); 2362 ARMConstantPoolValue *CPV = 2363 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex, 2364 ARMCP::CPLSDA, PCAdj); 2365 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2366 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2367 SDValue Result = 2368 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2369 MachinePointerInfo::getConstantPool(), 2370 false, false, false, 0); 2371 2372 if (RelocM == Reloc::PIC_) { 2373 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2374 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2375 } 2376 return Result; 2377 } 2378 case Intrinsic::arm_neon_vmulls: 2379 case Intrinsic::arm_neon_vmullu: { 2380 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) 2381 ? ARMISD::VMULLs : ARMISD::VMULLu; 2382 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 2383 Op.getOperand(1), Op.getOperand(2)); 2384 } 2385 } 2386} 2387 2388static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2389 const ARMSubtarget *Subtarget) { 2390 DebugLoc dl = Op.getDebugLoc(); 2391 if (!Subtarget->hasDataBarrier()) { 2392 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2393 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2394 // here. 2395 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2396 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2397 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2398 DAG.getConstant(0, MVT::i32)); 2399 } 2400 2401 SDValue Op5 = Op.getOperand(5); 2402 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; 2403 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 2404 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 2405 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0); 2406 2407 ARM_MB::MemBOpt DMBOpt; 2408 if (isDeviceBarrier) 2409 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY; 2410 else 2411 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH; 2412 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2413 DAG.getConstant(DMBOpt, MVT::i32)); 2414} 2415 2416 2417static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, 2418 const ARMSubtarget *Subtarget) { 2419 // FIXME: handle "fence singlethread" more efficiently. 2420 DebugLoc dl = Op.getDebugLoc(); 2421 if (!Subtarget->hasDataBarrier()) { 2422 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2423 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2424 // here. 2425 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2426 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2427 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2428 DAG.getConstant(0, MVT::i32)); 2429 } 2430 2431 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2432 DAG.getConstant(ARM_MB::ISH, MVT::i32)); 2433} 2434 2435static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, 2436 const ARMSubtarget *Subtarget) { 2437 // ARM pre v5TE and Thumb1 does not have preload instructions. 2438 if (!(Subtarget->isThumb2() || 2439 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) 2440 // Just preserve the chain. 2441 return Op.getOperand(0); 2442 2443 DebugLoc dl = Op.getDebugLoc(); 2444 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; 2445 if (!isRead && 2446 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) 2447 // ARMv7 with MP extension has PLDW. 2448 return Op.getOperand(0); 2449 2450 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 2451 if (Subtarget->isThumb()) { 2452 // Invert the bits. 2453 isRead = ~isRead & 1; 2454 isData = ~isData & 1; 2455 } 2456 2457 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), 2458 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), 2459 DAG.getConstant(isData, MVT::i32)); 2460} 2461 2462static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2463 MachineFunction &MF = DAG.getMachineFunction(); 2464 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2465 2466 // vastart just stores the address of the VarArgsFrameIndex slot into the 2467 // memory location argument. 2468 DebugLoc dl = Op.getDebugLoc(); 2469 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2470 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2471 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2472 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2473 MachinePointerInfo(SV), false, false, 0); 2474} 2475 2476SDValue 2477ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2478 SDValue &Root, SelectionDAG &DAG, 2479 DebugLoc dl) const { 2480 MachineFunction &MF = DAG.getMachineFunction(); 2481 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2482 2483 const TargetRegisterClass *RC; 2484 if (AFI->isThumb1OnlyFunction()) 2485 RC = &ARM::tGPRRegClass; 2486 else 2487 RC = &ARM::GPRRegClass; 2488 2489 // Transform the arguments stored in physical registers into virtual ones. 2490 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2491 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2492 2493 SDValue ArgValue2; 2494 if (NextVA.isMemLoc()) { 2495 MachineFrameInfo *MFI = MF.getFrameInfo(); 2496 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2497 2498 // Create load node to retrieve arguments from the stack. 2499 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2500 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2501 MachinePointerInfo::getFixedStack(FI), 2502 false, false, false, 0); 2503 } else { 2504 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2505 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2506 } 2507 2508 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2509} 2510 2511void 2512ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, 2513 unsigned &VARegSize, unsigned &VARegSaveSize) 2514 const { 2515 unsigned NumGPRs; 2516 if (CCInfo.isFirstByValRegValid()) 2517 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg(); 2518 else { 2519 unsigned int firstUnalloced; 2520 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2521 sizeof(GPRArgRegs) / 2522 sizeof(GPRArgRegs[0])); 2523 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0; 2524 } 2525 2526 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 2527 VARegSize = NumGPRs * 4; 2528 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2529} 2530 2531// The remaining GPRs hold either the beginning of variable-argument 2532// data, or the beginning of an aggregate passed by value (usuall 2533// byval). Either way, we allocate stack slots adjacent to the data 2534// provided by our caller, and store the unallocated registers there. 2535// If this is a variadic function, the va_list pointer will begin with 2536// these values; otherwise, this reassembles a (byval) structure that 2537// was split between registers and memory. 2538void 2539ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 2540 DebugLoc dl, SDValue &Chain, 2541 const Value *OrigArg, 2542 unsigned OffsetFromOrigArg, 2543 unsigned ArgOffset, 2544 bool ForceMutable) const { 2545 MachineFunction &MF = DAG.getMachineFunction(); 2546 MachineFrameInfo *MFI = MF.getFrameInfo(); 2547 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2548 unsigned firstRegToSaveIndex; 2549 if (CCInfo.isFirstByValRegValid()) 2550 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 2551 else { 2552 firstRegToSaveIndex = CCInfo.getFirstUnallocated 2553 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2554 } 2555 2556 unsigned VARegSize, VARegSaveSize; 2557 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2558 if (VARegSaveSize) { 2559 // If this function is vararg, store any remaining integer argument regs 2560 // to their spots on the stack so that they may be loaded by deferencing 2561 // the result of va_next. 2562 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2563 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize, 2564 ArgOffset + VARegSaveSize 2565 - VARegSize, 2566 false)); 2567 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2568 getPointerTy()); 2569 2570 SmallVector<SDValue, 4> MemOps; 2571 for (unsigned i = 0; firstRegToSaveIndex < 4; ++firstRegToSaveIndex, ++i) { 2572 const TargetRegisterClass *RC; 2573 if (AFI->isThumb1OnlyFunction()) 2574 RC = &ARM::tGPRRegClass; 2575 else 2576 RC = &ARM::GPRRegClass; 2577 2578 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 2579 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2580 SDValue Store = 2581 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2582 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i), 2583 false, false, 0); 2584 MemOps.push_back(Store); 2585 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2586 DAG.getConstant(4, getPointerTy())); 2587 } 2588 if (!MemOps.empty()) 2589 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2590 &MemOps[0], MemOps.size()); 2591 } else 2592 // This will point to the next argument passed via stack. 2593 AFI->setVarArgsFrameIndex( 2594 MFI->CreateFixedObject(4, ArgOffset, !ForceMutable)); 2595} 2596 2597SDValue 2598ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2599 CallingConv::ID CallConv, bool isVarArg, 2600 const SmallVectorImpl<ISD::InputArg> 2601 &Ins, 2602 DebugLoc dl, SelectionDAG &DAG, 2603 SmallVectorImpl<SDValue> &InVals) 2604 const { 2605 MachineFunction &MF = DAG.getMachineFunction(); 2606 MachineFrameInfo *MFI = MF.getFrameInfo(); 2607 2608 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2609 2610 // Assign locations to all of the incoming arguments. 2611 SmallVector<CCValAssign, 16> ArgLocs; 2612 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2613 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); 2614 CCInfo.AnalyzeFormalArguments(Ins, 2615 CCAssignFnForNode(CallConv, /* Return*/ false, 2616 isVarArg)); 2617 2618 SmallVector<SDValue, 16> ArgValues; 2619 int lastInsIndex = -1; 2620 SDValue ArgValue; 2621 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin(); 2622 unsigned CurArgIdx = 0; 2623 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2624 CCValAssign &VA = ArgLocs[i]; 2625 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx); 2626 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex; 2627 // Arguments stored in registers. 2628 if (VA.isRegLoc()) { 2629 EVT RegVT = VA.getLocVT(); 2630 2631 if (VA.needsCustom()) { 2632 // f64 and vector types are split up into multiple registers or 2633 // combinations of registers and stack slots. 2634 if (VA.getLocVT() == MVT::v2f64) { 2635 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2636 Chain, DAG, dl); 2637 VA = ArgLocs[++i]; // skip ahead to next loc 2638 SDValue ArgValue2; 2639 if (VA.isMemLoc()) { 2640 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2641 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2642 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2643 MachinePointerInfo::getFixedStack(FI), 2644 false, false, false, 0); 2645 } else { 2646 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2647 Chain, DAG, dl); 2648 } 2649 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2650 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2651 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2652 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2653 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2654 } else 2655 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2656 2657 } else { 2658 const TargetRegisterClass *RC; 2659 2660 if (RegVT == MVT::f32) 2661 RC = &ARM::SPRRegClass; 2662 else if (RegVT == MVT::f64) 2663 RC = &ARM::DPRRegClass; 2664 else if (RegVT == MVT::v2f64) 2665 RC = &ARM::QPRRegClass; 2666 else if (RegVT == MVT::i32) 2667 RC = AFI->isThumb1OnlyFunction() ? 2668 (const TargetRegisterClass*)&ARM::tGPRRegClass : 2669 (const TargetRegisterClass*)&ARM::GPRRegClass; 2670 else 2671 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2672 2673 // Transform the arguments in physical registers into virtual ones. 2674 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2675 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2676 } 2677 2678 // If this is an 8 or 16-bit value, it is really passed promoted 2679 // to 32 bits. Insert an assert[sz]ext to capture this, then 2680 // truncate to the right size. 2681 switch (VA.getLocInfo()) { 2682 default: llvm_unreachable("Unknown loc info!"); 2683 case CCValAssign::Full: break; 2684 case CCValAssign::BCvt: 2685 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2686 break; 2687 case CCValAssign::SExt: 2688 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2689 DAG.getValueType(VA.getValVT())); 2690 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2691 break; 2692 case CCValAssign::ZExt: 2693 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2694 DAG.getValueType(VA.getValVT())); 2695 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2696 break; 2697 } 2698 2699 InVals.push_back(ArgValue); 2700 2701 } else { // VA.isRegLoc() 2702 2703 // sanity check 2704 assert(VA.isMemLoc()); 2705 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2706 2707 int index = ArgLocs[i].getValNo(); 2708 2709 // Some Ins[] entries become multiple ArgLoc[] entries. 2710 // Process them only once. 2711 if (index != lastInsIndex) 2712 { 2713 ISD::ArgFlagsTy Flags = Ins[index].Flags; 2714 // FIXME: For now, all byval parameter objects are marked mutable. 2715 // This can be changed with more analysis. 2716 // In case of tail call optimization mark all arguments mutable. 2717 // Since they could be overwritten by lowering of arguments in case of 2718 // a tail call. 2719 if (Flags.isByVal()) { 2720 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2721 if (!AFI->getVarArgsFrameIndex()) { 2722 VarArgStyleRegisters(CCInfo, DAG, 2723 dl, Chain, CurOrigArg, 2724 Ins[VA.getValNo()].PartOffset, 2725 VA.getLocMemOffset(), 2726 true /*force mutable frames*/); 2727 int VAFrameIndex = AFI->getVarArgsFrameIndex(); 2728 InVals.push_back(DAG.getFrameIndex(VAFrameIndex, getPointerTy())); 2729 } else { 2730 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 2731 VA.getLocMemOffset(), false); 2732 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); 2733 } 2734 } else { 2735 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 2736 VA.getLocMemOffset(), true); 2737 2738 // Create load nodes to retrieve arguments from the stack. 2739 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2740 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2741 MachinePointerInfo::getFixedStack(FI), 2742 false, false, false, 0)); 2743 } 2744 lastInsIndex = index; 2745 } 2746 } 2747 } 2748 2749 // varargs 2750 if (isVarArg) 2751 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0, 0, 2752 CCInfo.getNextStackOffset()); 2753 2754 return Chain; 2755} 2756 2757/// isFloatingPointZero - Return true if this is +0.0. 2758static bool isFloatingPointZero(SDValue Op) { 2759 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2760 return CFP->getValueAPF().isPosZero(); 2761 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2762 // Maybe this has already been legalized into the constant pool? 2763 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2764 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2765 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2766 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2767 return CFP->getValueAPF().isPosZero(); 2768 } 2769 } 2770 return false; 2771} 2772 2773/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2774/// the given operands. 2775SDValue 2776ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2777 SDValue &ARMcc, SelectionDAG &DAG, 2778 DebugLoc dl) const { 2779 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2780 unsigned C = RHSC->getZExtValue(); 2781 if (!isLegalICmpImmediate(C)) { 2782 // Constant does not fit, try adjusting it by one? 2783 switch (CC) { 2784 default: break; 2785 case ISD::SETLT: 2786 case ISD::SETGE: 2787 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2788 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2789 RHS = DAG.getConstant(C-1, MVT::i32); 2790 } 2791 break; 2792 case ISD::SETULT: 2793 case ISD::SETUGE: 2794 if (C != 0 && isLegalICmpImmediate(C-1)) { 2795 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2796 RHS = DAG.getConstant(C-1, MVT::i32); 2797 } 2798 break; 2799 case ISD::SETLE: 2800 case ISD::SETGT: 2801 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2802 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2803 RHS = DAG.getConstant(C+1, MVT::i32); 2804 } 2805 break; 2806 case ISD::SETULE: 2807 case ISD::SETUGT: 2808 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2809 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2810 RHS = DAG.getConstant(C+1, MVT::i32); 2811 } 2812 break; 2813 } 2814 } 2815 } 2816 2817 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2818 ARMISD::NodeType CompareType; 2819 switch (CondCode) { 2820 default: 2821 CompareType = ARMISD::CMP; 2822 break; 2823 case ARMCC::EQ: 2824 case ARMCC::NE: 2825 // Uses only Z Flag 2826 CompareType = ARMISD::CMPZ; 2827 break; 2828 } 2829 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2830 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); 2831} 2832 2833/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2834SDValue 2835ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2836 DebugLoc dl) const { 2837 SDValue Cmp; 2838 if (!isFloatingPointZero(RHS)) 2839 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); 2840 else 2841 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); 2842 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); 2843} 2844 2845/// duplicateCmp - Glue values can have only one use, so this function 2846/// duplicates a comparison node. 2847SDValue 2848ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { 2849 unsigned Opc = Cmp.getOpcode(); 2850 DebugLoc DL = Cmp.getDebugLoc(); 2851 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) 2852 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2853 2854 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); 2855 Cmp = Cmp.getOperand(0); 2856 Opc = Cmp.getOpcode(); 2857 if (Opc == ARMISD::CMPFP) 2858 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2859 else { 2860 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"); 2861 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); 2862 } 2863 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); 2864} 2865 2866SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2867 SDValue Cond = Op.getOperand(0); 2868 SDValue SelectTrue = Op.getOperand(1); 2869 SDValue SelectFalse = Op.getOperand(2); 2870 DebugLoc dl = Op.getDebugLoc(); 2871 2872 // Convert: 2873 // 2874 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2875 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2876 // 2877 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2878 const ConstantSDNode *CMOVTrue = 2879 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2880 const ConstantSDNode *CMOVFalse = 2881 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2882 2883 if (CMOVTrue && CMOVFalse) { 2884 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2885 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2886 2887 SDValue True; 2888 SDValue False; 2889 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2890 True = SelectTrue; 2891 False = SelectFalse; 2892 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2893 True = SelectFalse; 2894 False = SelectTrue; 2895 } 2896 2897 if (True.getNode() && False.getNode()) { 2898 EVT VT = Op.getValueType(); 2899 SDValue ARMcc = Cond.getOperand(2); 2900 SDValue CCR = Cond.getOperand(3); 2901 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); 2902 assert(True.getValueType() == VT); 2903 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2904 } 2905 } 2906 } 2907 2908 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the 2909 // undefined bits before doing a full-word comparison with zero. 2910 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond, 2911 DAG.getConstant(1, Cond.getValueType())); 2912 2913 return DAG.getSelectCC(dl, Cond, 2914 DAG.getConstant(0, Cond.getValueType()), 2915 SelectTrue, SelectFalse, ISD::SETNE); 2916} 2917 2918SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2919 EVT VT = Op.getValueType(); 2920 SDValue LHS = Op.getOperand(0); 2921 SDValue RHS = Op.getOperand(1); 2922 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2923 SDValue TrueVal = Op.getOperand(2); 2924 SDValue FalseVal = Op.getOperand(3); 2925 DebugLoc dl = Op.getDebugLoc(); 2926 2927 if (LHS.getValueType() == MVT::i32) { 2928 SDValue ARMcc; 2929 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2930 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2931 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2932 } 2933 2934 ARMCC::CondCodes CondCode, CondCode2; 2935 FPCCToARMCC(CC, CondCode, CondCode2); 2936 2937 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2938 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2939 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2940 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2941 ARMcc, CCR, Cmp); 2942 if (CondCode2 != ARMCC::AL) { 2943 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2944 // FIXME: Needs another CMP because flag can have but one use. 2945 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2946 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2947 Result, TrueVal, ARMcc2, CCR, Cmp2); 2948 } 2949 return Result; 2950} 2951 2952/// canChangeToInt - Given the fp compare operand, return true if it is suitable 2953/// to morph to an integer compare sequence. 2954static bool canChangeToInt(SDValue Op, bool &SeenZero, 2955 const ARMSubtarget *Subtarget) { 2956 SDNode *N = Op.getNode(); 2957 if (!N->hasOneUse()) 2958 // Otherwise it requires moving the value from fp to integer registers. 2959 return false; 2960 if (!N->getNumValues()) 2961 return false; 2962 EVT VT = Op.getValueType(); 2963 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2964 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2965 // vmrs are very slow, e.g. cortex-a8. 2966 return false; 2967 2968 if (isFloatingPointZero(Op)) { 2969 SeenZero = true; 2970 return true; 2971 } 2972 return ISD::isNormalLoad(N); 2973} 2974 2975static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2976 if (isFloatingPointZero(Op)) 2977 return DAG.getConstant(0, MVT::i32); 2978 2979 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2980 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2981 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2982 Ld->isVolatile(), Ld->isNonTemporal(), 2983 Ld->isInvariant(), Ld->getAlignment()); 2984 2985 llvm_unreachable("Unknown VFP cmp argument!"); 2986} 2987 2988static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2989 SDValue &RetVal1, SDValue &RetVal2) { 2990 if (isFloatingPointZero(Op)) { 2991 RetVal1 = DAG.getConstant(0, MVT::i32); 2992 RetVal2 = DAG.getConstant(0, MVT::i32); 2993 return; 2994 } 2995 2996 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2997 SDValue Ptr = Ld->getBasePtr(); 2998 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2999 Ld->getChain(), Ptr, 3000 Ld->getPointerInfo(), 3001 Ld->isVolatile(), Ld->isNonTemporal(), 3002 Ld->isInvariant(), Ld->getAlignment()); 3003 3004 EVT PtrType = Ptr.getValueType(); 3005 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 3006 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 3007 PtrType, Ptr, DAG.getConstant(4, PtrType)); 3008 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 3009 Ld->getChain(), NewPtr, 3010 Ld->getPointerInfo().getWithOffset(4), 3011 Ld->isVolatile(), Ld->isNonTemporal(), 3012 Ld->isInvariant(), NewAlign); 3013 return; 3014 } 3015 3016 llvm_unreachable("Unknown VFP cmp argument!"); 3017} 3018 3019/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 3020/// f32 and even f64 comparisons to integer ones. 3021SDValue 3022ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 3023 SDValue Chain = Op.getOperand(0); 3024 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 3025 SDValue LHS = Op.getOperand(2); 3026 SDValue RHS = Op.getOperand(3); 3027 SDValue Dest = Op.getOperand(4); 3028 DebugLoc dl = Op.getDebugLoc(); 3029 3030 bool LHSSeenZero = false; 3031 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget); 3032 bool RHSSeenZero = false; 3033 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget); 3034 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) { 3035 // If unsafe fp math optimization is enabled and there are no other uses of 3036 // the CMP operands, and the condition code is EQ or NE, we can optimize it 3037 // to an integer comparison. 3038 if (CC == ISD::SETOEQ) 3039 CC = ISD::SETEQ; 3040 else if (CC == ISD::SETUNE) 3041 CC = ISD::SETNE; 3042 3043 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32); 3044 SDValue ARMcc; 3045 if (LHS.getValueType() == MVT::f32) { 3046 LHS = DAG.getNode(ISD::AND, dl, MVT::i32, 3047 bitcastf32Toi32(LHS, DAG), Mask); 3048 RHS = DAG.getNode(ISD::AND, dl, MVT::i32, 3049 bitcastf32Toi32(RHS, DAG), Mask); 3050 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 3051 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3052 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 3053 Chain, Dest, ARMcc, CCR, Cmp); 3054 } 3055 3056 SDValue LHS1, LHS2; 3057 SDValue RHS1, RHS2; 3058 expandf64Toi32(LHS, DAG, LHS1, LHS2); 3059 expandf64Toi32(RHS, DAG, RHS1, RHS2); 3060 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask); 3061 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask); 3062 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 3063 ARMcc = DAG.getConstant(CondCode, MVT::i32); 3064 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 3065 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 3066 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 3067 } 3068 3069 return SDValue(); 3070} 3071 3072SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 3073 SDValue Chain = Op.getOperand(0); 3074 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 3075 SDValue LHS = Op.getOperand(2); 3076 SDValue RHS = Op.getOperand(3); 3077 SDValue Dest = Op.getOperand(4); 3078 DebugLoc dl = Op.getDebugLoc(); 3079 3080 if (LHS.getValueType() == MVT::i32) { 3081 SDValue ARMcc; 3082 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 3083 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3084 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 3085 Chain, Dest, ARMcc, CCR, Cmp); 3086 } 3087 3088 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 3089 3090 if (getTargetMachine().Options.UnsafeFPMath && 3091 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 3092 CC == ISD::SETNE || CC == ISD::SETUNE)) { 3093 SDValue Result = OptimizeVFPBrcond(Op, DAG); 3094 if (Result.getNode()) 3095 return Result; 3096 } 3097 3098 ARMCC::CondCodes CondCode, CondCode2; 3099 FPCCToARMCC(CC, CondCode, CondCode2); 3100 3101 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 3102 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 3103 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3104 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 3105 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 3106 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 3107 if (CondCode2 != ARMCC::AL) { 3108 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 3109 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 3110 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 3111 } 3112 return Res; 3113} 3114 3115SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 3116 SDValue Chain = Op.getOperand(0); 3117 SDValue Table = Op.getOperand(1); 3118 SDValue Index = Op.getOperand(2); 3119 DebugLoc dl = Op.getDebugLoc(); 3120 3121 EVT PTy = getPointerTy(); 3122 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 3123 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 3124 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 3125 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 3126 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 3127 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 3128 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3129 if (Subtarget->isThumb2()) { 3130 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 3131 // which does another jump to the destination. This also makes it easier 3132 // to translate it to TBB / TBH later. 3133 // FIXME: This might not work if the function is extremely large. 3134 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 3135 Addr, Op.getOperand(2), JTI, UId); 3136 } 3137 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 3138 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 3139 MachinePointerInfo::getJumpTable(), 3140 false, false, false, 0); 3141 Chain = Addr.getValue(1); 3142 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 3143 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3144 } else { 3145 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 3146 MachinePointerInfo::getJumpTable(), 3147 false, false, false, 0); 3148 Chain = Addr.getValue(1); 3149 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3150 } 3151} 3152 3153static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 3154 EVT VT = Op.getValueType(); 3155 DebugLoc dl = Op.getDebugLoc(); 3156 3157 if (Op.getValueType().getVectorElementType() == MVT::i32) { 3158 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32) 3159 return Op; 3160 return DAG.UnrollVectorOp(Op.getNode()); 3161 } 3162 3163 assert(Op.getOperand(0).getValueType() == MVT::v4f32 && 3164 "Invalid type for custom lowering!"); 3165 if (VT != MVT::v4i16) 3166 return DAG.UnrollVectorOp(Op.getNode()); 3167 3168 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0)); 3169 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op); 3170} 3171 3172static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 3173 EVT VT = Op.getValueType(); 3174 if (VT.isVector()) 3175 return LowerVectorFP_TO_INT(Op, DAG); 3176 3177 DebugLoc dl = Op.getDebugLoc(); 3178 unsigned Opc; 3179 3180 switch (Op.getOpcode()) { 3181 default: llvm_unreachable("Invalid opcode!"); 3182 case ISD::FP_TO_SINT: 3183 Opc = ARMISD::FTOSI; 3184 break; 3185 case ISD::FP_TO_UINT: 3186 Opc = ARMISD::FTOUI; 3187 break; 3188 } 3189 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 3190 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3191} 3192 3193static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3194 EVT VT = Op.getValueType(); 3195 DebugLoc dl = Op.getDebugLoc(); 3196 3197 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) { 3198 if (VT.getVectorElementType() == MVT::f32) 3199 return Op; 3200 return DAG.UnrollVectorOp(Op.getNode()); 3201 } 3202 3203 assert(Op.getOperand(0).getValueType() == MVT::v4i16 && 3204 "Invalid type for custom lowering!"); 3205 if (VT != MVT::v4f32) 3206 return DAG.UnrollVectorOp(Op.getNode()); 3207 3208 unsigned CastOpc; 3209 unsigned Opc; 3210 switch (Op.getOpcode()) { 3211 default: llvm_unreachable("Invalid opcode!"); 3212 case ISD::SINT_TO_FP: 3213 CastOpc = ISD::SIGN_EXTEND; 3214 Opc = ISD::SINT_TO_FP; 3215 break; 3216 case ISD::UINT_TO_FP: 3217 CastOpc = ISD::ZERO_EXTEND; 3218 Opc = ISD::UINT_TO_FP; 3219 break; 3220 } 3221 3222 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); 3223 return DAG.getNode(Opc, dl, VT, Op); 3224} 3225 3226static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3227 EVT VT = Op.getValueType(); 3228 if (VT.isVector()) 3229 return LowerVectorINT_TO_FP(Op, DAG); 3230 3231 DebugLoc dl = Op.getDebugLoc(); 3232 unsigned Opc; 3233 3234 switch (Op.getOpcode()) { 3235 default: llvm_unreachable("Invalid opcode!"); 3236 case ISD::SINT_TO_FP: 3237 Opc = ARMISD::SITOF; 3238 break; 3239 case ISD::UINT_TO_FP: 3240 Opc = ARMISD::UITOF; 3241 break; 3242 } 3243 3244 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 3245 return DAG.getNode(Opc, dl, VT, Op); 3246} 3247 3248SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 3249 // Implement fcopysign with a fabs and a conditional fneg. 3250 SDValue Tmp0 = Op.getOperand(0); 3251 SDValue Tmp1 = Op.getOperand(1); 3252 DebugLoc dl = Op.getDebugLoc(); 3253 EVT VT = Op.getValueType(); 3254 EVT SrcVT = Tmp1.getValueType(); 3255 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || 3256 Tmp0.getOpcode() == ARMISD::VMOVDRR; 3257 bool UseNEON = !InGPR && Subtarget->hasNEON(); 3258 3259 if (UseNEON) { 3260 // Use VBSL to copy the sign bit. 3261 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); 3262 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, 3263 DAG.getTargetConstant(EncodedVal, MVT::i32)); 3264 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 3265 if (VT == MVT::f64) 3266 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3267 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), 3268 DAG.getConstant(32, MVT::i32)); 3269 else /*if (VT == MVT::f32)*/ 3270 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); 3271 if (SrcVT == MVT::f32) { 3272 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); 3273 if (VT == MVT::f64) 3274 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3275 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), 3276 DAG.getConstant(32, MVT::i32)); 3277 } else if (VT == MVT::f32) 3278 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, 3279 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 3280 DAG.getConstant(32, MVT::i32)); 3281 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); 3282 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); 3283 3284 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), 3285 MVT::i32); 3286 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); 3287 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, 3288 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); 3289 3290 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, 3291 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), 3292 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); 3293 if (VT == MVT::f32) { 3294 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); 3295 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, 3296 DAG.getConstant(0, MVT::i32)); 3297 } else { 3298 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); 3299 } 3300 3301 return Res; 3302 } 3303 3304 // Bitcast operand 1 to i32. 3305 if (SrcVT == MVT::f64) 3306 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3307 &Tmp1, 1).getValue(1); 3308 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); 3309 3310 // Or in the signbit with integer operations. 3311 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32); 3312 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); 3313 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); 3314 if (VT == MVT::f32) { 3315 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, 3316 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); 3317 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3318 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); 3319 } 3320 3321 // f64: Or the high part with signbit and then combine two parts. 3322 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3323 &Tmp0, 1); 3324 SDValue Lo = Tmp0.getValue(0); 3325 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); 3326 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); 3327 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 3328} 3329 3330SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 3331 MachineFunction &MF = DAG.getMachineFunction(); 3332 MachineFrameInfo *MFI = MF.getFrameInfo(); 3333 MFI->setReturnAddressIsTaken(true); 3334 3335 EVT VT = Op.getValueType(); 3336 DebugLoc dl = Op.getDebugLoc(); 3337 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3338 if (Depth) { 3339 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3340 SDValue Offset = DAG.getConstant(4, MVT::i32); 3341 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 3342 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 3343 MachinePointerInfo(), false, false, false, 0); 3344 } 3345 3346 // Return LR, which contains the return address. Mark it an implicit live-in. 3347 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); 3348 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 3349} 3350 3351SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 3352 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3353 MFI->setFrameAddressIsTaken(true); 3354 3355 EVT VT = Op.getValueType(); 3356 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 3357 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3358 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 3359 ? ARM::R7 : ARM::R11; 3360 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 3361 while (Depth--) 3362 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 3363 MachinePointerInfo(), 3364 false, false, false, 0); 3365 return FrameAddr; 3366} 3367 3368/// ExpandBITCAST - If the target supports VFP, this function is called to 3369/// expand a bit convert where either the source or destination type is i64 to 3370/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 3371/// operand type is illegal (e.g., v2f32 for a target that doesn't support 3372/// vectors), since the legalizer won't know what to do with that. 3373static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { 3374 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3375 DebugLoc dl = N->getDebugLoc(); 3376 SDValue Op = N->getOperand(0); 3377 3378 // This function is only supposed to be called for i64 types, either as the 3379 // source or destination of the bit convert. 3380 EVT SrcVT = Op.getValueType(); 3381 EVT DstVT = N->getValueType(0); 3382 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3383 "ExpandBITCAST called for non-i64 type"); 3384 3385 // Turn i64->f64 into VMOVDRR. 3386 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3387 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3388 DAG.getConstant(0, MVT::i32)); 3389 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3390 DAG.getConstant(1, MVT::i32)); 3391 return DAG.getNode(ISD::BITCAST, dl, DstVT, 3392 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 3393 } 3394 3395 // Turn f64->i64 into VMOVRRD. 3396 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 3397 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 3398 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 3399 // Merge the pieces into a single i64 value. 3400 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 3401 } 3402 3403 return SDValue(); 3404} 3405 3406/// getZeroVector - Returns a vector of specified type with all zero elements. 3407/// Zero vectors are used to represent vector negation and in those cases 3408/// will be implemented with the NEON VNEG instruction. However, VNEG does 3409/// not support i64 elements, so sometimes the zero vectors will need to be 3410/// explicitly constructed. Regardless, use a canonical VMOV to create the 3411/// zero vector. 3412static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3413 assert(VT.isVector() && "Expected a vector type"); 3414 // The canonical modified immediate encoding of a zero vector is....0! 3415 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); 3416 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 3417 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); 3418 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3419} 3420 3421/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3422/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3423SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 3424 SelectionDAG &DAG) const { 3425 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3426 EVT VT = Op.getValueType(); 3427 unsigned VTBits = VT.getSizeInBits(); 3428 DebugLoc dl = Op.getDebugLoc(); 3429 SDValue ShOpLo = Op.getOperand(0); 3430 SDValue ShOpHi = Op.getOperand(1); 3431 SDValue ShAmt = Op.getOperand(2); 3432 SDValue ARMcc; 3433 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3434 3435 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3436 3437 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3438 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3439 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3440 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3441 DAG.getConstant(VTBits, MVT::i32)); 3442 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3443 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3444 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3445 3446 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3447 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3448 ARMcc, DAG, dl); 3449 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3450 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, 3451 CCR, Cmp); 3452 3453 SDValue Ops[2] = { Lo, Hi }; 3454 return DAG.getMergeValues(Ops, 2, dl); 3455} 3456 3457/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3458/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3459SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 3460 SelectionDAG &DAG) const { 3461 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3462 EVT VT = Op.getValueType(); 3463 unsigned VTBits = VT.getSizeInBits(); 3464 DebugLoc dl = Op.getDebugLoc(); 3465 SDValue ShOpLo = Op.getOperand(0); 3466 SDValue ShOpHi = Op.getOperand(1); 3467 SDValue ShAmt = Op.getOperand(2); 3468 SDValue ARMcc; 3469 3470 assert(Op.getOpcode() == ISD::SHL_PARTS); 3471 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3472 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3473 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3474 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3475 DAG.getConstant(VTBits, MVT::i32)); 3476 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3477 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3478 3479 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3480 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3481 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3482 ARMcc, DAG, dl); 3483 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3484 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, 3485 CCR, Cmp); 3486 3487 SDValue Ops[2] = { Lo, Hi }; 3488 return DAG.getMergeValues(Ops, 2, dl); 3489} 3490 3491SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3492 SelectionDAG &DAG) const { 3493 // The rounding mode is in bits 23:22 of the FPSCR. 3494 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 3495 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) 3496 // so that the shift + and get folded into a bitfield extract. 3497 DebugLoc dl = Op.getDebugLoc(); 3498 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 3499 DAG.getConstant(Intrinsic::arm_get_fpscr, 3500 MVT::i32)); 3501 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, 3502 DAG.getConstant(1U << 22, MVT::i32)); 3503 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, 3504 DAG.getConstant(22, MVT::i32)); 3505 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, 3506 DAG.getConstant(3, MVT::i32)); 3507} 3508 3509static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 3510 const ARMSubtarget *ST) { 3511 EVT VT = N->getValueType(0); 3512 DebugLoc dl = N->getDebugLoc(); 3513 3514 if (!ST->hasV6T2Ops()) 3515 return SDValue(); 3516 3517 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 3518 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 3519} 3520 3521static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 3522 const ARMSubtarget *ST) { 3523 EVT VT = N->getValueType(0); 3524 DebugLoc dl = N->getDebugLoc(); 3525 3526 if (!VT.isVector()) 3527 return SDValue(); 3528 3529 // Lower vector shifts on NEON to use VSHL. 3530 assert(ST->hasNEON() && "unexpected vector shift"); 3531 3532 // Left shifts translate directly to the vshiftu intrinsic. 3533 if (N->getOpcode() == ISD::SHL) 3534 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3535 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 3536 N->getOperand(0), N->getOperand(1)); 3537 3538 assert((N->getOpcode() == ISD::SRA || 3539 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 3540 3541 // NEON uses the same intrinsics for both left and right shifts. For 3542 // right shifts, the shift amounts are negative, so negate the vector of 3543 // shift amounts. 3544 EVT ShiftVT = N->getOperand(1).getValueType(); 3545 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 3546 getZeroVector(ShiftVT, DAG, dl), 3547 N->getOperand(1)); 3548 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 3549 Intrinsic::arm_neon_vshifts : 3550 Intrinsic::arm_neon_vshiftu); 3551 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3552 DAG.getConstant(vshiftInt, MVT::i32), 3553 N->getOperand(0), NegatedCount); 3554} 3555 3556static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, 3557 const ARMSubtarget *ST) { 3558 EVT VT = N->getValueType(0); 3559 DebugLoc dl = N->getDebugLoc(); 3560 3561 // We can get here for a node like i32 = ISD::SHL i32, i64 3562 if (VT != MVT::i64) 3563 return SDValue(); 3564 3565 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 3566 "Unknown shift to lower!"); 3567 3568 // We only lower SRA, SRL of 1 here, all others use generic lowering. 3569 if (!isa<ConstantSDNode>(N->getOperand(1)) || 3570 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 3571 return SDValue(); 3572 3573 // If we are in thumb mode, we don't have RRX. 3574 if (ST->isThumb1Only()) return SDValue(); 3575 3576 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 3577 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3578 DAG.getConstant(0, MVT::i32)); 3579 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3580 DAG.getConstant(1, MVT::i32)); 3581 3582 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 3583 // captures the result into a carry flag. 3584 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 3585 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1); 3586 3587 // The low part is an ARMISD::RRX operand, which shifts the carry in. 3588 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 3589 3590 // Merge the pieces into a single i64 value. 3591 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 3592} 3593 3594static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 3595 SDValue TmpOp0, TmpOp1; 3596 bool Invert = false; 3597 bool Swap = false; 3598 unsigned Opc = 0; 3599 3600 SDValue Op0 = Op.getOperand(0); 3601 SDValue Op1 = Op.getOperand(1); 3602 SDValue CC = Op.getOperand(2); 3603 EVT VT = Op.getValueType(); 3604 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3605 DebugLoc dl = Op.getDebugLoc(); 3606 3607 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 3608 switch (SetCCOpcode) { 3609 default: llvm_unreachable("Illegal FP comparison"); 3610 case ISD::SETUNE: 3611 case ISD::SETNE: Invert = true; // Fallthrough 3612 case ISD::SETOEQ: 3613 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3614 case ISD::SETOLT: 3615 case ISD::SETLT: Swap = true; // Fallthrough 3616 case ISD::SETOGT: 3617 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3618 case ISD::SETOLE: 3619 case ISD::SETLE: Swap = true; // Fallthrough 3620 case ISD::SETOGE: 3621 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3622 case ISD::SETUGE: Swap = true; // Fallthrough 3623 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 3624 case ISD::SETUGT: Swap = true; // Fallthrough 3625 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 3626 case ISD::SETUEQ: Invert = true; // Fallthrough 3627 case ISD::SETONE: 3628 // Expand this to (OLT | OGT). 3629 TmpOp0 = Op0; 3630 TmpOp1 = Op1; 3631 Opc = ISD::OR; 3632 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3633 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 3634 break; 3635 case ISD::SETUO: Invert = true; // Fallthrough 3636 case ISD::SETO: 3637 // Expand this to (OLT | OGE). 3638 TmpOp0 = Op0; 3639 TmpOp1 = Op1; 3640 Opc = ISD::OR; 3641 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3642 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 3643 break; 3644 } 3645 } else { 3646 // Integer comparisons. 3647 switch (SetCCOpcode) { 3648 default: llvm_unreachable("Illegal integer comparison"); 3649 case ISD::SETNE: Invert = true; 3650 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3651 case ISD::SETLT: Swap = true; 3652 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3653 case ISD::SETLE: Swap = true; 3654 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3655 case ISD::SETULT: Swap = true; 3656 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 3657 case ISD::SETULE: Swap = true; 3658 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 3659 } 3660 3661 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 3662 if (Opc == ARMISD::VCEQ) { 3663 3664 SDValue AndOp; 3665 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3666 AndOp = Op0; 3667 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 3668 AndOp = Op1; 3669 3670 // Ignore bitconvert. 3671 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) 3672 AndOp = AndOp.getOperand(0); 3673 3674 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 3675 Opc = ARMISD::VTST; 3676 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0)); 3677 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1)); 3678 Invert = !Invert; 3679 } 3680 } 3681 } 3682 3683 if (Swap) 3684 std::swap(Op0, Op1); 3685 3686 // If one of the operands is a constant vector zero, attempt to fold the 3687 // comparison to a specialized compare-against-zero form. 3688 SDValue SingleOp; 3689 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3690 SingleOp = Op0; 3691 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { 3692 if (Opc == ARMISD::VCGE) 3693 Opc = ARMISD::VCLEZ; 3694 else if (Opc == ARMISD::VCGT) 3695 Opc = ARMISD::VCLTZ; 3696 SingleOp = Op1; 3697 } 3698 3699 SDValue Result; 3700 if (SingleOp.getNode()) { 3701 switch (Opc) { 3702 case ARMISD::VCEQ: 3703 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; 3704 case ARMISD::VCGE: 3705 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; 3706 case ARMISD::VCLEZ: 3707 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; 3708 case ARMISD::VCGT: 3709 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; 3710 case ARMISD::VCLTZ: 3711 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; 3712 default: 3713 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3714 } 3715 } else { 3716 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3717 } 3718 3719 if (Invert) 3720 Result = DAG.getNOT(dl, Result, VT); 3721 3722 return Result; 3723} 3724 3725/// isNEONModifiedImm - Check if the specified splat value corresponds to a 3726/// valid vector constant for a NEON instruction with a "modified immediate" 3727/// operand (e.g., VMOV). If so, return the encoded value. 3728static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 3729 unsigned SplatBitSize, SelectionDAG &DAG, 3730 EVT &VT, bool is128Bits, NEONModImmType type) { 3731 unsigned OpCmode, Imm; 3732 3733 // SplatBitSize is set to the smallest size that splats the vector, so a 3734 // zero vector will always have SplatBitSize == 8. However, NEON modified 3735 // immediate instructions others than VMOV do not support the 8-bit encoding 3736 // of a zero vector, and the default encoding of zero is supposed to be the 3737 // 32-bit version. 3738 if (SplatBits == 0) 3739 SplatBitSize = 32; 3740 3741 switch (SplatBitSize) { 3742 case 8: 3743 if (type != VMOVModImm) 3744 return SDValue(); 3745 // Any 1-byte value is OK. Op=0, Cmode=1110. 3746 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 3747 OpCmode = 0xe; 3748 Imm = SplatBits; 3749 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3750 break; 3751 3752 case 16: 3753 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 3754 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 3755 if ((SplatBits & ~0xff) == 0) { 3756 // Value = 0x00nn: Op=x, Cmode=100x. 3757 OpCmode = 0x8; 3758 Imm = SplatBits; 3759 break; 3760 } 3761 if ((SplatBits & ~0xff00) == 0) { 3762 // Value = 0xnn00: Op=x, Cmode=101x. 3763 OpCmode = 0xa; 3764 Imm = SplatBits >> 8; 3765 break; 3766 } 3767 return SDValue(); 3768 3769 case 32: 3770 // NEON's 32-bit VMOV supports splat values where: 3771 // * only one byte is nonzero, or 3772 // * the least significant byte is 0xff and the second byte is nonzero, or 3773 // * the least significant 2 bytes are 0xff and the third is nonzero. 3774 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 3775 if ((SplatBits & ~0xff) == 0) { 3776 // Value = 0x000000nn: Op=x, Cmode=000x. 3777 OpCmode = 0; 3778 Imm = SplatBits; 3779 break; 3780 } 3781 if ((SplatBits & ~0xff00) == 0) { 3782 // Value = 0x0000nn00: Op=x, Cmode=001x. 3783 OpCmode = 0x2; 3784 Imm = SplatBits >> 8; 3785 break; 3786 } 3787 if ((SplatBits & ~0xff0000) == 0) { 3788 // Value = 0x00nn0000: Op=x, Cmode=010x. 3789 OpCmode = 0x4; 3790 Imm = SplatBits >> 16; 3791 break; 3792 } 3793 if ((SplatBits & ~0xff000000) == 0) { 3794 // Value = 0xnn000000: Op=x, Cmode=011x. 3795 OpCmode = 0x6; 3796 Imm = SplatBits >> 24; 3797 break; 3798 } 3799 3800 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC 3801 if (type == OtherModImm) return SDValue(); 3802 3803 if ((SplatBits & ~0xffff) == 0 && 3804 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 3805 // Value = 0x0000nnff: Op=x, Cmode=1100. 3806 OpCmode = 0xc; 3807 Imm = SplatBits >> 8; 3808 SplatBits |= 0xff; 3809 break; 3810 } 3811 3812 if ((SplatBits & ~0xffffff) == 0 && 3813 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3814 // Value = 0x00nnffff: Op=x, Cmode=1101. 3815 OpCmode = 0xd; 3816 Imm = SplatBits >> 16; 3817 SplatBits |= 0xffff; 3818 break; 3819 } 3820 3821 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 3822 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 3823 // VMOV.I32. A (very) minor optimization would be to replicate the value 3824 // and fall through here to test for a valid 64-bit splat. But, then the 3825 // caller would also need to check and handle the change in size. 3826 return SDValue(); 3827 3828 case 64: { 3829 if (type != VMOVModImm) 3830 return SDValue(); 3831 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 3832 uint64_t BitMask = 0xff; 3833 uint64_t Val = 0; 3834 unsigned ImmMask = 1; 3835 Imm = 0; 3836 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3837 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3838 Val |= BitMask; 3839 Imm |= ImmMask; 3840 } else if ((SplatBits & BitMask) != 0) { 3841 return SDValue(); 3842 } 3843 BitMask <<= 8; 3844 ImmMask <<= 1; 3845 } 3846 // Op=1, Cmode=1110. 3847 OpCmode = 0x1e; 3848 SplatBits = Val; 3849 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3850 break; 3851 } 3852 3853 default: 3854 llvm_unreachable("unexpected size for isNEONModifiedImm"); 3855 } 3856 3857 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 3858 return DAG.getTargetConstant(EncodedVal, MVT::i32); 3859} 3860 3861SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG, 3862 const ARMSubtarget *ST) const { 3863 if (!ST->useNEONForSinglePrecisionFP() || !ST->hasVFP3() || ST->hasD16()) 3864 return SDValue(); 3865 3866 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op); 3867 assert(Op.getValueType() == MVT::f32 && 3868 "ConstantFP custom lowering should only occur for f32."); 3869 3870 // Try splatting with a VMOV.f32... 3871 APFloat FPVal = CFP->getValueAPF(); 3872 int ImmVal = ARM_AM::getFP32Imm(FPVal); 3873 if (ImmVal != -1) { 3874 DebugLoc DL = Op.getDebugLoc(); 3875 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32); 3876 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32, 3877 NewVal); 3878 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant, 3879 DAG.getConstant(0, MVT::i32)); 3880 } 3881 3882 // If that fails, try a VMOV.i32 3883 EVT VMovVT; 3884 unsigned iVal = FPVal.bitcastToAPInt().getZExtValue(); 3885 SDValue NewVal = isNEONModifiedImm(iVal, 0, 32, DAG, VMovVT, false, 3886 VMOVModImm); 3887 if (NewVal != SDValue()) { 3888 DebugLoc DL = Op.getDebugLoc(); 3889 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT, 3890 NewVal); 3891 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, 3892 VecConstant); 3893 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, 3894 DAG.getConstant(0, MVT::i32)); 3895 } 3896 3897 // Finally, try a VMVN.i32 3898 NewVal = isNEONModifiedImm(~iVal & 0xffffffff, 0, 32, DAG, VMovVT, false, 3899 VMVNModImm); 3900 if (NewVal != SDValue()) { 3901 DebugLoc DL = Op.getDebugLoc(); 3902 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal); 3903 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, 3904 VecConstant); 3905 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, 3906 DAG.getConstant(0, MVT::i32)); 3907 } 3908 3909 return SDValue(); 3910} 3911 3912 3913static bool isVEXTMask(ArrayRef<int> M, EVT VT, 3914 bool &ReverseVEXT, unsigned &Imm) { 3915 unsigned NumElts = VT.getVectorNumElements(); 3916 ReverseVEXT = false; 3917 3918 // Assume that the first shuffle index is not UNDEF. Fail if it is. 3919 if (M[0] < 0) 3920 return false; 3921 3922 Imm = M[0]; 3923 3924 // If this is a VEXT shuffle, the immediate value is the index of the first 3925 // element. The other shuffle indices must be the successive elements after 3926 // the first one. 3927 unsigned ExpectedElt = Imm; 3928 for (unsigned i = 1; i < NumElts; ++i) { 3929 // Increment the expected index. If it wraps around, it may still be 3930 // a VEXT but the source vectors must be swapped. 3931 ExpectedElt += 1; 3932 if (ExpectedElt == NumElts * 2) { 3933 ExpectedElt = 0; 3934 ReverseVEXT = true; 3935 } 3936 3937 if (M[i] < 0) continue; // ignore UNDEF indices 3938 if (ExpectedElt != static_cast<unsigned>(M[i])) 3939 return false; 3940 } 3941 3942 // Adjust the index value if the source operands will be swapped. 3943 if (ReverseVEXT) 3944 Imm -= NumElts; 3945 3946 return true; 3947} 3948 3949/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3950/// instruction with the specified blocksize. (The order of the elements 3951/// within each block of the vector is reversed.) 3952static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) { 3953 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3954 "Only possible block sizes for VREV are: 16, 32, 64"); 3955 3956 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3957 if (EltSz == 64) 3958 return false; 3959 3960 unsigned NumElts = VT.getVectorNumElements(); 3961 unsigned BlockElts = M[0] + 1; 3962 // If the first shuffle index is UNDEF, be optimistic. 3963 if (M[0] < 0) 3964 BlockElts = BlockSize / EltSz; 3965 3966 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3967 return false; 3968 3969 for (unsigned i = 0; i < NumElts; ++i) { 3970 if (M[i] < 0) continue; // ignore UNDEF indices 3971 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3972 return false; 3973 } 3974 3975 return true; 3976} 3977 3978static bool isVTBLMask(ArrayRef<int> M, EVT VT) { 3979 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of 3980 // range, then 0 is placed into the resulting vector. So pretty much any mask 3981 // of 8 elements can work here. 3982 return VT == MVT::v8i8 && M.size() == 8; 3983} 3984 3985static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 3986 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3987 if (EltSz == 64) 3988 return false; 3989 3990 unsigned NumElts = VT.getVectorNumElements(); 3991 WhichResult = (M[0] == 0 ? 0 : 1); 3992 for (unsigned i = 0; i < NumElts; i += 2) { 3993 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3994 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult)) 3995 return false; 3996 } 3997 return true; 3998} 3999 4000/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 4001/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4002/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 4003static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ 4004 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 4005 if (EltSz == 64) 4006 return false; 4007 4008 unsigned NumElts = VT.getVectorNumElements(); 4009 WhichResult = (M[0] == 0 ? 0 : 1); 4010 for (unsigned i = 0; i < NumElts; i += 2) { 4011 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 4012 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult)) 4013 return false; 4014 } 4015 return true; 4016} 4017 4018static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4019 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 4020 if (EltSz == 64) 4021 return false; 4022 4023 unsigned NumElts = VT.getVectorNumElements(); 4024 WhichResult = (M[0] == 0 ? 0 : 1); 4025 for (unsigned i = 0; i != NumElts; ++i) { 4026 if (M[i] < 0) continue; // ignore UNDEF indices 4027 if ((unsigned) M[i] != 2 * i + WhichResult) 4028 return false; 4029 } 4030 4031 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 4032 if (VT.is64BitVector() && EltSz == 32) 4033 return false; 4034 4035 return true; 4036} 4037 4038/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 4039/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4040/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 4041static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ 4042 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 4043 if (EltSz == 64) 4044 return false; 4045 4046 unsigned Half = VT.getVectorNumElements() / 2; 4047 WhichResult = (M[0] == 0 ? 0 : 1); 4048 for (unsigned j = 0; j != 2; ++j) { 4049 unsigned Idx = WhichResult; 4050 for (unsigned i = 0; i != Half; ++i) { 4051 int MIdx = M[i + j * Half]; 4052 if (MIdx >= 0 && (unsigned) MIdx != Idx) 4053 return false; 4054 Idx += 2; 4055 } 4056 } 4057 4058 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 4059 if (VT.is64BitVector() && EltSz == 32) 4060 return false; 4061 4062 return true; 4063} 4064 4065static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4066 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 4067 if (EltSz == 64) 4068 return false; 4069 4070 unsigned NumElts = VT.getVectorNumElements(); 4071 WhichResult = (M[0] == 0 ? 0 : 1); 4072 unsigned Idx = WhichResult * NumElts / 2; 4073 for (unsigned i = 0; i != NumElts; i += 2) { 4074 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 4075 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts)) 4076 return false; 4077 Idx += 1; 4078 } 4079 4080 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 4081 if (VT.is64BitVector() && EltSz == 32) 4082 return false; 4083 4084 return true; 4085} 4086 4087/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 4088/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4089/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 4090static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ 4091 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 4092 if (EltSz == 64) 4093 return false; 4094 4095 unsigned NumElts = VT.getVectorNumElements(); 4096 WhichResult = (M[0] == 0 ? 0 : 1); 4097 unsigned Idx = WhichResult * NumElts / 2; 4098 for (unsigned i = 0; i != NumElts; i += 2) { 4099 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 4100 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx)) 4101 return false; 4102 Idx += 1; 4103 } 4104 4105 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 4106 if (VT.is64BitVector() && EltSz == 32) 4107 return false; 4108 4109 return true; 4110} 4111 4112// If N is an integer constant that can be moved into a register in one 4113// instruction, return an SDValue of such a constant (will become a MOV 4114// instruction). Otherwise return null. 4115static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, 4116 const ARMSubtarget *ST, DebugLoc dl) { 4117 uint64_t Val; 4118 if (!isa<ConstantSDNode>(N)) 4119 return SDValue(); 4120 Val = cast<ConstantSDNode>(N)->getZExtValue(); 4121 4122 if (ST->isThumb1Only()) { 4123 if (Val <= 255 || ~Val <= 255) 4124 return DAG.getConstant(Val, MVT::i32); 4125 } else { 4126 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 4127 return DAG.getConstant(Val, MVT::i32); 4128 } 4129 return SDValue(); 4130} 4131 4132// If this is a case we can't handle, return null and let the default 4133// expansion code take care of it. 4134SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 4135 const ARMSubtarget *ST) const { 4136 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 4137 DebugLoc dl = Op.getDebugLoc(); 4138 EVT VT = Op.getValueType(); 4139 4140 APInt SplatBits, SplatUndef; 4141 unsigned SplatBitSize; 4142 bool HasAnyUndefs; 4143 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 4144 if (SplatBitSize <= 64) { 4145 // Check if an immediate VMOV works. 4146 EVT VmovVT; 4147 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 4148 SplatUndef.getZExtValue(), SplatBitSize, 4149 DAG, VmovVT, VT.is128BitVector(), 4150 VMOVModImm); 4151 if (Val.getNode()) { 4152 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); 4153 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 4154 } 4155 4156 // Try an immediate VMVN. 4157 uint64_t NegatedImm = (~SplatBits).getZExtValue(); 4158 Val = isNEONModifiedImm(NegatedImm, 4159 SplatUndef.getZExtValue(), SplatBitSize, 4160 DAG, VmovVT, VT.is128BitVector(), 4161 VMVNModImm); 4162 if (Val.getNode()) { 4163 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); 4164 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 4165 } 4166 4167 // Use vmov.f32 to materialize other v2f32 and v4f32 splats. 4168 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) { 4169 int ImmVal = ARM_AM::getFP32Imm(SplatBits); 4170 if (ImmVal != -1) { 4171 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32); 4172 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val); 4173 } 4174 } 4175 } 4176 } 4177 4178 // Scan through the operands to see if only one value is used. 4179 // 4180 // As an optimisation, even if more than one value is used it may be more 4181 // profitable to splat with one value then change some lanes. 4182 // 4183 // Heuristically we decide to do this if the vector has a "dominant" value, 4184 // defined as splatted to more than half of the lanes. 4185 unsigned NumElts = VT.getVectorNumElements(); 4186 bool isOnlyLowElement = true; 4187 bool usesOnlyOneValue = true; 4188 bool hasDominantValue = false; 4189 bool isConstant = true; 4190 4191 // Map of the number of times a particular SDValue appears in the 4192 // element list. 4193 DenseMap<SDValue, unsigned> ValueCounts; 4194 SDValue Value; 4195 for (unsigned i = 0; i < NumElts; ++i) { 4196 SDValue V = Op.getOperand(i); 4197 if (V.getOpcode() == ISD::UNDEF) 4198 continue; 4199 if (i > 0) 4200 isOnlyLowElement = false; 4201 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 4202 isConstant = false; 4203 4204 ValueCounts.insert(std::make_pair(V, 0)); 4205 unsigned &Count = ValueCounts[V]; 4206 4207 // Is this value dominant? (takes up more than half of the lanes) 4208 if (++Count > (NumElts / 2)) { 4209 hasDominantValue = true; 4210 Value = V; 4211 } 4212 } 4213 if (ValueCounts.size() != 1) 4214 usesOnlyOneValue = false; 4215 if (!Value.getNode() && ValueCounts.size() > 0) 4216 Value = ValueCounts.begin()->first; 4217 4218 if (ValueCounts.size() == 0) 4219 return DAG.getUNDEF(VT); 4220 4221 if (isOnlyLowElement) 4222 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 4223 4224 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4225 4226 // Use VDUP for non-constant splats. For f32 constant splats, reduce to 4227 // i32 and try again. 4228 if (hasDominantValue && EltSize <= 32) { 4229 if (!isConstant) { 4230 SDValue N; 4231 4232 // If we are VDUPing a value that comes directly from a vector, that will 4233 // cause an unnecessary move to and from a GPR, where instead we could 4234 // just use VDUPLANE. 4235 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 4236 // We need to create a new undef vector to use for the VDUPLANE if the 4237 // size of the vector from which we get the value is different than the 4238 // size of the vector that we need to create. We will insert the element 4239 // such that the register coalescer will remove unnecessary copies. 4240 if (VT != Value->getOperand(0).getValueType()) { 4241 ConstantSDNode *constIndex; 4242 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1)); 4243 assert(constIndex && "The index is not a constant!"); 4244 unsigned index = constIndex->getAPIntValue().getLimitedValue() % 4245 VT.getVectorNumElements(); 4246 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4247 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT), 4248 Value, DAG.getConstant(index, MVT::i32)), 4249 DAG.getConstant(index, MVT::i32)); 4250 } else { 4251 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4252 Value->getOperand(0), Value->getOperand(1)); 4253 } 4254 } 4255 else 4256 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value); 4257 4258 if (!usesOnlyOneValue) { 4259 // The dominant value was splatted as 'N', but we now have to insert 4260 // all differing elements. 4261 for (unsigned I = 0; I < NumElts; ++I) { 4262 if (Op.getOperand(I) == Value) 4263 continue; 4264 SmallVector<SDValue, 3> Ops; 4265 Ops.push_back(N); 4266 Ops.push_back(Op.getOperand(I)); 4267 Ops.push_back(DAG.getConstant(I, MVT::i32)); 4268 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, &Ops[0], 3); 4269 } 4270 } 4271 return N; 4272 } 4273 if (VT.getVectorElementType().isFloatingPoint()) { 4274 SmallVector<SDValue, 8> Ops; 4275 for (unsigned i = 0; i < NumElts; ++i) 4276 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, 4277 Op.getOperand(i))); 4278 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); 4279 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); 4280 Val = LowerBUILD_VECTOR(Val, DAG, ST); 4281 if (Val.getNode()) 4282 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4283 } 4284 if (usesOnlyOneValue) { 4285 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); 4286 if (isConstant && Val.getNode()) 4287 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); 4288 } 4289 } 4290 4291 // If all elements are constants and the case above didn't get hit, fall back 4292 // to the default expansion, which will generate a load from the constant 4293 // pool. 4294 if (isConstant) 4295 return SDValue(); 4296 4297 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 4298 if (NumElts >= 4) { 4299 SDValue shuffle = ReconstructShuffle(Op, DAG); 4300 if (shuffle != SDValue()) 4301 return shuffle; 4302 } 4303 4304 // Vectors with 32- or 64-bit elements can be built by directly assigning 4305 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 4306 // will be legalized. 4307 if (EltSize >= 32) { 4308 // Do the expansion with floating-point types, since that is what the VFP 4309 // registers are defined to use, and since i64 is not legal. 4310 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4311 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4312 SmallVector<SDValue, 8> Ops; 4313 for (unsigned i = 0; i < NumElts; ++i) 4314 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); 4315 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4316 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4317 } 4318 4319 return SDValue(); 4320} 4321 4322// Gather data to see if the operation can be modelled as a 4323// shuffle in combination with VEXTs. 4324SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, 4325 SelectionDAG &DAG) const { 4326 DebugLoc dl = Op.getDebugLoc(); 4327 EVT VT = Op.getValueType(); 4328 unsigned NumElts = VT.getVectorNumElements(); 4329 4330 SmallVector<SDValue, 2> SourceVecs; 4331 SmallVector<unsigned, 2> MinElts; 4332 SmallVector<unsigned, 2> MaxElts; 4333 4334 for (unsigned i = 0; i < NumElts; ++i) { 4335 SDValue V = Op.getOperand(i); 4336 if (V.getOpcode() == ISD::UNDEF) 4337 continue; 4338 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4339 // A shuffle can only come from building a vector from various 4340 // elements of other vectors. 4341 return SDValue(); 4342 } else if (V.getOperand(0).getValueType().getVectorElementType() != 4343 VT.getVectorElementType()) { 4344 // This code doesn't know how to handle shuffles where the vector 4345 // element types do not match (this happens because type legalization 4346 // promotes the return type of EXTRACT_VECTOR_ELT). 4347 // FIXME: It might be appropriate to extend this code to handle 4348 // mismatched types. 4349 return SDValue(); 4350 } 4351 4352 // Record this extraction against the appropriate vector if possible... 4353 SDValue SourceVec = V.getOperand(0); 4354 // If the element number isn't a constant, we can't effectively 4355 // analyze what's going on. 4356 if (!isa<ConstantSDNode>(V.getOperand(1))) 4357 return SDValue(); 4358 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4359 bool FoundSource = false; 4360 for (unsigned j = 0; j < SourceVecs.size(); ++j) { 4361 if (SourceVecs[j] == SourceVec) { 4362 if (MinElts[j] > EltNo) 4363 MinElts[j] = EltNo; 4364 if (MaxElts[j] < EltNo) 4365 MaxElts[j] = EltNo; 4366 FoundSource = true; 4367 break; 4368 } 4369 } 4370 4371 // Or record a new source if not... 4372 if (!FoundSource) { 4373 SourceVecs.push_back(SourceVec); 4374 MinElts.push_back(EltNo); 4375 MaxElts.push_back(EltNo); 4376 } 4377 } 4378 4379 // Currently only do something sane when at most two source vectors 4380 // involved. 4381 if (SourceVecs.size() > 2) 4382 return SDValue(); 4383 4384 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; 4385 int VEXTOffsets[2] = {0, 0}; 4386 4387 // This loop extracts the usage patterns of the source vectors 4388 // and prepares appropriate SDValues for a shuffle if possible. 4389 for (unsigned i = 0; i < SourceVecs.size(); ++i) { 4390 if (SourceVecs[i].getValueType() == VT) { 4391 // No VEXT necessary 4392 ShuffleSrcs[i] = SourceVecs[i]; 4393 VEXTOffsets[i] = 0; 4394 continue; 4395 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) { 4396 // It probably isn't worth padding out a smaller vector just to 4397 // break it down again in a shuffle. 4398 return SDValue(); 4399 } 4400 4401 // Since only 64-bit and 128-bit vectors are legal on ARM and 4402 // we've eliminated the other cases... 4403 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && 4404 "unexpected vector sizes in ReconstructShuffle"); 4405 4406 if (MaxElts[i] - MinElts[i] >= NumElts) { 4407 // Span too large for a VEXT to cope 4408 return SDValue(); 4409 } 4410 4411 if (MinElts[i] >= NumElts) { 4412 // The extraction can just take the second half 4413 VEXTOffsets[i] = NumElts; 4414 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4415 SourceVecs[i], 4416 DAG.getIntPtrConstant(NumElts)); 4417 } else if (MaxElts[i] < NumElts) { 4418 // The extraction can just take the first half 4419 VEXTOffsets[i] = 0; 4420 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4421 SourceVecs[i], 4422 DAG.getIntPtrConstant(0)); 4423 } else { 4424 // An actual VEXT is needed 4425 VEXTOffsets[i] = MinElts[i]; 4426 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4427 SourceVecs[i], 4428 DAG.getIntPtrConstant(0)); 4429 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4430 SourceVecs[i], 4431 DAG.getIntPtrConstant(NumElts)); 4432 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, 4433 DAG.getConstant(VEXTOffsets[i], MVT::i32)); 4434 } 4435 } 4436 4437 SmallVector<int, 8> Mask; 4438 4439 for (unsigned i = 0; i < NumElts; ++i) { 4440 SDValue Entry = Op.getOperand(i); 4441 if (Entry.getOpcode() == ISD::UNDEF) { 4442 Mask.push_back(-1); 4443 continue; 4444 } 4445 4446 SDValue ExtractVec = Entry.getOperand(0); 4447 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i) 4448 .getOperand(1))->getSExtValue(); 4449 if (ExtractVec == SourceVecs[0]) { 4450 Mask.push_back(ExtractElt - VEXTOffsets[0]); 4451 } else { 4452 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); 4453 } 4454 } 4455 4456 // Final check before we try to produce nonsense... 4457 if (isShuffleMaskLegal(Mask, VT)) 4458 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], 4459 &Mask[0]); 4460 4461 return SDValue(); 4462} 4463 4464/// isShuffleMaskLegal - Targets can use this to indicate that they only 4465/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4466/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4467/// are assumed to be legal. 4468bool 4469ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 4470 EVT VT) const { 4471 if (VT.getVectorNumElements() == 4 && 4472 (VT.is128BitVector() || VT.is64BitVector())) { 4473 unsigned PFIndexes[4]; 4474 for (unsigned i = 0; i != 4; ++i) { 4475 if (M[i] < 0) 4476 PFIndexes[i] = 8; 4477 else 4478 PFIndexes[i] = M[i]; 4479 } 4480 4481 // Compute the index in the perfect shuffle table. 4482 unsigned PFTableIndex = 4483 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4484 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4485 unsigned Cost = (PFEntry >> 30); 4486 4487 if (Cost <= 4) 4488 return true; 4489 } 4490 4491 bool ReverseVEXT; 4492 unsigned Imm, WhichResult; 4493 4494 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4495 return (EltSize >= 32 || 4496 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 4497 isVREVMask(M, VT, 64) || 4498 isVREVMask(M, VT, 32) || 4499 isVREVMask(M, VT, 16) || 4500 isVEXTMask(M, VT, ReverseVEXT, Imm) || 4501 isVTBLMask(M, VT) || 4502 isVTRNMask(M, VT, WhichResult) || 4503 isVUZPMask(M, VT, WhichResult) || 4504 isVZIPMask(M, VT, WhichResult) || 4505 isVTRN_v_undef_Mask(M, VT, WhichResult) || 4506 isVUZP_v_undef_Mask(M, VT, WhichResult) || 4507 isVZIP_v_undef_Mask(M, VT, WhichResult)); 4508} 4509 4510/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4511/// the specified operations to build the shuffle. 4512static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4513 SDValue RHS, SelectionDAG &DAG, 4514 DebugLoc dl) { 4515 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4516 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4517 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4518 4519 enum { 4520 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4521 OP_VREV, 4522 OP_VDUP0, 4523 OP_VDUP1, 4524 OP_VDUP2, 4525 OP_VDUP3, 4526 OP_VEXT1, 4527 OP_VEXT2, 4528 OP_VEXT3, 4529 OP_VUZPL, // VUZP, left result 4530 OP_VUZPR, // VUZP, right result 4531 OP_VZIPL, // VZIP, left result 4532 OP_VZIPR, // VZIP, right result 4533 OP_VTRNL, // VTRN, left result 4534 OP_VTRNR // VTRN, right result 4535 }; 4536 4537 if (OpNum == OP_COPY) { 4538 if (LHSID == (1*9+2)*9+3) return LHS; 4539 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4540 return RHS; 4541 } 4542 4543 SDValue OpLHS, OpRHS; 4544 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4545 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4546 EVT VT = OpLHS.getValueType(); 4547 4548 switch (OpNum) { 4549 default: llvm_unreachable("Unknown shuffle opcode!"); 4550 case OP_VREV: 4551 // VREV divides the vector in half and swaps within the half. 4552 if (VT.getVectorElementType() == MVT::i32 || 4553 VT.getVectorElementType() == MVT::f32) 4554 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 4555 // vrev <4 x i16> -> VREV32 4556 if (VT.getVectorElementType() == MVT::i16) 4557 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); 4558 // vrev <4 x i8> -> VREV16 4559 assert(VT.getVectorElementType() == MVT::i8); 4560 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); 4561 case OP_VDUP0: 4562 case OP_VDUP1: 4563 case OP_VDUP2: 4564 case OP_VDUP3: 4565 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4566 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 4567 case OP_VEXT1: 4568 case OP_VEXT2: 4569 case OP_VEXT3: 4570 return DAG.getNode(ARMISD::VEXT, dl, VT, 4571 OpLHS, OpRHS, 4572 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 4573 case OP_VUZPL: 4574 case OP_VUZPR: 4575 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4576 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 4577 case OP_VZIPL: 4578 case OP_VZIPR: 4579 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4580 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 4581 case OP_VTRNL: 4582 case OP_VTRNR: 4583 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4584 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 4585 } 4586} 4587 4588static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, 4589 ArrayRef<int> ShuffleMask, 4590 SelectionDAG &DAG) { 4591 // Check to see if we can use the VTBL instruction. 4592 SDValue V1 = Op.getOperand(0); 4593 SDValue V2 = Op.getOperand(1); 4594 DebugLoc DL = Op.getDebugLoc(); 4595 4596 SmallVector<SDValue, 8> VTBLMask; 4597 for (ArrayRef<int>::iterator 4598 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I) 4599 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32)); 4600 4601 if (V2.getNode()->getOpcode() == ISD::UNDEF) 4602 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, 4603 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4604 &VTBLMask[0], 8)); 4605 4606 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 4607 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4608 &VTBLMask[0], 8)); 4609} 4610 4611static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4612 SDValue V1 = Op.getOperand(0); 4613 SDValue V2 = Op.getOperand(1); 4614 DebugLoc dl = Op.getDebugLoc(); 4615 EVT VT = Op.getValueType(); 4616 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4617 4618 // Convert shuffles that are directly supported on NEON to target-specific 4619 // DAG nodes, instead of keeping them as shuffles and matching them again 4620 // during code selection. This is more efficient and avoids the possibility 4621 // of inconsistencies between legalization and selection. 4622 // FIXME: floating-point vectors should be canonicalized to integer vectors 4623 // of the same time so that they get CSEd properly. 4624 ArrayRef<int> ShuffleMask = SVN->getMask(); 4625 4626 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4627 if (EltSize <= 32) { 4628 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 4629 int Lane = SVN->getSplatIndex(); 4630 // If this is undef splat, generate it via "just" vdup, if possible. 4631 if (Lane == -1) Lane = 0; 4632 4633 // Test if V1 is a SCALAR_TO_VECTOR. 4634 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4635 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4636 } 4637 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR 4638 // (and probably will turn into a SCALAR_TO_VECTOR once legalization 4639 // reaches it). 4640 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR && 4641 !isa<ConstantSDNode>(V1.getOperand(0))) { 4642 bool IsScalarToVector = true; 4643 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) 4644 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) { 4645 IsScalarToVector = false; 4646 break; 4647 } 4648 if (IsScalarToVector) 4649 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4650 } 4651 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 4652 DAG.getConstant(Lane, MVT::i32)); 4653 } 4654 4655 bool ReverseVEXT; 4656 unsigned Imm; 4657 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 4658 if (ReverseVEXT) 4659 std::swap(V1, V2); 4660 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 4661 DAG.getConstant(Imm, MVT::i32)); 4662 } 4663 4664 if (isVREVMask(ShuffleMask, VT, 64)) 4665 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 4666 if (isVREVMask(ShuffleMask, VT, 32)) 4667 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 4668 if (isVREVMask(ShuffleMask, VT, 16)) 4669 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 4670 4671 // Check for Neon shuffles that modify both input vectors in place. 4672 // If both results are used, i.e., if there are two shuffles with the same 4673 // source operands and with masks corresponding to both results of one of 4674 // these operations, DAG memoization will ensure that a single node is 4675 // used for both shuffles. 4676 unsigned WhichResult; 4677 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 4678 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4679 V1, V2).getValue(WhichResult); 4680 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 4681 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4682 V1, V2).getValue(WhichResult); 4683 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 4684 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4685 V1, V2).getValue(WhichResult); 4686 4687 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4688 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4689 V1, V1).getValue(WhichResult); 4690 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4691 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4692 V1, V1).getValue(WhichResult); 4693 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4694 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4695 V1, V1).getValue(WhichResult); 4696 } 4697 4698 // If the shuffle is not directly supported and it has 4 elements, use 4699 // the PerfectShuffle-generated table to synthesize it from other shuffles. 4700 unsigned NumElts = VT.getVectorNumElements(); 4701 if (NumElts == 4) { 4702 unsigned PFIndexes[4]; 4703 for (unsigned i = 0; i != 4; ++i) { 4704 if (ShuffleMask[i] < 0) 4705 PFIndexes[i] = 8; 4706 else 4707 PFIndexes[i] = ShuffleMask[i]; 4708 } 4709 4710 // Compute the index in the perfect shuffle table. 4711 unsigned PFTableIndex = 4712 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4713 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4714 unsigned Cost = (PFEntry >> 30); 4715 4716 if (Cost <= 4) 4717 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4718 } 4719 4720 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 4721 if (EltSize >= 32) { 4722 // Do the expansion with floating-point types, since that is what the VFP 4723 // registers are defined to use, and since i64 is not legal. 4724 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4725 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4726 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 4727 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 4728 SmallVector<SDValue, 8> Ops; 4729 for (unsigned i = 0; i < NumElts; ++i) { 4730 if (ShuffleMask[i] < 0) 4731 Ops.push_back(DAG.getUNDEF(EltVT)); 4732 else 4733 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 4734 ShuffleMask[i] < (int)NumElts ? V1 : V2, 4735 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 4736 MVT::i32))); 4737 } 4738 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4739 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4740 } 4741 4742 if (VT == MVT::v8i8) { 4743 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); 4744 if (NewOp.getNode()) 4745 return NewOp; 4746 } 4747 4748 return SDValue(); 4749} 4750 4751static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4752 // INSERT_VECTOR_ELT is legal only for immediate indexes. 4753 SDValue Lane = Op.getOperand(2); 4754 if (!isa<ConstantSDNode>(Lane)) 4755 return SDValue(); 4756 4757 return Op; 4758} 4759 4760static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4761 // EXTRACT_VECTOR_ELT is legal only for immediate indexes. 4762 SDValue Lane = Op.getOperand(1); 4763 if (!isa<ConstantSDNode>(Lane)) 4764 return SDValue(); 4765 4766 SDValue Vec = Op.getOperand(0); 4767 if (Op.getValueType() == MVT::i32 && 4768 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { 4769 DebugLoc dl = Op.getDebugLoc(); 4770 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 4771 } 4772 4773 return Op; 4774} 4775 4776static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 4777 // The only time a CONCAT_VECTORS operation can have legal types is when 4778 // two 64-bit vectors are concatenated to a 128-bit vector. 4779 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 4780 "unexpected CONCAT_VECTORS"); 4781 DebugLoc dl = Op.getDebugLoc(); 4782 SDValue Val = DAG.getUNDEF(MVT::v2f64); 4783 SDValue Op0 = Op.getOperand(0); 4784 SDValue Op1 = Op.getOperand(1); 4785 if (Op0.getOpcode() != ISD::UNDEF) 4786 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4787 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), 4788 DAG.getIntPtrConstant(0)); 4789 if (Op1.getOpcode() != ISD::UNDEF) 4790 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4791 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), 4792 DAG.getIntPtrConstant(1)); 4793 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); 4794} 4795 4796/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each 4797/// element has been zero/sign-extended, depending on the isSigned parameter, 4798/// from an integer type half its size. 4799static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, 4800 bool isSigned) { 4801 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32. 4802 EVT VT = N->getValueType(0); 4803 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { 4804 SDNode *BVN = N->getOperand(0).getNode(); 4805 if (BVN->getValueType(0) != MVT::v4i32 || 4806 BVN->getOpcode() != ISD::BUILD_VECTOR) 4807 return false; 4808 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4809 unsigned HiElt = 1 - LoElt; 4810 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt)); 4811 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); 4812 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); 4813 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); 4814 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) 4815 return false; 4816 if (isSigned) { 4817 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && 4818 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) 4819 return true; 4820 } else { 4821 if (Hi0->isNullValue() && Hi1->isNullValue()) 4822 return true; 4823 } 4824 return false; 4825 } 4826 4827 if (N->getOpcode() != ISD::BUILD_VECTOR) 4828 return false; 4829 4830 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 4831 SDNode *Elt = N->getOperand(i).getNode(); 4832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) { 4833 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4834 unsigned HalfSize = EltSize / 2; 4835 if (isSigned) { 4836 if (!isIntN(HalfSize, C->getSExtValue())) 4837 return false; 4838 } else { 4839 if (!isUIntN(HalfSize, C->getZExtValue())) 4840 return false; 4841 } 4842 continue; 4843 } 4844 return false; 4845 } 4846 4847 return true; 4848} 4849 4850/// isSignExtended - Check if a node is a vector value that is sign-extended 4851/// or a constant BUILD_VECTOR with sign-extended elements. 4852static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { 4853 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) 4854 return true; 4855 if (isExtendedBUILD_VECTOR(N, DAG, true)) 4856 return true; 4857 return false; 4858} 4859 4860/// isZeroExtended - Check if a node is a vector value that is zero-extended 4861/// or a constant BUILD_VECTOR with zero-extended elements. 4862static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { 4863 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) 4864 return true; 4865 if (isExtendedBUILD_VECTOR(N, DAG, false)) 4866 return true; 4867 return false; 4868} 4869 4870/// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending 4871/// load, or BUILD_VECTOR with extended elements, return the unextended value. 4872static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { 4873 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) 4874 return N->getOperand(0); 4875 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) 4876 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), 4877 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), 4878 LD->isNonTemporal(), LD->isInvariant(), 4879 LD->getAlignment()); 4880 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will 4881 // have been legalized as a BITCAST from v4i32. 4882 if (N->getOpcode() == ISD::BITCAST) { 4883 SDNode *BVN = N->getOperand(0).getNode(); 4884 assert(BVN->getOpcode() == ISD::BUILD_VECTOR && 4885 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR"); 4886 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4887 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32, 4888 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2)); 4889 } 4890 // Construct a new BUILD_VECTOR with elements truncated to half the size. 4891 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); 4892 EVT VT = N->getValueType(0); 4893 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; 4894 unsigned NumElts = VT.getVectorNumElements(); 4895 MVT TruncVT = MVT::getIntegerVT(EltSize); 4896 SmallVector<SDValue, 8> Ops; 4897 for (unsigned i = 0; i != NumElts; ++i) { 4898 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i)); 4899 const APInt &CInt = C->getAPIntValue(); 4900 // Element types smaller than 32 bits are not legal, so use i32 elements. 4901 // The values are implicitly truncated so sext vs. zext doesn't matter. 4902 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32)); 4903 } 4904 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 4905 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts); 4906} 4907 4908static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { 4909 unsigned Opcode = N->getOpcode(); 4910 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4911 SDNode *N0 = N->getOperand(0).getNode(); 4912 SDNode *N1 = N->getOperand(1).getNode(); 4913 return N0->hasOneUse() && N1->hasOneUse() && 4914 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); 4915 } 4916 return false; 4917} 4918 4919static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { 4920 unsigned Opcode = N->getOpcode(); 4921 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4922 SDNode *N0 = N->getOperand(0).getNode(); 4923 SDNode *N1 = N->getOperand(1).getNode(); 4924 return N0->hasOneUse() && N1->hasOneUse() && 4925 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); 4926 } 4927 return false; 4928} 4929 4930static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { 4931 // Multiplications are only custom-lowered for 128-bit vectors so that 4932 // VMULL can be detected. Otherwise v2i64 multiplications are not legal. 4933 EVT VT = Op.getValueType(); 4934 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); 4935 SDNode *N0 = Op.getOperand(0).getNode(); 4936 SDNode *N1 = Op.getOperand(1).getNode(); 4937 unsigned NewOpc = 0; 4938 bool isMLA = false; 4939 bool isN0SExt = isSignExtended(N0, DAG); 4940 bool isN1SExt = isSignExtended(N1, DAG); 4941 if (isN0SExt && isN1SExt) 4942 NewOpc = ARMISD::VMULLs; 4943 else { 4944 bool isN0ZExt = isZeroExtended(N0, DAG); 4945 bool isN1ZExt = isZeroExtended(N1, DAG); 4946 if (isN0ZExt && isN1ZExt) 4947 NewOpc = ARMISD::VMULLu; 4948 else if (isN1SExt || isN1ZExt) { 4949 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these 4950 // into (s/zext A * s/zext C) + (s/zext B * s/zext C) 4951 if (isN1SExt && isAddSubSExt(N0, DAG)) { 4952 NewOpc = ARMISD::VMULLs; 4953 isMLA = true; 4954 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { 4955 NewOpc = ARMISD::VMULLu; 4956 isMLA = true; 4957 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { 4958 std::swap(N0, N1); 4959 NewOpc = ARMISD::VMULLu; 4960 isMLA = true; 4961 } 4962 } 4963 4964 if (!NewOpc) { 4965 if (VT == MVT::v2i64) 4966 // Fall through to expand this. It is not legal. 4967 return SDValue(); 4968 else 4969 // Other vector multiplications are legal. 4970 return Op; 4971 } 4972 } 4973 4974 // Legalize to a VMULL instruction. 4975 DebugLoc DL = Op.getDebugLoc(); 4976 SDValue Op0; 4977 SDValue Op1 = SkipExtension(N1, DAG); 4978 if (!isMLA) { 4979 Op0 = SkipExtension(N0, DAG); 4980 assert(Op0.getValueType().is64BitVector() && 4981 Op1.getValueType().is64BitVector() && 4982 "unexpected types for extended operands to VMULL"); 4983 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); 4984 } 4985 4986 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during 4987 // isel lowering to take advantage of no-stall back to back vmul + vmla. 4988 // vmull q0, d4, d6 4989 // vmlal q0, d5, d6 4990 // is faster than 4991 // vaddl q0, d4, d5 4992 // vmovl q1, d6 4993 // vmul q0, q0, q1 4994 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); 4995 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); 4996 EVT Op1VT = Op1.getValueType(); 4997 return DAG.getNode(N0->getOpcode(), DL, VT, 4998 DAG.getNode(NewOpc, DL, VT, 4999 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), 5000 DAG.getNode(NewOpc, DL, VT, 5001 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); 5002} 5003 5004static SDValue 5005LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) { 5006 // Convert to float 5007 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo)); 5008 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo)); 5009 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); 5010 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); 5011 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 5012 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); 5013 // Get reciprocal estimate. 5014 // float4 recip = vrecpeq_f32(yf); 5015 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 5016 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y); 5017 // Because char has a smaller range than uchar, we can actually get away 5018 // without any newton steps. This requires that we use a weird bias 5019 // of 0xb000, however (again, this has been exhaustively tested). 5020 // float4 result = as_float4(as_int4(xf*recip) + 0xb000); 5021 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); 5022 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); 5023 Y = DAG.getConstant(0xb000, MVT::i32); 5024 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); 5025 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); 5026 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); 5027 // Convert back to short. 5028 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); 5029 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); 5030 return X; 5031} 5032 5033static SDValue 5034LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) { 5035 SDValue N2; 5036 // Convert to float. 5037 // float4 yf = vcvt_f32_s32(vmovl_s16(y)); 5038 // float4 xf = vcvt_f32_s32(vmovl_s16(x)); 5039 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); 5040 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); 5041 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 5042 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 5043 5044 // Use reciprocal estimate and one refinement step. 5045 // float4 recip = vrecpeq_f32(yf); 5046 // recip *= vrecpsq_f32(yf, recip); 5047 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 5048 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); 5049 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 5050 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 5051 N1, N2); 5052 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 5053 // Because short has a smaller range than ushort, we can actually get away 5054 // with only a single newton step. This requires that we use a weird bias 5055 // of 89, however (again, this has been exhaustively tested). 5056 // float4 result = as_float4(as_int4(xf*recip) + 0x89); 5057 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 5058 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 5059 N1 = DAG.getConstant(0x89, MVT::i32); 5060 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 5061 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 5062 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 5063 // Convert back to integer and return. 5064 // return vmovn_s32(vcvt_s32_f32(result)); 5065 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 5066 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 5067 return N0; 5068} 5069 5070static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { 5071 EVT VT = Op.getValueType(); 5072 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 5073 "unexpected type for custom-lowering ISD::SDIV"); 5074 5075 DebugLoc dl = Op.getDebugLoc(); 5076 SDValue N0 = Op.getOperand(0); 5077 SDValue N1 = Op.getOperand(1); 5078 SDValue N2, N3; 5079 5080 if (VT == MVT::v8i8) { 5081 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); 5082 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); 5083 5084 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 5085 DAG.getIntPtrConstant(4)); 5086 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 5087 DAG.getIntPtrConstant(4)); 5088 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 5089 DAG.getIntPtrConstant(0)); 5090 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 5091 DAG.getIntPtrConstant(0)); 5092 5093 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 5094 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 5095 5096 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 5097 N0 = LowerCONCAT_VECTORS(N0, DAG); 5098 5099 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); 5100 return N0; 5101 } 5102 return LowerSDIV_v4i16(N0, N1, dl, DAG); 5103} 5104 5105static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { 5106 EVT VT = Op.getValueType(); 5107 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 5108 "unexpected type for custom-lowering ISD::UDIV"); 5109 5110 DebugLoc dl = Op.getDebugLoc(); 5111 SDValue N0 = Op.getOperand(0); 5112 SDValue N1 = Op.getOperand(1); 5113 SDValue N2, N3; 5114 5115 if (VT == MVT::v8i8) { 5116 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); 5117 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); 5118 5119 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 5120 DAG.getIntPtrConstant(4)); 5121 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 5122 DAG.getIntPtrConstant(4)); 5123 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 5124 DAG.getIntPtrConstant(0)); 5125 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 5126 DAG.getIntPtrConstant(0)); 5127 5128 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 5129 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 5130 5131 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 5132 N0 = LowerCONCAT_VECTORS(N0, DAG); 5133 5134 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, 5135 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32), 5136 N0); 5137 return N0; 5138 } 5139 5140 // v4i16 sdiv ... Convert to float. 5141 // float4 yf = vcvt_f32_s32(vmovl_u16(y)); 5142 // float4 xf = vcvt_f32_s32(vmovl_u16(x)); 5143 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); 5144 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); 5145 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 5146 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 5147 5148 // Use reciprocal estimate and two refinement steps. 5149 // float4 recip = vrecpeq_f32(yf); 5150 // recip *= vrecpsq_f32(yf, recip); 5151 // recip *= vrecpsq_f32(yf, recip); 5152 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 5153 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); 5154 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 5155 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 5156 BN1, N2); 5157 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 5158 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 5159 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 5160 BN1, N2); 5161 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 5162 // Simply multiplying by the reciprocal estimate can leave us a few ulps 5163 // too low, so we add 2 ulps (exhaustive testing shows that this is enough, 5164 // and that it will never cause us to return an answer too large). 5165 // float4 result = as_float4(as_int4(xf*recip) + 2); 5166 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 5167 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 5168 N1 = DAG.getConstant(2, MVT::i32); 5169 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 5170 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 5171 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 5172 // Convert back to integer and return. 5173 // return vmovn_u32(vcvt_s32_f32(result)); 5174 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 5175 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 5176 return N0; 5177} 5178 5179static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 5180 EVT VT = Op.getNode()->getValueType(0); 5181 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 5182 5183 unsigned Opc; 5184 bool ExtraOp = false; 5185 switch (Op.getOpcode()) { 5186 default: llvm_unreachable("Invalid code"); 5187 case ISD::ADDC: Opc = ARMISD::ADDC; break; 5188 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; 5189 case ISD::SUBC: Opc = ARMISD::SUBC; break; 5190 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; 5191 } 5192 5193 if (!ExtraOp) 5194 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 5195 Op.getOperand(1)); 5196 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 5197 Op.getOperand(1), Op.getOperand(2)); 5198} 5199 5200static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { 5201 // Monotonic load/store is legal for all targets 5202 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) 5203 return Op; 5204 5205 // Aquire/Release load/store is not legal for targets without a 5206 // dmb or equivalent available. 5207 return SDValue(); 5208} 5209 5210 5211static void 5212ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, 5213 SelectionDAG &DAG, unsigned NewOp) { 5214 DebugLoc dl = Node->getDebugLoc(); 5215 assert (Node->getValueType(0) == MVT::i64 && 5216 "Only know how to expand i64 atomics"); 5217 5218 SmallVector<SDValue, 6> Ops; 5219 Ops.push_back(Node->getOperand(0)); // Chain 5220 Ops.push_back(Node->getOperand(1)); // Ptr 5221 // Low part of Val1 5222 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5223 Node->getOperand(2), DAG.getIntPtrConstant(0))); 5224 // High part of Val1 5225 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5226 Node->getOperand(2), DAG.getIntPtrConstant(1))); 5227 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) { 5228 // High part of Val1 5229 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5230 Node->getOperand(3), DAG.getIntPtrConstant(0))); 5231 // High part of Val2 5232 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5233 Node->getOperand(3), DAG.getIntPtrConstant(1))); 5234 } 5235 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 5236 SDValue Result = 5237 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64, 5238 cast<MemSDNode>(Node)->getMemOperand()); 5239 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; 5240 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 5241 Results.push_back(Result.getValue(2)); 5242} 5243 5244SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5245 switch (Op.getOpcode()) { 5246 default: llvm_unreachable("Don't know how to custom lower this!"); 5247 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5248 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 5249 case ISD::GlobalAddress: 5250 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 5251 LowerGlobalAddressELF(Op, DAG); 5252 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5253 case ISD::SELECT: return LowerSELECT(Op, DAG); 5254 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 5255 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 5256 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 5257 case ISD::VASTART: return LowerVASTART(Op, DAG); 5258 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 5259 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); 5260 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); 5261 case ISD::SINT_TO_FP: 5262 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 5263 case ISD::FP_TO_SINT: 5264 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 5265 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 5266 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5267 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5268 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 5269 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 5270 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 5271 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 5272 Subtarget); 5273 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); 5274 case ISD::SHL: 5275 case ISD::SRL: 5276 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 5277 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 5278 case ISD::SRL_PARTS: 5279 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 5280 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 5281 case ISD::SETCC: return LowerVSETCC(Op, DAG); 5282 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget); 5283 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); 5284 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5285 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 5286 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 5287 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 5288 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5289 case ISD::MUL: return LowerMUL(Op, DAG); 5290 case ISD::SDIV: return LowerSDIV(Op, DAG); 5291 case ISD::UDIV: return LowerUDIV(Op, DAG); 5292 case ISD::ADDC: 5293 case ISD::ADDE: 5294 case ISD::SUBC: 5295 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 5296 case ISD::ATOMIC_LOAD: 5297 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); 5298 } 5299} 5300 5301/// ReplaceNodeResults - Replace the results of node with an illegal result 5302/// type with new values built out of custom code. 5303void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 5304 SmallVectorImpl<SDValue>&Results, 5305 SelectionDAG &DAG) const { 5306 SDValue Res; 5307 switch (N->getOpcode()) { 5308 default: 5309 llvm_unreachable("Don't know how to custom expand this!"); 5310 case ISD::BITCAST: 5311 Res = ExpandBITCAST(N, DAG); 5312 break; 5313 case ISD::SRL: 5314 case ISD::SRA: 5315 Res = Expand64BitShift(N, DAG, Subtarget); 5316 break; 5317 case ISD::ATOMIC_LOAD_ADD: 5318 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); 5319 return; 5320 case ISD::ATOMIC_LOAD_AND: 5321 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); 5322 return; 5323 case ISD::ATOMIC_LOAD_NAND: 5324 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); 5325 return; 5326 case ISD::ATOMIC_LOAD_OR: 5327 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); 5328 return; 5329 case ISD::ATOMIC_LOAD_SUB: 5330 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); 5331 return; 5332 case ISD::ATOMIC_LOAD_XOR: 5333 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); 5334 return; 5335 case ISD::ATOMIC_SWAP: 5336 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); 5337 return; 5338 case ISD::ATOMIC_CMP_SWAP: 5339 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG); 5340 return; 5341 } 5342 if (Res.getNode()) 5343 Results.push_back(Res); 5344} 5345 5346//===----------------------------------------------------------------------===// 5347// ARM Scheduler Hooks 5348//===----------------------------------------------------------------------===// 5349 5350MachineBasicBlock * 5351ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 5352 MachineBasicBlock *BB, 5353 unsigned Size) const { 5354 unsigned dest = MI->getOperand(0).getReg(); 5355 unsigned ptr = MI->getOperand(1).getReg(); 5356 unsigned oldval = MI->getOperand(2).getReg(); 5357 unsigned newval = MI->getOperand(3).getReg(); 5358 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5359 DebugLoc dl = MI->getDebugLoc(); 5360 bool isThumb2 = Subtarget->isThumb2(); 5361 5362 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5363 unsigned scratch = MRI.createVirtualRegister(isThumb2 ? 5364 (const TargetRegisterClass*)&ARM::rGPRRegClass : 5365 (const TargetRegisterClass*)&ARM::GPRRegClass); 5366 5367 if (isThumb2) { 5368 MRI.constrainRegClass(dest, &ARM::rGPRRegClass); 5369 MRI.constrainRegClass(oldval, &ARM::rGPRRegClass); 5370 MRI.constrainRegClass(newval, &ARM::rGPRRegClass); 5371 } 5372 5373 unsigned ldrOpc, strOpc; 5374 switch (Size) { 5375 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5376 case 1: 5377 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5378 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5379 break; 5380 case 2: 5381 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5382 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5383 break; 5384 case 4: 5385 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5386 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5387 break; 5388 } 5389 5390 MachineFunction *MF = BB->getParent(); 5391 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5392 MachineFunction::iterator It = BB; 5393 ++It; // insert the new blocks after the current block 5394 5395 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5396 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5397 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5398 MF->insert(It, loop1MBB); 5399 MF->insert(It, loop2MBB); 5400 MF->insert(It, exitMBB); 5401 5402 // Transfer the remainder of BB and its successor edges to exitMBB. 5403 exitMBB->splice(exitMBB->begin(), BB, 5404 llvm::next(MachineBasicBlock::iterator(MI)), 5405 BB->end()); 5406 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5407 5408 // thisMBB: 5409 // ... 5410 // fallthrough --> loop1MBB 5411 BB->addSuccessor(loop1MBB); 5412 5413 // loop1MBB: 5414 // ldrex dest, [ptr] 5415 // cmp dest, oldval 5416 // bne exitMBB 5417 BB = loop1MBB; 5418 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5419 if (ldrOpc == ARM::t2LDREX) 5420 MIB.addImm(0); 5421 AddDefaultPred(MIB); 5422 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5423 .addReg(dest).addReg(oldval)); 5424 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5425 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5426 BB->addSuccessor(loop2MBB); 5427 BB->addSuccessor(exitMBB); 5428 5429 // loop2MBB: 5430 // strex scratch, newval, [ptr] 5431 // cmp scratch, #0 5432 // bne loop1MBB 5433 BB = loop2MBB; 5434 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr); 5435 if (strOpc == ARM::t2STREX) 5436 MIB.addImm(0); 5437 AddDefaultPred(MIB); 5438 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5439 .addReg(scratch).addImm(0)); 5440 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5441 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5442 BB->addSuccessor(loop1MBB); 5443 BB->addSuccessor(exitMBB); 5444 5445 // exitMBB: 5446 // ... 5447 BB = exitMBB; 5448 5449 MI->eraseFromParent(); // The instruction is gone now. 5450 5451 return BB; 5452} 5453 5454MachineBasicBlock * 5455ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5456 unsigned Size, unsigned BinOpcode) const { 5457 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5458 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5459 5460 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5461 MachineFunction *MF = BB->getParent(); 5462 MachineFunction::iterator It = BB; 5463 ++It; 5464 5465 unsigned dest = MI->getOperand(0).getReg(); 5466 unsigned ptr = MI->getOperand(1).getReg(); 5467 unsigned incr = MI->getOperand(2).getReg(); 5468 DebugLoc dl = MI->getDebugLoc(); 5469 bool isThumb2 = Subtarget->isThumb2(); 5470 5471 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5472 if (isThumb2) { 5473 MRI.constrainRegClass(dest, &ARM::rGPRRegClass); 5474 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass); 5475 } 5476 5477 unsigned ldrOpc, strOpc; 5478 switch (Size) { 5479 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5480 case 1: 5481 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5482 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5483 break; 5484 case 2: 5485 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5486 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5487 break; 5488 case 4: 5489 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5490 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5491 break; 5492 } 5493 5494 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5495 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5496 MF->insert(It, loopMBB); 5497 MF->insert(It, exitMBB); 5498 5499 // Transfer the remainder of BB and its successor edges to exitMBB. 5500 exitMBB->splice(exitMBB->begin(), BB, 5501 llvm::next(MachineBasicBlock::iterator(MI)), 5502 BB->end()); 5503 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5504 5505 const TargetRegisterClass *TRC = isThumb2 ? 5506 (const TargetRegisterClass*)&ARM::rGPRRegClass : 5507 (const TargetRegisterClass*)&ARM::GPRRegClass; 5508 unsigned scratch = MRI.createVirtualRegister(TRC); 5509 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 5510 5511 // thisMBB: 5512 // ... 5513 // fallthrough --> loopMBB 5514 BB->addSuccessor(loopMBB); 5515 5516 // loopMBB: 5517 // ldrex dest, ptr 5518 // <binop> scratch2, dest, incr 5519 // strex scratch, scratch2, ptr 5520 // cmp scratch, #0 5521 // bne- loopMBB 5522 // fallthrough --> exitMBB 5523 BB = loopMBB; 5524 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5525 if (ldrOpc == ARM::t2LDREX) 5526 MIB.addImm(0); 5527 AddDefaultPred(MIB); 5528 if (BinOpcode) { 5529 // operand order needs to go the other way for NAND 5530 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 5531 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5532 addReg(incr).addReg(dest)).addReg(0); 5533 else 5534 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5535 addReg(dest).addReg(incr)).addReg(0); 5536 } 5537 5538 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5539 if (strOpc == ARM::t2STREX) 5540 MIB.addImm(0); 5541 AddDefaultPred(MIB); 5542 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5543 .addReg(scratch).addImm(0)); 5544 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5545 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5546 5547 BB->addSuccessor(loopMBB); 5548 BB->addSuccessor(exitMBB); 5549 5550 // exitMBB: 5551 // ... 5552 BB = exitMBB; 5553 5554 MI->eraseFromParent(); // The instruction is gone now. 5555 5556 return BB; 5557} 5558 5559MachineBasicBlock * 5560ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI, 5561 MachineBasicBlock *BB, 5562 unsigned Size, 5563 bool signExtend, 5564 ARMCC::CondCodes Cond) const { 5565 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5566 5567 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5568 MachineFunction *MF = BB->getParent(); 5569 MachineFunction::iterator It = BB; 5570 ++It; 5571 5572 unsigned dest = MI->getOperand(0).getReg(); 5573 unsigned ptr = MI->getOperand(1).getReg(); 5574 unsigned incr = MI->getOperand(2).getReg(); 5575 unsigned oldval = dest; 5576 DebugLoc dl = MI->getDebugLoc(); 5577 bool isThumb2 = Subtarget->isThumb2(); 5578 5579 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5580 if (isThumb2) { 5581 MRI.constrainRegClass(dest, &ARM::rGPRRegClass); 5582 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass); 5583 } 5584 5585 unsigned ldrOpc, strOpc, extendOpc; 5586 switch (Size) { 5587 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5588 case 1: 5589 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5590 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5591 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; 5592 break; 5593 case 2: 5594 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5595 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5596 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; 5597 break; 5598 case 4: 5599 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5600 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5601 extendOpc = 0; 5602 break; 5603 } 5604 5605 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5606 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5607 MF->insert(It, loopMBB); 5608 MF->insert(It, exitMBB); 5609 5610 // Transfer the remainder of BB and its successor edges to exitMBB. 5611 exitMBB->splice(exitMBB->begin(), BB, 5612 llvm::next(MachineBasicBlock::iterator(MI)), 5613 BB->end()); 5614 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5615 5616 const TargetRegisterClass *TRC = isThumb2 ? 5617 (const TargetRegisterClass*)&ARM::rGPRRegClass : 5618 (const TargetRegisterClass*)&ARM::GPRRegClass; 5619 unsigned scratch = MRI.createVirtualRegister(TRC); 5620 unsigned scratch2 = MRI.createVirtualRegister(TRC); 5621 5622 // thisMBB: 5623 // ... 5624 // fallthrough --> loopMBB 5625 BB->addSuccessor(loopMBB); 5626 5627 // loopMBB: 5628 // ldrex dest, ptr 5629 // (sign extend dest, if required) 5630 // cmp dest, incr 5631 // cmov.cond scratch2, incr, dest 5632 // strex scratch, scratch2, ptr 5633 // cmp scratch, #0 5634 // bne- loopMBB 5635 // fallthrough --> exitMBB 5636 BB = loopMBB; 5637 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5638 if (ldrOpc == ARM::t2LDREX) 5639 MIB.addImm(0); 5640 AddDefaultPred(MIB); 5641 5642 // Sign extend the value, if necessary. 5643 if (signExtend && extendOpc) { 5644 oldval = MRI.createVirtualRegister(&ARM::GPRRegClass); 5645 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval) 5646 .addReg(dest) 5647 .addImm(0)); 5648 } 5649 5650 // Build compare and cmov instructions. 5651 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5652 .addReg(oldval).addReg(incr)); 5653 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2) 5654 .addReg(incr).addReg(oldval).addImm(Cond).addReg(ARM::CPSR); 5655 5656 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5657 if (strOpc == ARM::t2STREX) 5658 MIB.addImm(0); 5659 AddDefaultPred(MIB); 5660 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5661 .addReg(scratch).addImm(0)); 5662 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5663 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5664 5665 BB->addSuccessor(loopMBB); 5666 BB->addSuccessor(exitMBB); 5667 5668 // exitMBB: 5669 // ... 5670 BB = exitMBB; 5671 5672 MI->eraseFromParent(); // The instruction is gone now. 5673 5674 return BB; 5675} 5676 5677MachineBasicBlock * 5678ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, 5679 unsigned Op1, unsigned Op2, 5680 bool NeedsCarry, bool IsCmpxchg) const { 5681 // This also handles ATOMIC_SWAP, indicated by Op1==0. 5682 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5683 5684 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5685 MachineFunction *MF = BB->getParent(); 5686 MachineFunction::iterator It = BB; 5687 ++It; 5688 5689 unsigned destlo = MI->getOperand(0).getReg(); 5690 unsigned desthi = MI->getOperand(1).getReg(); 5691 unsigned ptr = MI->getOperand(2).getReg(); 5692 unsigned vallo = MI->getOperand(3).getReg(); 5693 unsigned valhi = MI->getOperand(4).getReg(); 5694 DebugLoc dl = MI->getDebugLoc(); 5695 bool isThumb2 = Subtarget->isThumb2(); 5696 5697 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5698 if (isThumb2) { 5699 MRI.constrainRegClass(destlo, &ARM::rGPRRegClass); 5700 MRI.constrainRegClass(desthi, &ARM::rGPRRegClass); 5701 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass); 5702 } 5703 5704 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD; 5705 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; 5706 5707 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5708 MachineBasicBlock *contBB = 0, *cont2BB = 0; 5709 if (IsCmpxchg) { 5710 contBB = MF->CreateMachineBasicBlock(LLVM_BB); 5711 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB); 5712 } 5713 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5714 MF->insert(It, loopMBB); 5715 if (IsCmpxchg) { 5716 MF->insert(It, contBB); 5717 MF->insert(It, cont2BB); 5718 } 5719 MF->insert(It, exitMBB); 5720 5721 // Transfer the remainder of BB and its successor edges to exitMBB. 5722 exitMBB->splice(exitMBB->begin(), BB, 5723 llvm::next(MachineBasicBlock::iterator(MI)), 5724 BB->end()); 5725 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5726 5727 const TargetRegisterClass *TRC = isThumb2 ? 5728 (const TargetRegisterClass*)&ARM::tGPRRegClass : 5729 (const TargetRegisterClass*)&ARM::GPRRegClass; 5730 unsigned storesuccess = MRI.createVirtualRegister(TRC); 5731 5732 // thisMBB: 5733 // ... 5734 // fallthrough --> loopMBB 5735 BB->addSuccessor(loopMBB); 5736 5737 // loopMBB: 5738 // ldrexd r2, r3, ptr 5739 // <binopa> r0, r2, incr 5740 // <binopb> r1, r3, incr 5741 // strexd storesuccess, r0, r1, ptr 5742 // cmp storesuccess, #0 5743 // bne- loopMBB 5744 // fallthrough --> exitMBB 5745 // 5746 // Note that the registers are explicitly specified because there is not any 5747 // way to force the register allocator to allocate a register pair. 5748 // 5749 // FIXME: The hardcoded registers are not necessary for Thumb2, but we 5750 // need to properly enforce the restriction that the two output registers 5751 // for ldrexd must be different. 5752 BB = loopMBB; 5753 // Load 5754 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc)) 5755 .addReg(ARM::R2, RegState::Define) 5756 .addReg(ARM::R3, RegState::Define).addReg(ptr)); 5757 // Copy r2/r3 into dest. (This copy will normally be coalesced.) 5758 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); 5759 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); 5760 5761 if (IsCmpxchg) { 5762 // Add early exit 5763 for (unsigned i = 0; i < 2; i++) { 5764 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : 5765 ARM::CMPrr)) 5766 .addReg(i == 0 ? destlo : desthi) 5767 .addReg(i == 0 ? vallo : valhi)); 5768 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5769 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5770 BB->addSuccessor(exitMBB); 5771 BB->addSuccessor(i == 0 ? contBB : cont2BB); 5772 BB = (i == 0 ? contBB : cont2BB); 5773 } 5774 5775 // Copy to physregs for strexd 5776 unsigned setlo = MI->getOperand(5).getReg(); 5777 unsigned sethi = MI->getOperand(6).getReg(); 5778 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); 5779 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi); 5780 } else if (Op1) { 5781 // Perform binary operation 5782 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) 5783 .addReg(destlo).addReg(vallo)) 5784 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry)); 5785 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1) 5786 .addReg(desthi).addReg(valhi)).addReg(0); 5787 } else { 5788 // Copy to physregs for strexd 5789 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); 5790 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi); 5791 } 5792 5793 // Store 5794 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess) 5795 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr)); 5796 // Cmp+jump 5797 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5798 .addReg(storesuccess).addImm(0)); 5799 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5800 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5801 5802 BB->addSuccessor(loopMBB); 5803 BB->addSuccessor(exitMBB); 5804 5805 // exitMBB: 5806 // ... 5807 BB = exitMBB; 5808 5809 MI->eraseFromParent(); // The instruction is gone now. 5810 5811 return BB; 5812} 5813 5814/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and 5815/// registers the function context. 5816void ARMTargetLowering:: 5817SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, 5818 MachineBasicBlock *DispatchBB, int FI) const { 5819 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5820 DebugLoc dl = MI->getDebugLoc(); 5821 MachineFunction *MF = MBB->getParent(); 5822 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5823 MachineConstantPool *MCP = MF->getConstantPool(); 5824 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5825 const Function *F = MF->getFunction(); 5826 5827 bool isThumb = Subtarget->isThumb(); 5828 bool isThumb2 = Subtarget->isThumb2(); 5829 5830 unsigned PCLabelId = AFI->createPICLabelUId(); 5831 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8; 5832 ARMConstantPoolValue *CPV = 5833 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj); 5834 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4); 5835 5836 const TargetRegisterClass *TRC = isThumb ? 5837 (const TargetRegisterClass*)&ARM::tGPRRegClass : 5838 (const TargetRegisterClass*)&ARM::GPRRegClass; 5839 5840 // Grab constant pool and fixed stack memory operands. 5841 MachineMemOperand *CPMMO = 5842 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(), 5843 MachineMemOperand::MOLoad, 4, 4); 5844 5845 MachineMemOperand *FIMMOSt = 5846 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5847 MachineMemOperand::MOStore, 4, 4); 5848 5849 // Load the address of the dispatch MBB into the jump buffer. 5850 if (isThumb2) { 5851 // Incoming value: jbuf 5852 // ldr.n r5, LCPI1_1 5853 // orr r5, r5, #1 5854 // add r5, pc 5855 // str r5, [$jbuf, #+4] ; &jbuf[1] 5856 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5857 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1) 5858 .addConstantPoolIndex(CPI) 5859 .addMemOperand(CPMMO)); 5860 // Set the low bit because of thumb mode. 5861 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5862 AddDefaultCC( 5863 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2) 5864 .addReg(NewVReg1, RegState::Kill) 5865 .addImm(0x01))); 5866 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5867 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3) 5868 .addReg(NewVReg2, RegState::Kill) 5869 .addImm(PCLabelId); 5870 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12)) 5871 .addReg(NewVReg3, RegState::Kill) 5872 .addFrameIndex(FI) 5873 .addImm(36) // &jbuf[1] :: pc 5874 .addMemOperand(FIMMOSt)); 5875 } else if (isThumb) { 5876 // Incoming value: jbuf 5877 // ldr.n r1, LCPI1_4 5878 // add r1, pc 5879 // mov r2, #1 5880 // orrs r1, r2 5881 // add r2, $jbuf, #+4 ; &jbuf[1] 5882 // str r1, [r2] 5883 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5884 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1) 5885 .addConstantPoolIndex(CPI) 5886 .addMemOperand(CPMMO)); 5887 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5888 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2) 5889 .addReg(NewVReg1, RegState::Kill) 5890 .addImm(PCLabelId); 5891 // Set the low bit because of thumb mode. 5892 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5893 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3) 5894 .addReg(ARM::CPSR, RegState::Define) 5895 .addImm(1)); 5896 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5897 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4) 5898 .addReg(ARM::CPSR, RegState::Define) 5899 .addReg(NewVReg2, RegState::Kill) 5900 .addReg(NewVReg3, RegState::Kill)); 5901 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5902 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5) 5903 .addFrameIndex(FI) 5904 .addImm(36)); // &jbuf[1] :: pc 5905 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi)) 5906 .addReg(NewVReg4, RegState::Kill) 5907 .addReg(NewVReg5, RegState::Kill) 5908 .addImm(0) 5909 .addMemOperand(FIMMOSt)); 5910 } else { 5911 // Incoming value: jbuf 5912 // ldr r1, LCPI1_1 5913 // add r1, pc, r1 5914 // str r1, [$jbuf, #+4] ; &jbuf[1] 5915 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5916 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1) 5917 .addConstantPoolIndex(CPI) 5918 .addImm(0) 5919 .addMemOperand(CPMMO)); 5920 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5921 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2) 5922 .addReg(NewVReg1, RegState::Kill) 5923 .addImm(PCLabelId)); 5924 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12)) 5925 .addReg(NewVReg2, RegState::Kill) 5926 .addFrameIndex(FI) 5927 .addImm(36) // &jbuf[1] :: pc 5928 .addMemOperand(FIMMOSt)); 5929 } 5930} 5931 5932MachineBasicBlock *ARMTargetLowering:: 5933EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { 5934 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5935 DebugLoc dl = MI->getDebugLoc(); 5936 MachineFunction *MF = MBB->getParent(); 5937 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5938 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5939 MachineFrameInfo *MFI = MF->getFrameInfo(); 5940 int FI = MFI->getFunctionContextIndex(); 5941 5942 const TargetRegisterClass *TRC = Subtarget->isThumb() ? 5943 (const TargetRegisterClass*)&ARM::tGPRRegClass : 5944 (const TargetRegisterClass*)&ARM::GPRnopcRegClass; 5945 5946 // Get a mapping of the call site numbers to all of the landing pads they're 5947 // associated with. 5948 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad; 5949 unsigned MaxCSNum = 0; 5950 MachineModuleInfo &MMI = MF->getMMI(); 5951 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; 5952 ++BB) { 5953 if (!BB->isLandingPad()) continue; 5954 5955 // FIXME: We should assert that the EH_LABEL is the first MI in the landing 5956 // pad. 5957 for (MachineBasicBlock::iterator 5958 II = BB->begin(), IE = BB->end(); II != IE; ++II) { 5959 if (!II->isEHLabel()) continue; 5960 5961 MCSymbol *Sym = II->getOperand(0).getMCSymbol(); 5962 if (!MMI.hasCallSiteLandingPad(Sym)) continue; 5963 5964 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym); 5965 for (SmallVectorImpl<unsigned>::iterator 5966 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end(); 5967 CSI != CSE; ++CSI) { 5968 CallSiteNumToLPad[*CSI].push_back(BB); 5969 MaxCSNum = std::max(MaxCSNum, *CSI); 5970 } 5971 break; 5972 } 5973 } 5974 5975 // Get an ordered list of the machine basic blocks for the jump table. 5976 std::vector<MachineBasicBlock*> LPadList; 5977 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs; 5978 LPadList.reserve(CallSiteNumToLPad.size()); 5979 for (unsigned I = 1; I <= MaxCSNum; ++I) { 5980 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I]; 5981 for (SmallVectorImpl<MachineBasicBlock*>::iterator 5982 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) { 5983 LPadList.push_back(*II); 5984 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end()); 5985 } 5986 } 5987 5988 assert(!LPadList.empty() && 5989 "No landing pad destinations for the dispatch jump table!"); 5990 5991 // Create the jump table and associated information. 5992 MachineJumpTableInfo *JTI = 5993 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline); 5994 unsigned MJTI = JTI->createJumpTableIndex(LPadList); 5995 unsigned UId = AFI->createJumpTableUId(); 5996 5997 // Create the MBBs for the dispatch code. 5998 5999 // Shove the dispatch's address into the return slot in the function context. 6000 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock(); 6001 DispatchBB->setIsLandingPad(); 6002 6003 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); 6004 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP)); 6005 DispatchBB->addSuccessor(TrapBB); 6006 6007 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); 6008 DispatchBB->addSuccessor(DispContBB); 6009 6010 // Insert and MBBs. 6011 MF->insert(MF->end(), DispatchBB); 6012 MF->insert(MF->end(), DispContBB); 6013 MF->insert(MF->end(), TrapBB); 6014 6015 // Insert code into the entry block that creates and registers the function 6016 // context. 6017 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI); 6018 6019 MachineMemOperand *FIMMOLd = 6020 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 6021 MachineMemOperand::MOLoad | 6022 MachineMemOperand::MOVolatile, 4, 4); 6023 6024 if (AFI->isThumb1OnlyFunction()) 6025 BuildMI(DispatchBB, dl, TII->get(ARM::tInt_eh_sjlj_dispatchsetup)); 6026 else if (!Subtarget->hasVFP2()) 6027 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup_nofp)); 6028 else 6029 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup)); 6030 6031 unsigned NumLPads = LPadList.size(); 6032 if (Subtarget->isThumb2()) { 6033 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6034 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1) 6035 .addFrameIndex(FI) 6036 .addImm(4) 6037 .addMemOperand(FIMMOLd)); 6038 6039 if (NumLPads < 256) { 6040 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri)) 6041 .addReg(NewVReg1) 6042 .addImm(LPadList.size())); 6043 } else { 6044 unsigned VReg1 = MRI->createVirtualRegister(TRC); 6045 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1) 6046 .addImm(NumLPads & 0xFFFF)); 6047 6048 unsigned VReg2 = VReg1; 6049 if ((NumLPads & 0xFFFF0000) != 0) { 6050 VReg2 = MRI->createVirtualRegister(TRC); 6051 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2) 6052 .addReg(VReg1) 6053 .addImm(NumLPads >> 16)); 6054 } 6055 6056 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr)) 6057 .addReg(NewVReg1) 6058 .addReg(VReg2)); 6059 } 6060 6061 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc)) 6062 .addMBB(TrapBB) 6063 .addImm(ARMCC::HI) 6064 .addReg(ARM::CPSR); 6065 6066 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 6067 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3) 6068 .addJumpTableIndex(MJTI) 6069 .addImm(UId)); 6070 6071 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 6072 AddDefaultCC( 6073 AddDefaultPred( 6074 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4) 6075 .addReg(NewVReg3, RegState::Kill) 6076 .addReg(NewVReg1) 6077 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 6078 6079 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT)) 6080 .addReg(NewVReg4, RegState::Kill) 6081 .addReg(NewVReg1) 6082 .addJumpTableIndex(MJTI) 6083 .addImm(UId); 6084 } else if (Subtarget->isThumb()) { 6085 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6086 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1) 6087 .addFrameIndex(FI) 6088 .addImm(1) 6089 .addMemOperand(FIMMOLd)); 6090 6091 if (NumLPads < 256) { 6092 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8)) 6093 .addReg(NewVReg1) 6094 .addImm(NumLPads)); 6095 } else { 6096 MachineConstantPool *ConstantPool = MF->getConstantPool(); 6097 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext()); 6098 const Constant *C = ConstantInt::get(Int32Ty, NumLPads); 6099 6100 // MachineConstantPool wants an explicit alignment. 6101 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty); 6102 if (Align == 0) 6103 Align = getTargetData()->getTypeAllocSize(C->getType()); 6104 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align); 6105 6106 unsigned VReg1 = MRI->createVirtualRegister(TRC); 6107 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci)) 6108 .addReg(VReg1, RegState::Define) 6109 .addConstantPoolIndex(Idx)); 6110 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr)) 6111 .addReg(NewVReg1) 6112 .addReg(VReg1)); 6113 } 6114 6115 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc)) 6116 .addMBB(TrapBB) 6117 .addImm(ARMCC::HI) 6118 .addReg(ARM::CPSR); 6119 6120 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 6121 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2) 6122 .addReg(ARM::CPSR, RegState::Define) 6123 .addReg(NewVReg1) 6124 .addImm(2)); 6125 6126 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 6127 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3) 6128 .addJumpTableIndex(MJTI) 6129 .addImm(UId)); 6130 6131 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 6132 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4) 6133 .addReg(ARM::CPSR, RegState::Define) 6134 .addReg(NewVReg2, RegState::Kill) 6135 .addReg(NewVReg3)); 6136 6137 MachineMemOperand *JTMMOLd = 6138 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 6139 MachineMemOperand::MOLoad, 4, 4); 6140 6141 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 6142 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5) 6143 .addReg(NewVReg4, RegState::Kill) 6144 .addImm(0) 6145 .addMemOperand(JTMMOLd)); 6146 6147 unsigned NewVReg6 = MRI->createVirtualRegister(TRC); 6148 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6) 6149 .addReg(ARM::CPSR, RegState::Define) 6150 .addReg(NewVReg5, RegState::Kill) 6151 .addReg(NewVReg3)); 6152 6153 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr)) 6154 .addReg(NewVReg6, RegState::Kill) 6155 .addJumpTableIndex(MJTI) 6156 .addImm(UId); 6157 } else { 6158 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 6159 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1) 6160 .addFrameIndex(FI) 6161 .addImm(4) 6162 .addMemOperand(FIMMOLd)); 6163 6164 if (NumLPads < 256) { 6165 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) 6166 .addReg(NewVReg1) 6167 .addImm(NumLPads)); 6168 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) { 6169 unsigned VReg1 = MRI->createVirtualRegister(TRC); 6170 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) 6171 .addImm(NumLPads & 0xFFFF)); 6172 6173 unsigned VReg2 = VReg1; 6174 if ((NumLPads & 0xFFFF0000) != 0) { 6175 VReg2 = MRI->createVirtualRegister(TRC); 6176 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2) 6177 .addReg(VReg1) 6178 .addImm(NumLPads >> 16)); 6179 } 6180 6181 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) 6182 .addReg(NewVReg1) 6183 .addReg(VReg2)); 6184 } else { 6185 MachineConstantPool *ConstantPool = MF->getConstantPool(); 6186 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext()); 6187 const Constant *C = ConstantInt::get(Int32Ty, NumLPads); 6188 6189 // MachineConstantPool wants an explicit alignment. 6190 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty); 6191 if (Align == 0) 6192 Align = getTargetData()->getTypeAllocSize(C->getType()); 6193 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align); 6194 6195 unsigned VReg1 = MRI->createVirtualRegister(TRC); 6196 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp)) 6197 .addReg(VReg1, RegState::Define) 6198 .addConstantPoolIndex(Idx) 6199 .addImm(0)); 6200 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) 6201 .addReg(NewVReg1) 6202 .addReg(VReg1, RegState::Kill)); 6203 } 6204 6205 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) 6206 .addMBB(TrapBB) 6207 .addImm(ARMCC::HI) 6208 .addReg(ARM::CPSR); 6209 6210 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 6211 AddDefaultCC( 6212 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3) 6213 .addReg(NewVReg1) 6214 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 6215 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 6216 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4) 6217 .addJumpTableIndex(MJTI) 6218 .addImm(UId)); 6219 6220 MachineMemOperand *JTMMOLd = 6221 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 6222 MachineMemOperand::MOLoad, 4, 4); 6223 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 6224 AddDefaultPred( 6225 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5) 6226 .addReg(NewVReg3, RegState::Kill) 6227 .addReg(NewVReg4) 6228 .addImm(0) 6229 .addMemOperand(JTMMOLd)); 6230 6231 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd)) 6232 .addReg(NewVReg5, RegState::Kill) 6233 .addReg(NewVReg4) 6234 .addJumpTableIndex(MJTI) 6235 .addImm(UId); 6236 } 6237 6238 // Add the jump table entries as successors to the MBB. 6239 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs; 6240 for (std::vector<MachineBasicBlock*>::iterator 6241 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) { 6242 MachineBasicBlock *CurMBB = *I; 6243 if (SeenMBBs.insert(CurMBB)) 6244 DispContBB->addSuccessor(CurMBB); 6245 } 6246 6247 // N.B. the order the invoke BBs are processed in doesn't matter here. 6248 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); 6249 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 6250 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF); 6251 SmallVector<MachineBasicBlock*, 64> MBBLPads; 6252 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator 6253 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) { 6254 MachineBasicBlock *BB = *I; 6255 6256 // Remove the landing pad successor from the invoke block and replace it 6257 // with the new dispatch block. 6258 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(), 6259 BB->succ_end()); 6260 while (!Successors.empty()) { 6261 MachineBasicBlock *SMBB = Successors.pop_back_val(); 6262 if (SMBB->isLandingPad()) { 6263 BB->removeSuccessor(SMBB); 6264 MBBLPads.push_back(SMBB); 6265 } 6266 } 6267 6268 BB->addSuccessor(DispatchBB); 6269 6270 // Find the invoke call and mark all of the callee-saved registers as 6271 // 'implicit defined' so that they're spilled. This prevents code from 6272 // moving instructions to before the EH block, where they will never be 6273 // executed. 6274 for (MachineBasicBlock::reverse_iterator 6275 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) { 6276 if (!II->isCall()) continue; 6277 6278 DenseMap<unsigned, bool> DefRegs; 6279 for (MachineInstr::mop_iterator 6280 OI = II->operands_begin(), OE = II->operands_end(); 6281 OI != OE; ++OI) { 6282 if (!OI->isReg()) continue; 6283 DefRegs[OI->getReg()] = true; 6284 } 6285 6286 MachineInstrBuilder MIB(&*II); 6287 6288 for (unsigned i = 0; SavedRegs[i] != 0; ++i) { 6289 unsigned Reg = SavedRegs[i]; 6290 if (Subtarget->isThumb2() && 6291 !ARM::tGPRRegClass.contains(Reg) && 6292 !ARM::hGPRRegClass.contains(Reg)) 6293 continue; 6294 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg)) 6295 continue; 6296 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg)) 6297 continue; 6298 if (!DefRegs[Reg]) 6299 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); 6300 } 6301 6302 break; 6303 } 6304 } 6305 6306 // Mark all former landing pads as non-landing pads. The dispatch is the only 6307 // landing pad now. 6308 for (SmallVectorImpl<MachineBasicBlock*>::iterator 6309 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I) 6310 (*I)->setIsLandingPad(false); 6311 6312 // The instruction is gone now. 6313 MI->eraseFromParent(); 6314 6315 return MBB; 6316} 6317 6318static 6319MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { 6320 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), 6321 E = MBB->succ_end(); I != E; ++I) 6322 if (*I != Succ) 6323 return *I; 6324 llvm_unreachable("Expecting a BB with two successors!"); 6325} 6326 6327MachineBasicBlock *ARMTargetLowering:: 6328EmitStructByval(MachineInstr *MI, MachineBasicBlock *BB) const { 6329 // This pseudo instruction has 3 operands: dst, src, size 6330 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold(). 6331 // Otherwise, we will generate unrolled scalar copies. 6332 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6333 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6334 MachineFunction::iterator It = BB; 6335 ++It; 6336 6337 unsigned dest = MI->getOperand(0).getReg(); 6338 unsigned src = MI->getOperand(1).getReg(); 6339 unsigned SizeVal = MI->getOperand(2).getImm(); 6340 unsigned Align = MI->getOperand(3).getImm(); 6341 DebugLoc dl = MI->getDebugLoc(); 6342 6343 bool isThumb2 = Subtarget->isThumb2(); 6344 MachineFunction *MF = BB->getParent(); 6345 MachineRegisterInfo &MRI = MF->getRegInfo(); 6346 unsigned ldrOpc, strOpc, UnitSize = 0; 6347 6348 const TargetRegisterClass *TRC = isThumb2 ? 6349 (const TargetRegisterClass*)&ARM::tGPRRegClass : 6350 (const TargetRegisterClass*)&ARM::GPRRegClass; 6351 const TargetRegisterClass *TRC_Vec = 0; 6352 6353 if (Align & 1) { 6354 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM; 6355 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM; 6356 UnitSize = 1; 6357 } else if (Align & 2) { 6358 ldrOpc = isThumb2 ? ARM::t2LDRH_POST : ARM::LDRH_POST; 6359 strOpc = isThumb2 ? ARM::t2STRH_POST : ARM::STRH_POST; 6360 UnitSize = 2; 6361 } else { 6362 // Check whether we can use NEON instructions. 6363 if (!MF->getFunction()->getFnAttributes().hasNoImplicitFloatAttr() && 6364 Subtarget->hasNEON()) { 6365 if ((Align % 16 == 0) && SizeVal >= 16) { 6366 ldrOpc = ARM::VLD1q32wb_fixed; 6367 strOpc = ARM::VST1q32wb_fixed; 6368 UnitSize = 16; 6369 TRC_Vec = (const TargetRegisterClass*)&ARM::DPairRegClass; 6370 } 6371 else if ((Align % 8 == 0) && SizeVal >= 8) { 6372 ldrOpc = ARM::VLD1d32wb_fixed; 6373 strOpc = ARM::VST1d32wb_fixed; 6374 UnitSize = 8; 6375 TRC_Vec = (const TargetRegisterClass*)&ARM::DPRRegClass; 6376 } 6377 } 6378 // Can't use NEON instructions. 6379 if (UnitSize == 0) { 6380 ldrOpc = isThumb2 ? ARM::t2LDR_POST : ARM::LDR_POST_IMM; 6381 strOpc = isThumb2 ? ARM::t2STR_POST : ARM::STR_POST_IMM; 6382 UnitSize = 4; 6383 } 6384 } 6385 6386 unsigned BytesLeft = SizeVal % UnitSize; 6387 unsigned LoopSize = SizeVal - BytesLeft; 6388 6389 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) { 6390 // Use LDR and STR to copy. 6391 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize) 6392 // [destOut] = STR_POST(scratch, destIn, UnitSize) 6393 unsigned srcIn = src; 6394 unsigned destIn = dest; 6395 for (unsigned i = 0; i < LoopSize; i+=UnitSize) { 6396 unsigned scratch = MRI.createVirtualRegister(UnitSize >= 8 ? TRC_Vec:TRC); 6397 unsigned srcOut = MRI.createVirtualRegister(TRC); 6398 unsigned destOut = MRI.createVirtualRegister(TRC); 6399 if (UnitSize >= 8) { 6400 AddDefaultPred(BuildMI(*BB, MI, dl, 6401 TII->get(ldrOpc), scratch) 6402 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(0)); 6403 6404 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut) 6405 .addReg(destIn).addImm(0).addReg(scratch)); 6406 } else if (isThumb2) { 6407 AddDefaultPred(BuildMI(*BB, MI, dl, 6408 TII->get(ldrOpc), scratch) 6409 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(UnitSize)); 6410 6411 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut) 6412 .addReg(scratch).addReg(destIn) 6413 .addImm(UnitSize)); 6414 } else { 6415 AddDefaultPred(BuildMI(*BB, MI, dl, 6416 TII->get(ldrOpc), scratch) 6417 .addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0) 6418 .addImm(UnitSize)); 6419 6420 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut) 6421 .addReg(scratch).addReg(destIn) 6422 .addReg(0).addImm(UnitSize)); 6423 } 6424 srcIn = srcOut; 6425 destIn = destOut; 6426 } 6427 6428 // Handle the leftover bytes with LDRB and STRB. 6429 // [scratch, srcOut] = LDRB_POST(srcIn, 1) 6430 // [destOut] = STRB_POST(scratch, destIn, 1) 6431 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM; 6432 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM; 6433 for (unsigned i = 0; i < BytesLeft; i++) { 6434 unsigned scratch = MRI.createVirtualRegister(TRC); 6435 unsigned srcOut = MRI.createVirtualRegister(TRC); 6436 unsigned destOut = MRI.createVirtualRegister(TRC); 6437 if (isThumb2) { 6438 AddDefaultPred(BuildMI(*BB, MI, dl, 6439 TII->get(ldrOpc),scratch) 6440 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1)); 6441 6442 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut) 6443 .addReg(scratch).addReg(destIn) 6444 .addReg(0).addImm(1)); 6445 } else { 6446 AddDefaultPred(BuildMI(*BB, MI, dl, 6447 TII->get(ldrOpc),scratch) 6448 .addReg(srcOut, RegState::Define).addReg(srcIn) 6449 .addReg(0).addImm(1)); 6450 6451 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut) 6452 .addReg(scratch).addReg(destIn) 6453 .addReg(0).addImm(1)); 6454 } 6455 srcIn = srcOut; 6456 destIn = destOut; 6457 } 6458 MI->eraseFromParent(); // The instruction is gone now. 6459 return BB; 6460 } 6461 6462 // Expand the pseudo op to a loop. 6463 // thisMBB: 6464 // ... 6465 // movw varEnd, # --> with thumb2 6466 // movt varEnd, # 6467 // ldrcp varEnd, idx --> without thumb2 6468 // fallthrough --> loopMBB 6469 // loopMBB: 6470 // PHI varPhi, varEnd, varLoop 6471 // PHI srcPhi, src, srcLoop 6472 // PHI destPhi, dst, destLoop 6473 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize) 6474 // [destLoop] = STR_POST(scratch, destPhi, UnitSize) 6475 // subs varLoop, varPhi, #UnitSize 6476 // bne loopMBB 6477 // fallthrough --> exitMBB 6478 // exitMBB: 6479 // epilogue to handle left-over bytes 6480 // [scratch, srcOut] = LDRB_POST(srcLoop, 1) 6481 // [destOut] = STRB_POST(scratch, destLoop, 1) 6482 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 6483 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 6484 MF->insert(It, loopMBB); 6485 MF->insert(It, exitMBB); 6486 6487 // Transfer the remainder of BB and its successor edges to exitMBB. 6488 exitMBB->splice(exitMBB->begin(), BB, 6489 llvm::next(MachineBasicBlock::iterator(MI)), 6490 BB->end()); 6491 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6492 6493 // Load an immediate to varEnd. 6494 unsigned varEnd = MRI.createVirtualRegister(TRC); 6495 if (isThumb2) { 6496 unsigned VReg1 = varEnd; 6497 if ((LoopSize & 0xFFFF0000) != 0) 6498 VReg1 = MRI.createVirtualRegister(TRC); 6499 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), VReg1) 6500 .addImm(LoopSize & 0xFFFF)); 6501 6502 if ((LoopSize & 0xFFFF0000) != 0) 6503 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd) 6504 .addReg(VReg1) 6505 .addImm(LoopSize >> 16)); 6506 } else { 6507 MachineConstantPool *ConstantPool = MF->getConstantPool(); 6508 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext()); 6509 const Constant *C = ConstantInt::get(Int32Ty, LoopSize); 6510 6511 // MachineConstantPool wants an explicit alignment. 6512 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty); 6513 if (Align == 0) 6514 Align = getTargetData()->getTypeAllocSize(C->getType()); 6515 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align); 6516 6517 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDRcp)) 6518 .addReg(varEnd, RegState::Define) 6519 .addConstantPoolIndex(Idx) 6520 .addImm(0)); 6521 } 6522 BB->addSuccessor(loopMBB); 6523 6524 // Generate the loop body: 6525 // varPhi = PHI(varLoop, varEnd) 6526 // srcPhi = PHI(srcLoop, src) 6527 // destPhi = PHI(destLoop, dst) 6528 MachineBasicBlock *entryBB = BB; 6529 BB = loopMBB; 6530 unsigned varLoop = MRI.createVirtualRegister(TRC); 6531 unsigned varPhi = MRI.createVirtualRegister(TRC); 6532 unsigned srcLoop = MRI.createVirtualRegister(TRC); 6533 unsigned srcPhi = MRI.createVirtualRegister(TRC); 6534 unsigned destLoop = MRI.createVirtualRegister(TRC); 6535 unsigned destPhi = MRI.createVirtualRegister(TRC); 6536 6537 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi) 6538 .addReg(varLoop).addMBB(loopMBB) 6539 .addReg(varEnd).addMBB(entryBB); 6540 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi) 6541 .addReg(srcLoop).addMBB(loopMBB) 6542 .addReg(src).addMBB(entryBB); 6543 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi) 6544 .addReg(destLoop).addMBB(loopMBB) 6545 .addReg(dest).addMBB(entryBB); 6546 6547 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize) 6548 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz) 6549 unsigned scratch = MRI.createVirtualRegister(UnitSize >= 8 ? TRC_Vec:TRC); 6550 if (UnitSize >= 8) { 6551 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch) 6552 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(0)); 6553 6554 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop) 6555 .addReg(destPhi).addImm(0).addReg(scratch)); 6556 } else if (isThumb2) { 6557 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch) 6558 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(UnitSize)); 6559 6560 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop) 6561 .addReg(scratch).addReg(destPhi) 6562 .addImm(UnitSize)); 6563 } else { 6564 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch) 6565 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addReg(0) 6566 .addImm(UnitSize)); 6567 6568 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop) 6569 .addReg(scratch).addReg(destPhi) 6570 .addReg(0).addImm(UnitSize)); 6571 } 6572 6573 // Decrement loop variable by UnitSize. 6574 MachineInstrBuilder MIB = BuildMI(BB, dl, 6575 TII->get(isThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop); 6576 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize))); 6577 MIB->getOperand(5).setReg(ARM::CPSR); 6578 MIB->getOperand(5).setIsDef(true); 6579 6580 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 6581 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 6582 6583 // loopMBB can loop back to loopMBB or fall through to exitMBB. 6584 BB->addSuccessor(loopMBB); 6585 BB->addSuccessor(exitMBB); 6586 6587 // Add epilogue to handle BytesLeft. 6588 BB = exitMBB; 6589 MachineInstr *StartOfExit = exitMBB->begin(); 6590 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM; 6591 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM; 6592 6593 // [scratch, srcOut] = LDRB_POST(srcLoop, 1) 6594 // [destOut] = STRB_POST(scratch, destLoop, 1) 6595 unsigned srcIn = srcLoop; 6596 unsigned destIn = destLoop; 6597 for (unsigned i = 0; i < BytesLeft; i++) { 6598 unsigned scratch = MRI.createVirtualRegister(TRC); 6599 unsigned srcOut = MRI.createVirtualRegister(TRC); 6600 unsigned destOut = MRI.createVirtualRegister(TRC); 6601 if (isThumb2) { 6602 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, 6603 TII->get(ldrOpc),scratch) 6604 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1)); 6605 6606 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut) 6607 .addReg(scratch).addReg(destIn) 6608 .addImm(1)); 6609 } else { 6610 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, 6611 TII->get(ldrOpc),scratch) 6612 .addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0).addImm(1)); 6613 6614 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut) 6615 .addReg(scratch).addReg(destIn) 6616 .addReg(0).addImm(1)); 6617 } 6618 srcIn = srcOut; 6619 destIn = destOut; 6620 } 6621 6622 MI->eraseFromParent(); // The instruction is gone now. 6623 return BB; 6624} 6625 6626MachineBasicBlock * 6627ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 6628 MachineBasicBlock *BB) const { 6629 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6630 DebugLoc dl = MI->getDebugLoc(); 6631 bool isThumb2 = Subtarget->isThumb2(); 6632 switch (MI->getOpcode()) { 6633 default: { 6634 MI->dump(); 6635 llvm_unreachable("Unexpected instr type to insert"); 6636 } 6637 // The Thumb2 pre-indexed stores have the same MI operands, they just 6638 // define them differently in the .td files from the isel patterns, so 6639 // they need pseudos. 6640 case ARM::t2STR_preidx: 6641 MI->setDesc(TII->get(ARM::t2STR_PRE)); 6642 return BB; 6643 case ARM::t2STRB_preidx: 6644 MI->setDesc(TII->get(ARM::t2STRB_PRE)); 6645 return BB; 6646 case ARM::t2STRH_preidx: 6647 MI->setDesc(TII->get(ARM::t2STRH_PRE)); 6648 return BB; 6649 6650 case ARM::STRi_preidx: 6651 case ARM::STRBi_preidx: { 6652 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? 6653 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM; 6654 // Decode the offset. 6655 unsigned Offset = MI->getOperand(4).getImm(); 6656 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; 6657 Offset = ARM_AM::getAM2Offset(Offset); 6658 if (isSub) 6659 Offset = -Offset; 6660 6661 MachineMemOperand *MMO = *MI->memoperands_begin(); 6662 BuildMI(*BB, MI, dl, TII->get(NewOpc)) 6663 .addOperand(MI->getOperand(0)) // Rn_wb 6664 .addOperand(MI->getOperand(1)) // Rt 6665 .addOperand(MI->getOperand(2)) // Rn 6666 .addImm(Offset) // offset (skip GPR==zero_reg) 6667 .addOperand(MI->getOperand(5)) // pred 6668 .addOperand(MI->getOperand(6)) 6669 .addMemOperand(MMO); 6670 MI->eraseFromParent(); 6671 return BB; 6672 } 6673 case ARM::STRr_preidx: 6674 case ARM::STRBr_preidx: 6675 case ARM::STRH_preidx: { 6676 unsigned NewOpc; 6677 switch (MI->getOpcode()) { 6678 default: llvm_unreachable("unexpected opcode!"); 6679 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; 6680 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; 6681 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; 6682 } 6683 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); 6684 for (unsigned i = 0; i < MI->getNumOperands(); ++i) 6685 MIB.addOperand(MI->getOperand(i)); 6686 MI->eraseFromParent(); 6687 return BB; 6688 } 6689 case ARM::ATOMIC_LOAD_ADD_I8: 6690 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6691 case ARM::ATOMIC_LOAD_ADD_I16: 6692 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6693 case ARM::ATOMIC_LOAD_ADD_I32: 6694 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6695 6696 case ARM::ATOMIC_LOAD_AND_I8: 6697 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6698 case ARM::ATOMIC_LOAD_AND_I16: 6699 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6700 case ARM::ATOMIC_LOAD_AND_I32: 6701 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6702 6703 case ARM::ATOMIC_LOAD_OR_I8: 6704 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6705 case ARM::ATOMIC_LOAD_OR_I16: 6706 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6707 case ARM::ATOMIC_LOAD_OR_I32: 6708 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6709 6710 case ARM::ATOMIC_LOAD_XOR_I8: 6711 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6712 case ARM::ATOMIC_LOAD_XOR_I16: 6713 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6714 case ARM::ATOMIC_LOAD_XOR_I32: 6715 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6716 6717 case ARM::ATOMIC_LOAD_NAND_I8: 6718 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6719 case ARM::ATOMIC_LOAD_NAND_I16: 6720 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6721 case ARM::ATOMIC_LOAD_NAND_I32: 6722 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6723 6724 case ARM::ATOMIC_LOAD_SUB_I8: 6725 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6726 case ARM::ATOMIC_LOAD_SUB_I16: 6727 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6728 case ARM::ATOMIC_LOAD_SUB_I32: 6729 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6730 6731 case ARM::ATOMIC_LOAD_MIN_I8: 6732 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT); 6733 case ARM::ATOMIC_LOAD_MIN_I16: 6734 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT); 6735 case ARM::ATOMIC_LOAD_MIN_I32: 6736 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT); 6737 6738 case ARM::ATOMIC_LOAD_MAX_I8: 6739 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT); 6740 case ARM::ATOMIC_LOAD_MAX_I16: 6741 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT); 6742 case ARM::ATOMIC_LOAD_MAX_I32: 6743 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT); 6744 6745 case ARM::ATOMIC_LOAD_UMIN_I8: 6746 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO); 6747 case ARM::ATOMIC_LOAD_UMIN_I16: 6748 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO); 6749 case ARM::ATOMIC_LOAD_UMIN_I32: 6750 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO); 6751 6752 case ARM::ATOMIC_LOAD_UMAX_I8: 6753 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI); 6754 case ARM::ATOMIC_LOAD_UMAX_I16: 6755 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI); 6756 case ARM::ATOMIC_LOAD_UMAX_I32: 6757 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI); 6758 6759 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 6760 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 6761 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 6762 6763 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 6764 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 6765 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 6766 6767 6768 case ARM::ATOMADD6432: 6769 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, 6770 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, 6771 /*NeedsCarry*/ true); 6772 case ARM::ATOMSUB6432: 6773 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6774 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6775 /*NeedsCarry*/ true); 6776 case ARM::ATOMOR6432: 6777 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, 6778 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6779 case ARM::ATOMXOR6432: 6780 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, 6781 isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6782 case ARM::ATOMAND6432: 6783 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, 6784 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6785 case ARM::ATOMSWAP6432: 6786 return EmitAtomicBinary64(MI, BB, 0, 0, false); 6787 case ARM::ATOMCMPXCHG6432: 6788 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6789 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6790 /*NeedsCarry*/ false, /*IsCmpxchg*/true); 6791 6792 case ARM::tMOVCCr_pseudo: { 6793 // To "insert" a SELECT_CC instruction, we actually have to insert the 6794 // diamond control-flow pattern. The incoming instruction knows the 6795 // destination vreg to set, the condition code register to branch on, the 6796 // true/false values to select between, and a branch opcode to use. 6797 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6798 MachineFunction::iterator It = BB; 6799 ++It; 6800 6801 // thisMBB: 6802 // ... 6803 // TrueVal = ... 6804 // cmpTY ccX, r1, r2 6805 // bCC copy1MBB 6806 // fallthrough --> copy0MBB 6807 MachineBasicBlock *thisMBB = BB; 6808 MachineFunction *F = BB->getParent(); 6809 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6810 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6811 F->insert(It, copy0MBB); 6812 F->insert(It, sinkMBB); 6813 6814 // Transfer the remainder of BB and its successor edges to sinkMBB. 6815 sinkMBB->splice(sinkMBB->begin(), BB, 6816 llvm::next(MachineBasicBlock::iterator(MI)), 6817 BB->end()); 6818 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 6819 6820 BB->addSuccessor(copy0MBB); 6821 BB->addSuccessor(sinkMBB); 6822 6823 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 6824 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 6825 6826 // copy0MBB: 6827 // %FalseValue = ... 6828 // # fallthrough to sinkMBB 6829 BB = copy0MBB; 6830 6831 // Update machine-CFG edges 6832 BB->addSuccessor(sinkMBB); 6833 6834 // sinkMBB: 6835 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6836 // ... 6837 BB = sinkMBB; 6838 BuildMI(*BB, BB->begin(), dl, 6839 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 6840 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 6841 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6842 6843 MI->eraseFromParent(); // The pseudo instruction is gone now. 6844 return BB; 6845 } 6846 6847 case ARM::BCCi64: 6848 case ARM::BCCZi64: { 6849 // If there is an unconditional branch to the other successor, remove it. 6850 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 6851 6852 // Compare both parts that make up the double comparison separately for 6853 // equality. 6854 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; 6855 6856 unsigned LHS1 = MI->getOperand(1).getReg(); 6857 unsigned LHS2 = MI->getOperand(2).getReg(); 6858 if (RHSisZero) { 6859 AddDefaultPred(BuildMI(BB, dl, 6860 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6861 .addReg(LHS1).addImm(0)); 6862 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6863 .addReg(LHS2).addImm(0) 6864 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6865 } else { 6866 unsigned RHS1 = MI->getOperand(3).getReg(); 6867 unsigned RHS2 = MI->getOperand(4).getReg(); 6868 AddDefaultPred(BuildMI(BB, dl, 6869 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6870 .addReg(LHS1).addReg(RHS1)); 6871 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6872 .addReg(LHS2).addReg(RHS2) 6873 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6874 } 6875 6876 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); 6877 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); 6878 if (MI->getOperand(0).getImm() == ARMCC::NE) 6879 std::swap(destMBB, exitMBB); 6880 6881 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 6882 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 6883 if (isThumb2) 6884 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB)); 6885 else 6886 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); 6887 6888 MI->eraseFromParent(); // The pseudo instruction is gone now. 6889 return BB; 6890 } 6891 6892 case ARM::Int_eh_sjlj_setjmp: 6893 case ARM::Int_eh_sjlj_setjmp_nofp: 6894 case ARM::tInt_eh_sjlj_setjmp: 6895 case ARM::t2Int_eh_sjlj_setjmp: 6896 case ARM::t2Int_eh_sjlj_setjmp_nofp: 6897 EmitSjLjDispatchBlock(MI, BB); 6898 return BB; 6899 6900 case ARM::ABS: 6901 case ARM::t2ABS: { 6902 // To insert an ABS instruction, we have to insert the 6903 // diamond control-flow pattern. The incoming instruction knows the 6904 // source vreg to test against 0, the destination vreg to set, 6905 // the condition code register to branch on, the 6906 // true/false values to select between, and a branch opcode to use. 6907 // It transforms 6908 // V1 = ABS V0 6909 // into 6910 // V2 = MOVS V0 6911 // BCC (branch to SinkBB if V0 >= 0) 6912 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0) 6913 // SinkBB: V1 = PHI(V2, V3) 6914 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6915 MachineFunction::iterator BBI = BB; 6916 ++BBI; 6917 MachineFunction *Fn = BB->getParent(); 6918 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6919 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6920 Fn->insert(BBI, RSBBB); 6921 Fn->insert(BBI, SinkBB); 6922 6923 unsigned int ABSSrcReg = MI->getOperand(1).getReg(); 6924 unsigned int ABSDstReg = MI->getOperand(0).getReg(); 6925 bool isThumb2 = Subtarget->isThumb2(); 6926 MachineRegisterInfo &MRI = Fn->getRegInfo(); 6927 // In Thumb mode S must not be specified if source register is the SP or 6928 // PC and if destination register is the SP, so restrict register class 6929 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ? 6930 (const TargetRegisterClass*)&ARM::rGPRRegClass : 6931 (const TargetRegisterClass*)&ARM::GPRRegClass); 6932 6933 // Transfer the remainder of BB and its successor edges to sinkMBB. 6934 SinkBB->splice(SinkBB->begin(), BB, 6935 llvm::next(MachineBasicBlock::iterator(MI)), 6936 BB->end()); 6937 SinkBB->transferSuccessorsAndUpdatePHIs(BB); 6938 6939 BB->addSuccessor(RSBBB); 6940 BB->addSuccessor(SinkBB); 6941 6942 // fall through to SinkMBB 6943 RSBBB->addSuccessor(SinkBB); 6944 6945 // insert a cmp at the end of BB 6946 AddDefaultPred(BuildMI(BB, dl, 6947 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6948 .addReg(ABSSrcReg).addImm(0)); 6949 6950 // insert a bcc with opposite CC to ARMCC::MI at the end of BB 6951 BuildMI(BB, dl, 6952 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB) 6953 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR); 6954 6955 // insert rsbri in RSBBB 6956 // Note: BCC and rsbri will be converted into predicated rsbmi 6957 // by if-conversion pass 6958 BuildMI(*RSBBB, RSBBB->begin(), dl, 6959 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) 6960 .addReg(ABSSrcReg, RegState::Kill) 6961 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 6962 6963 // insert PHI in SinkBB, 6964 // reuse ABSDstReg to not change uses of ABS instruction 6965 BuildMI(*SinkBB, SinkBB->begin(), dl, 6966 TII->get(ARM::PHI), ABSDstReg) 6967 .addReg(NewRsbDstReg).addMBB(RSBBB) 6968 .addReg(ABSSrcReg).addMBB(BB); 6969 6970 // remove ABS instruction 6971 MI->eraseFromParent(); 6972 6973 // return last added BB 6974 return SinkBB; 6975 } 6976 case ARM::COPY_STRUCT_BYVAL_I32: 6977 ++NumLoopByVals; 6978 return EmitStructByval(MI, BB); 6979 } 6980} 6981 6982void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 6983 SDNode *Node) const { 6984 if (!MI->hasPostISelHook()) { 6985 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 6986 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"); 6987 return; 6988 } 6989 6990 const MCInstrDesc *MCID = &MI->getDesc(); 6991 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB, 6992 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional 6993 // operand is still set to noreg. If needed, set the optional operand's 6994 // register to CPSR, and remove the redundant implicit def. 6995 // 6996 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>). 6997 6998 // Rename pseudo opcodes. 6999 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); 7000 if (NewOpc) { 7001 const ARMBaseInstrInfo *TII = 7002 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo()); 7003 MCID = &TII->get(NewOpc); 7004 7005 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 && 7006 "converted opcode should be the same except for cc_out"); 7007 7008 MI->setDesc(*MCID); 7009 7010 // Add the optional cc_out operand 7011 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true)); 7012 } 7013 unsigned ccOutIdx = MCID->getNumOperands() - 1; 7014 7015 // Any ARM instruction that sets the 's' bit should specify an optional 7016 // "cc_out" operand in the last operand position. 7017 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { 7018 assert(!NewOpc && "Optional cc_out operand required"); 7019 return; 7020 } 7021 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it 7022 // since we already have an optional CPSR def. 7023 bool definesCPSR = false; 7024 bool deadCPSR = false; 7025 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands(); 7026 i != e; ++i) { 7027 const MachineOperand &MO = MI->getOperand(i); 7028 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { 7029 definesCPSR = true; 7030 if (MO.isDead()) 7031 deadCPSR = true; 7032 MI->RemoveOperand(i); 7033 break; 7034 } 7035 } 7036 if (!definesCPSR) { 7037 assert(!NewOpc && "Optional cc_out operand required"); 7038 return; 7039 } 7040 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag"); 7041 if (deadCPSR) { 7042 assert(!MI->getOperand(ccOutIdx).getReg() && 7043 "expect uninitialized optional cc_out operand"); 7044 return; 7045 } 7046 7047 // If this instruction was defined with an optional CPSR def and its dag node 7048 // had a live implicit CPSR def, then activate the optional CPSR def. 7049 MachineOperand &MO = MI->getOperand(ccOutIdx); 7050 MO.setReg(ARM::CPSR); 7051 MO.setIsDef(true); 7052} 7053 7054//===----------------------------------------------------------------------===// 7055// ARM Optimization Hooks 7056//===----------------------------------------------------------------------===// 7057 7058// Helper function that checks if N is a null or all ones constant. 7059static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) { 7060 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 7061 if (!C) 7062 return false; 7063 return AllOnes ? C->isAllOnesValue() : C->isNullValue(); 7064} 7065 7066// Return true if N is conditionally 0 or all ones. 7067// Detects these expressions where cc is an i1 value: 7068// 7069// (select cc 0, y) [AllOnes=0] 7070// (select cc y, 0) [AllOnes=0] 7071// (zext cc) [AllOnes=0] 7072// (sext cc) [AllOnes=0/1] 7073// (select cc -1, y) [AllOnes=1] 7074// (select cc y, -1) [AllOnes=1] 7075// 7076// Invert is set when N is the null/all ones constant when CC is false. 7077// OtherOp is set to the alternative value of N. 7078static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, 7079 SDValue &CC, bool &Invert, 7080 SDValue &OtherOp, 7081 SelectionDAG &DAG) { 7082 switch (N->getOpcode()) { 7083 default: return false; 7084 case ISD::SELECT: { 7085 CC = N->getOperand(0); 7086 SDValue N1 = N->getOperand(1); 7087 SDValue N2 = N->getOperand(2); 7088 if (isZeroOrAllOnes(N1, AllOnes)) { 7089 Invert = false; 7090 OtherOp = N2; 7091 return true; 7092 } 7093 if (isZeroOrAllOnes(N2, AllOnes)) { 7094 Invert = true; 7095 OtherOp = N1; 7096 return true; 7097 } 7098 return false; 7099 } 7100 case ISD::ZERO_EXTEND: 7101 // (zext cc) can never be the all ones value. 7102 if (AllOnes) 7103 return false; 7104 // Fall through. 7105 case ISD::SIGN_EXTEND: { 7106 EVT VT = N->getValueType(0); 7107 CC = N->getOperand(0); 7108 if (CC.getValueType() != MVT::i1) 7109 return false; 7110 Invert = !AllOnes; 7111 if (AllOnes) 7112 // When looking for an AllOnes constant, N is an sext, and the 'other' 7113 // value is 0. 7114 OtherOp = DAG.getConstant(0, VT); 7115 else if (N->getOpcode() == ISD::ZERO_EXTEND) 7116 // When looking for a 0 constant, N can be zext or sext. 7117 OtherOp = DAG.getConstant(1, VT); 7118 else 7119 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 7120 return true; 7121 } 7122 } 7123} 7124 7125// Combine a constant select operand into its use: 7126// 7127// (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 7128// (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 7129// (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1] 7130// (or (select cc, 0, c), x) -> (select cc, x, (or, x, c)) 7131// (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c)) 7132// 7133// The transform is rejected if the select doesn't have a constant operand that 7134// is null, or all ones when AllOnes is set. 7135// 7136// Also recognize sext/zext from i1: 7137// 7138// (add (zext cc), x) -> (select cc (add x, 1), x) 7139// (add (sext cc), x) -> (select cc (add x, -1), x) 7140// 7141// These transformations eventually create predicated instructions. 7142// 7143// @param N The node to transform. 7144// @param Slct The N operand that is a select. 7145// @param OtherOp The other N operand (x above). 7146// @param DCI Context. 7147// @param AllOnes Require the select constant to be all ones instead of null. 7148// @returns The new node, or SDValue() on failure. 7149static 7150SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 7151 TargetLowering::DAGCombinerInfo &DCI, 7152 bool AllOnes = false) { 7153 SelectionDAG &DAG = DCI.DAG; 7154 EVT VT = N->getValueType(0); 7155 SDValue NonConstantVal; 7156 SDValue CCOp; 7157 bool SwapSelectOps; 7158 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, 7159 NonConstantVal, DAG)) 7160 return SDValue(); 7161 7162 // Slct is now know to be the desired identity constant when CC is true. 7163 SDValue TrueVal = OtherOp; 7164 SDValue FalseVal = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 7165 OtherOp, NonConstantVal); 7166 // Unless SwapSelectOps says CC should be false. 7167 if (SwapSelectOps) 7168 std::swap(TrueVal, FalseVal); 7169 7170 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 7171 CCOp, TrueVal, FalseVal); 7172} 7173 7174// Attempt combineSelectAndUse on each operand of a commutative operator N. 7175static 7176SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes, 7177 TargetLowering::DAGCombinerInfo &DCI) { 7178 SDValue N0 = N->getOperand(0); 7179 SDValue N1 = N->getOperand(1); 7180 if (N0.getNode()->hasOneUse()) { 7181 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes); 7182 if (Result.getNode()) 7183 return Result; 7184 } 7185 if (N1.getNode()->hasOneUse()) { 7186 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes); 7187 if (Result.getNode()) 7188 return Result; 7189 } 7190 return SDValue(); 7191} 7192 7193// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction 7194// (only after legalization). 7195static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, 7196 TargetLowering::DAGCombinerInfo &DCI, 7197 const ARMSubtarget *Subtarget) { 7198 7199 // Only perform optimization if after legalize, and if NEON is available. We 7200 // also expected both operands to be BUILD_VECTORs. 7201 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() 7202 || N0.getOpcode() != ISD::BUILD_VECTOR 7203 || N1.getOpcode() != ISD::BUILD_VECTOR) 7204 return SDValue(); 7205 7206 // Check output type since VPADDL operand elements can only be 8, 16, or 32. 7207 EVT VT = N->getValueType(0); 7208 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) 7209 return SDValue(); 7210 7211 // Check that the vector operands are of the right form. 7212 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR 7213 // operands, where N is the size of the formed vector. 7214 // Each EXTRACT_VECTOR should have the same input vector and odd or even 7215 // index such that we have a pair wise add pattern. 7216 7217 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing. 7218 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 7219 return SDValue(); 7220 SDValue Vec = N0->getOperand(0)->getOperand(0); 7221 SDNode *V = Vec.getNode(); 7222 unsigned nextIndex = 0; 7223 7224 // For each operands to the ADD which are BUILD_VECTORs, 7225 // check to see if each of their operands are an EXTRACT_VECTOR with 7226 // the same vector and appropriate index. 7227 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { 7228 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT 7229 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 7230 7231 SDValue ExtVec0 = N0->getOperand(i); 7232 SDValue ExtVec1 = N1->getOperand(i); 7233 7234 // First operand is the vector, verify its the same. 7235 if (V != ExtVec0->getOperand(0).getNode() || 7236 V != ExtVec1->getOperand(0).getNode()) 7237 return SDValue(); 7238 7239 // Second is the constant, verify its correct. 7240 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1)); 7241 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1)); 7242 7243 // For the constant, we want to see all the even or all the odd. 7244 if (!C0 || !C1 || C0->getZExtValue() != nextIndex 7245 || C1->getZExtValue() != nextIndex+1) 7246 return SDValue(); 7247 7248 // Increment index. 7249 nextIndex+=2; 7250 } else 7251 return SDValue(); 7252 } 7253 7254 // Create VPADDL node. 7255 SelectionDAG &DAG = DCI.DAG; 7256 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7257 7258 // Build operand list. 7259 SmallVector<SDValue, 8> Ops; 7260 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, 7261 TLI.getPointerTy())); 7262 7263 // Input is the vector. 7264 Ops.push_back(Vec); 7265 7266 // Get widened type and narrowed type. 7267 MVT widenType; 7268 unsigned numElem = VT.getVectorNumElements(); 7269 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 7270 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; 7271 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; 7272 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; 7273 default: 7274 llvm_unreachable("Invalid vector element type for padd optimization."); 7275 } 7276 7277 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7278 widenType, &Ops[0], Ops.size()); 7279 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp); 7280} 7281 7282static SDValue findMUL_LOHI(SDValue V) { 7283 if (V->getOpcode() == ISD::UMUL_LOHI || 7284 V->getOpcode() == ISD::SMUL_LOHI) 7285 return V; 7286 return SDValue(); 7287} 7288 7289static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode, 7290 TargetLowering::DAGCombinerInfo &DCI, 7291 const ARMSubtarget *Subtarget) { 7292 7293 if (Subtarget->isThumb1Only()) return SDValue(); 7294 7295 // Only perform the checks after legalize when the pattern is available. 7296 if (DCI.isBeforeLegalize()) return SDValue(); 7297 7298 // Look for multiply add opportunities. 7299 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where 7300 // each add nodes consumes a value from ISD::UMUL_LOHI and there is 7301 // a glue link from the first add to the second add. 7302 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by 7303 // a S/UMLAL instruction. 7304 // loAdd UMUL_LOHI 7305 // \ / :lo \ :hi 7306 // \ / \ [no multiline comment] 7307 // ADDC | hiAdd 7308 // \ :glue / / 7309 // \ / / 7310 // ADDE 7311 // 7312 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC"); 7313 SDValue AddcOp0 = AddcNode->getOperand(0); 7314 SDValue AddcOp1 = AddcNode->getOperand(1); 7315 7316 // Check if the two operands are from the same mul_lohi node. 7317 if (AddcOp0.getNode() == AddcOp1.getNode()) 7318 return SDValue(); 7319 7320 assert(AddcNode->getNumValues() == 2 && 7321 AddcNode->getValueType(0) == MVT::i32 && 7322 AddcNode->getValueType(1) == MVT::Glue && 7323 "Expect ADDC with two result values: i32, glue"); 7324 7325 // Check that the ADDC adds the low result of the S/UMUL_LOHI. 7326 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI && 7327 AddcOp0->getOpcode() != ISD::SMUL_LOHI && 7328 AddcOp1->getOpcode() != ISD::UMUL_LOHI && 7329 AddcOp1->getOpcode() != ISD::SMUL_LOHI) 7330 return SDValue(); 7331 7332 // Look for the glued ADDE. 7333 SDNode* AddeNode = AddcNode->getGluedUser(); 7334 if (AddeNode == NULL) 7335 return SDValue(); 7336 7337 // Make sure it is really an ADDE. 7338 if (AddeNode->getOpcode() != ISD::ADDE) 7339 return SDValue(); 7340 7341 assert(AddeNode->getNumOperands() == 3 && 7342 AddeNode->getOperand(2).getValueType() == MVT::Glue && 7343 "ADDE node has the wrong inputs"); 7344 7345 // Check for the triangle shape. 7346 SDValue AddeOp0 = AddeNode->getOperand(0); 7347 SDValue AddeOp1 = AddeNode->getOperand(1); 7348 7349 // Make sure that the ADDE operands are not coming from the same node. 7350 if (AddeOp0.getNode() == AddeOp1.getNode()) 7351 return SDValue(); 7352 7353 // Find the MUL_LOHI node walking up ADDE's operands. 7354 bool IsLeftOperandMUL = false; 7355 SDValue MULOp = findMUL_LOHI(AddeOp0); 7356 if (MULOp == SDValue()) 7357 MULOp = findMUL_LOHI(AddeOp1); 7358 else 7359 IsLeftOperandMUL = true; 7360 if (MULOp == SDValue()) 7361 return SDValue(); 7362 7363 // Figure out the right opcode. 7364 unsigned Opc = MULOp->getOpcode(); 7365 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; 7366 7367 // Figure out the high and low input values to the MLAL node. 7368 SDValue* HiMul = &MULOp; 7369 SDValue* HiAdd = NULL; 7370 SDValue* LoMul = NULL; 7371 SDValue* LowAdd = NULL; 7372 7373 if (IsLeftOperandMUL) 7374 HiAdd = &AddeOp1; 7375 else 7376 HiAdd = &AddeOp0; 7377 7378 7379 if (AddcOp0->getOpcode() == Opc) { 7380 LoMul = &AddcOp0; 7381 LowAdd = &AddcOp1; 7382 } 7383 if (AddcOp1->getOpcode() == Opc) { 7384 LoMul = &AddcOp1; 7385 LowAdd = &AddcOp0; 7386 } 7387 7388 if (LoMul == NULL) 7389 return SDValue(); 7390 7391 if (LoMul->getNode() != HiMul->getNode()) 7392 return SDValue(); 7393 7394 // Create the merged node. 7395 SelectionDAG &DAG = DCI.DAG; 7396 7397 // Build operand list. 7398 SmallVector<SDValue, 8> Ops; 7399 Ops.push_back(LoMul->getOperand(0)); 7400 Ops.push_back(LoMul->getOperand(1)); 7401 Ops.push_back(*LowAdd); 7402 Ops.push_back(*HiAdd); 7403 7404 SDValue MLALNode = DAG.getNode(FinalOpc, AddcNode->getDebugLoc(), 7405 DAG.getVTList(MVT::i32, MVT::i32), 7406 &Ops[0], Ops.size()); 7407 7408 // Replace the ADDs' nodes uses by the MLA node's values. 7409 SDValue HiMLALResult(MLALNode.getNode(), 1); 7410 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult); 7411 7412 SDValue LoMLALResult(MLALNode.getNode(), 0); 7413 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult); 7414 7415 // Return original node to notify the driver to stop replacing. 7416 SDValue resNode(AddcNode, 0); 7417 return resNode; 7418} 7419 7420/// PerformADDCCombine - Target-specific dag combine transform from 7421/// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL. 7422static SDValue PerformADDCCombine(SDNode *N, 7423 TargetLowering::DAGCombinerInfo &DCI, 7424 const ARMSubtarget *Subtarget) { 7425 7426 return AddCombineTo64bitMLAL(N, DCI, Subtarget); 7427 7428} 7429 7430/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 7431/// operands N0 and N1. This is a helper for PerformADDCombine that is 7432/// called with the default operands, and if that fails, with commuted 7433/// operands. 7434static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, 7435 TargetLowering::DAGCombinerInfo &DCI, 7436 const ARMSubtarget *Subtarget){ 7437 7438 // Attempt to create vpaddl for this add. 7439 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); 7440 if (Result.getNode()) 7441 return Result; 7442 7443 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 7444 if (N0.getNode()->hasOneUse()) { 7445 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 7446 if (Result.getNode()) return Result; 7447 } 7448 return SDValue(); 7449} 7450 7451/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 7452/// 7453static SDValue PerformADDCombine(SDNode *N, 7454 TargetLowering::DAGCombinerInfo &DCI, 7455 const ARMSubtarget *Subtarget) { 7456 SDValue N0 = N->getOperand(0); 7457 SDValue N1 = N->getOperand(1); 7458 7459 // First try with the default operand order. 7460 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); 7461 if (Result.getNode()) 7462 return Result; 7463 7464 // If that didn't work, try again with the operands commuted. 7465 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); 7466} 7467 7468/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 7469/// 7470static SDValue PerformSUBCombine(SDNode *N, 7471 TargetLowering::DAGCombinerInfo &DCI) { 7472 SDValue N0 = N->getOperand(0); 7473 SDValue N1 = N->getOperand(1); 7474 7475 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 7476 if (N1.getNode()->hasOneUse()) { 7477 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 7478 if (Result.getNode()) return Result; 7479 } 7480 7481 return SDValue(); 7482} 7483 7484/// PerformVMULCombine 7485/// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the 7486/// special multiplier accumulator forwarding. 7487/// vmul d3, d0, d2 7488/// vmla d3, d1, d2 7489/// is faster than 7490/// vadd d3, d0, d1 7491/// vmul d3, d3, d2 7492static SDValue PerformVMULCombine(SDNode *N, 7493 TargetLowering::DAGCombinerInfo &DCI, 7494 const ARMSubtarget *Subtarget) { 7495 if (!Subtarget->hasVMLxForwarding()) 7496 return SDValue(); 7497 7498 SelectionDAG &DAG = DCI.DAG; 7499 SDValue N0 = N->getOperand(0); 7500 SDValue N1 = N->getOperand(1); 7501 unsigned Opcode = N0.getOpcode(); 7502 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 7503 Opcode != ISD::FADD && Opcode != ISD::FSUB) { 7504 Opcode = N1.getOpcode(); 7505 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 7506 Opcode != ISD::FADD && Opcode != ISD::FSUB) 7507 return SDValue(); 7508 std::swap(N0, N1); 7509 } 7510 7511 EVT VT = N->getValueType(0); 7512 DebugLoc DL = N->getDebugLoc(); 7513 SDValue N00 = N0->getOperand(0); 7514 SDValue N01 = N0->getOperand(1); 7515 return DAG.getNode(Opcode, DL, VT, 7516 DAG.getNode(ISD::MUL, DL, VT, N00, N1), 7517 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); 7518} 7519 7520static SDValue PerformMULCombine(SDNode *N, 7521 TargetLowering::DAGCombinerInfo &DCI, 7522 const ARMSubtarget *Subtarget) { 7523 SelectionDAG &DAG = DCI.DAG; 7524 7525 if (Subtarget->isThumb1Only()) 7526 return SDValue(); 7527 7528 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 7529 return SDValue(); 7530 7531 EVT VT = N->getValueType(0); 7532 if (VT.is64BitVector() || VT.is128BitVector()) 7533 return PerformVMULCombine(N, DCI, Subtarget); 7534 if (VT != MVT::i32) 7535 return SDValue(); 7536 7537 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7538 if (!C) 7539 return SDValue(); 7540 7541 int64_t MulAmt = C->getSExtValue(); 7542 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 7543 7544 ShiftAmt = ShiftAmt & (32 - 1); 7545 SDValue V = N->getOperand(0); 7546 DebugLoc DL = N->getDebugLoc(); 7547 7548 SDValue Res; 7549 MulAmt >>= ShiftAmt; 7550 7551 if (MulAmt >= 0) { 7552 if (isPowerOf2_32(MulAmt - 1)) { 7553 // (mul x, 2^N + 1) => (add (shl x, N), x) 7554 Res = DAG.getNode(ISD::ADD, DL, VT, 7555 V, 7556 DAG.getNode(ISD::SHL, DL, VT, 7557 V, 7558 DAG.getConstant(Log2_32(MulAmt - 1), 7559 MVT::i32))); 7560 } else if (isPowerOf2_32(MulAmt + 1)) { 7561 // (mul x, 2^N - 1) => (sub (shl x, N), x) 7562 Res = DAG.getNode(ISD::SUB, DL, VT, 7563 DAG.getNode(ISD::SHL, DL, VT, 7564 V, 7565 DAG.getConstant(Log2_32(MulAmt + 1), 7566 MVT::i32)), 7567 V); 7568 } else 7569 return SDValue(); 7570 } else { 7571 uint64_t MulAmtAbs = -MulAmt; 7572 if (isPowerOf2_32(MulAmtAbs + 1)) { 7573 // (mul x, -(2^N - 1)) => (sub x, (shl x, N)) 7574 Res = DAG.getNode(ISD::SUB, DL, VT, 7575 V, 7576 DAG.getNode(ISD::SHL, DL, VT, 7577 V, 7578 DAG.getConstant(Log2_32(MulAmtAbs + 1), 7579 MVT::i32))); 7580 } else if (isPowerOf2_32(MulAmtAbs - 1)) { 7581 // (mul x, -(2^N + 1)) => - (add (shl x, N), x) 7582 Res = DAG.getNode(ISD::ADD, DL, VT, 7583 V, 7584 DAG.getNode(ISD::SHL, DL, VT, 7585 V, 7586 DAG.getConstant(Log2_32(MulAmtAbs-1), 7587 MVT::i32))); 7588 Res = DAG.getNode(ISD::SUB, DL, VT, 7589 DAG.getConstant(0, MVT::i32),Res); 7590 7591 } else 7592 return SDValue(); 7593 } 7594 7595 if (ShiftAmt != 0) 7596 Res = DAG.getNode(ISD::SHL, DL, VT, 7597 Res, DAG.getConstant(ShiftAmt, MVT::i32)); 7598 7599 // Do not add new nodes to DAG combiner worklist. 7600 DCI.CombineTo(N, Res, false); 7601 return SDValue(); 7602} 7603 7604static SDValue PerformANDCombine(SDNode *N, 7605 TargetLowering::DAGCombinerInfo &DCI, 7606 const ARMSubtarget *Subtarget) { 7607 7608 // Attempt to use immediate-form VBIC 7609 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 7610 DebugLoc dl = N->getDebugLoc(); 7611 EVT VT = N->getValueType(0); 7612 SelectionDAG &DAG = DCI.DAG; 7613 7614 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 7615 return SDValue(); 7616 7617 APInt SplatBits, SplatUndef; 7618 unsigned SplatBitSize; 7619 bool HasAnyUndefs; 7620 if (BVN && 7621 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 7622 if (SplatBitSize <= 64) { 7623 EVT VbicVT; 7624 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), 7625 SplatUndef.getZExtValue(), SplatBitSize, 7626 DAG, VbicVT, VT.is128BitVector(), 7627 OtherModImm); 7628 if (Val.getNode()) { 7629 SDValue Input = 7630 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); 7631 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); 7632 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); 7633 } 7634 } 7635 } 7636 7637 if (!Subtarget->isThumb1Only()) { 7638 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) 7639 SDValue Result = combineSelectAndUseCommutative(N, true, DCI); 7640 if (Result.getNode()) 7641 return Result; 7642 } 7643 7644 return SDValue(); 7645} 7646 7647/// PerformORCombine - Target-specific dag combine xforms for ISD::OR 7648static SDValue PerformORCombine(SDNode *N, 7649 TargetLowering::DAGCombinerInfo &DCI, 7650 const ARMSubtarget *Subtarget) { 7651 // Attempt to use immediate-form VORR 7652 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 7653 DebugLoc dl = N->getDebugLoc(); 7654 EVT VT = N->getValueType(0); 7655 SelectionDAG &DAG = DCI.DAG; 7656 7657 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 7658 return SDValue(); 7659 7660 APInt SplatBits, SplatUndef; 7661 unsigned SplatBitSize; 7662 bool HasAnyUndefs; 7663 if (BVN && Subtarget->hasNEON() && 7664 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 7665 if (SplatBitSize <= 64) { 7666 EVT VorrVT; 7667 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 7668 SplatUndef.getZExtValue(), SplatBitSize, 7669 DAG, VorrVT, VT.is128BitVector(), 7670 OtherModImm); 7671 if (Val.getNode()) { 7672 SDValue Input = 7673 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); 7674 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); 7675 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); 7676 } 7677 } 7678 } 7679 7680 if (!Subtarget->isThumb1Only()) { 7681 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c)) 7682 SDValue Result = combineSelectAndUseCommutative(N, false, DCI); 7683 if (Result.getNode()) 7684 return Result; 7685 } 7686 7687 // The code below optimizes (or (and X, Y), Z). 7688 // The AND operand needs to have a single user to make these optimizations 7689 // profitable. 7690 SDValue N0 = N->getOperand(0); 7691 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) 7692 return SDValue(); 7693 SDValue N1 = N->getOperand(1); 7694 7695 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. 7696 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && 7697 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 7698 APInt SplatUndef; 7699 unsigned SplatBitSize; 7700 bool HasAnyUndefs; 7701 7702 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); 7703 APInt SplatBits0; 7704 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, 7705 HasAnyUndefs) && !HasAnyUndefs) { 7706 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); 7707 APInt SplatBits1; 7708 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, 7709 HasAnyUndefs) && !HasAnyUndefs && 7710 SplatBits0 == ~SplatBits1) { 7711 // Canonicalize the vector type to make instruction selection simpler. 7712 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 7713 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, 7714 N0->getOperand(1), N0->getOperand(0), 7715 N1->getOperand(0)); 7716 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 7717 } 7718 } 7719 } 7720 7721 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when 7722 // reasonable. 7723 7724 // BFI is only available on V6T2+ 7725 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) 7726 return SDValue(); 7727 7728 DebugLoc DL = N->getDebugLoc(); 7729 // 1) or (and A, mask), val => ARMbfi A, val, mask 7730 // iff (val & mask) == val 7731 // 7732 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 7733 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) 7734 // && mask == ~mask2 7735 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) 7736 // && ~mask == mask2 7737 // (i.e., copy a bitfield value into another bitfield of the same width) 7738 7739 if (VT != MVT::i32) 7740 return SDValue(); 7741 7742 SDValue N00 = N0.getOperand(0); 7743 7744 // The value and the mask need to be constants so we can verify this is 7745 // actually a bitfield set. If the mask is 0xffff, we can do better 7746 // via a movt instruction, so don't use BFI in that case. 7747 SDValue MaskOp = N0.getOperand(1); 7748 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp); 7749 if (!MaskC) 7750 return SDValue(); 7751 unsigned Mask = MaskC->getZExtValue(); 7752 if (Mask == 0xffff) 7753 return SDValue(); 7754 SDValue Res; 7755 // Case (1): or (and A, mask), val => ARMbfi A, val, mask 7756 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 7757 if (N1C) { 7758 unsigned Val = N1C->getZExtValue(); 7759 if ((Val & ~Mask) != Val) 7760 return SDValue(); 7761 7762 if (ARM::isBitFieldInvertedMask(Mask)) { 7763 Val >>= CountTrailingZeros_32(~Mask); 7764 7765 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, 7766 DAG.getConstant(Val, MVT::i32), 7767 DAG.getConstant(Mask, MVT::i32)); 7768 7769 // Do not add new nodes to DAG combiner worklist. 7770 DCI.CombineTo(N, Res, false); 7771 return SDValue(); 7772 } 7773 } else if (N1.getOpcode() == ISD::AND) { 7774 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 7775 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 7776 if (!N11C) 7777 return SDValue(); 7778 unsigned Mask2 = N11C->getZExtValue(); 7779 7780 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern 7781 // as is to match. 7782 if (ARM::isBitFieldInvertedMask(Mask) && 7783 (Mask == ~Mask2)) { 7784 // The pack halfword instruction works better for masks that fit it, 7785 // so use that when it's available. 7786 if (Subtarget->hasT2ExtractPack() && 7787 (Mask == 0xffff || Mask == 0xffff0000)) 7788 return SDValue(); 7789 // 2a 7790 unsigned amt = CountTrailingZeros_32(Mask2); 7791 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), 7792 DAG.getConstant(amt, MVT::i32)); 7793 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, 7794 DAG.getConstant(Mask, MVT::i32)); 7795 // Do not add new nodes to DAG combiner worklist. 7796 DCI.CombineTo(N, Res, false); 7797 return SDValue(); 7798 } else if (ARM::isBitFieldInvertedMask(~Mask) && 7799 (~Mask == Mask2)) { 7800 // The pack halfword instruction works better for masks that fit it, 7801 // so use that when it's available. 7802 if (Subtarget->hasT2ExtractPack() && 7803 (Mask2 == 0xffff || Mask2 == 0xffff0000)) 7804 return SDValue(); 7805 // 2b 7806 unsigned lsb = CountTrailingZeros_32(Mask); 7807 Res = DAG.getNode(ISD::SRL, DL, VT, N00, 7808 DAG.getConstant(lsb, MVT::i32)); 7809 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, 7810 DAG.getConstant(Mask2, MVT::i32)); 7811 // Do not add new nodes to DAG combiner worklist. 7812 DCI.CombineTo(N, Res, false); 7813 return SDValue(); 7814 } 7815 } 7816 7817 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && 7818 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && 7819 ARM::isBitFieldInvertedMask(~Mask)) { 7820 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask 7821 // where lsb(mask) == #shamt and masked bits of B are known zero. 7822 SDValue ShAmt = N00.getOperand(1); 7823 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 7824 unsigned LSB = CountTrailingZeros_32(Mask); 7825 if (ShAmtC != LSB) 7826 return SDValue(); 7827 7828 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), 7829 DAG.getConstant(~Mask, MVT::i32)); 7830 7831 // Do not add new nodes to DAG combiner worklist. 7832 DCI.CombineTo(N, Res, false); 7833 } 7834 7835 return SDValue(); 7836} 7837 7838static SDValue PerformXORCombine(SDNode *N, 7839 TargetLowering::DAGCombinerInfo &DCI, 7840 const ARMSubtarget *Subtarget) { 7841 EVT VT = N->getValueType(0); 7842 SelectionDAG &DAG = DCI.DAG; 7843 7844 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 7845 return SDValue(); 7846 7847 if (!Subtarget->isThumb1Only()) { 7848 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c)) 7849 SDValue Result = combineSelectAndUseCommutative(N, false, DCI); 7850 if (Result.getNode()) 7851 return Result; 7852 } 7853 7854 return SDValue(); 7855} 7856 7857/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 7858/// the bits being cleared by the AND are not demanded by the BFI. 7859static SDValue PerformBFICombine(SDNode *N, 7860 TargetLowering::DAGCombinerInfo &DCI) { 7861 SDValue N1 = N->getOperand(1); 7862 if (N1.getOpcode() == ISD::AND) { 7863 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 7864 if (!N11C) 7865 return SDValue(); 7866 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 7867 unsigned LSB = CountTrailingZeros_32(~InvMask); 7868 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB; 7869 unsigned Mask = (1 << Width)-1; 7870 unsigned Mask2 = N11C->getZExtValue(); 7871 if ((Mask & (~Mask2)) == 0) 7872 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), 7873 N->getOperand(0), N1.getOperand(0), 7874 N->getOperand(2)); 7875 } 7876 return SDValue(); 7877} 7878 7879/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 7880/// ARMISD::VMOVRRD. 7881static SDValue PerformVMOVRRDCombine(SDNode *N, 7882 TargetLowering::DAGCombinerInfo &DCI) { 7883 // vmovrrd(vmovdrr x, y) -> x,y 7884 SDValue InDouble = N->getOperand(0); 7885 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 7886 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 7887 7888 // vmovrrd(load f64) -> (load i32), (load i32) 7889 SDNode *InNode = InDouble.getNode(); 7890 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() && 7891 InNode->getValueType(0) == MVT::f64 && 7892 InNode->getOperand(1).getOpcode() == ISD::FrameIndex && 7893 !cast<LoadSDNode>(InNode)->isVolatile()) { 7894 // TODO: Should this be done for non-FrameIndex operands? 7895 LoadSDNode *LD = cast<LoadSDNode>(InNode); 7896 7897 SelectionDAG &DAG = DCI.DAG; 7898 DebugLoc DL = LD->getDebugLoc(); 7899 SDValue BasePtr = LD->getBasePtr(); 7900 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, 7901 LD->getPointerInfo(), LD->isVolatile(), 7902 LD->isNonTemporal(), LD->isInvariant(), 7903 LD->getAlignment()); 7904 7905 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 7906 DAG.getConstant(4, MVT::i32)); 7907 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, 7908 LD->getPointerInfo(), LD->isVolatile(), 7909 LD->isNonTemporal(), LD->isInvariant(), 7910 std::min(4U, LD->getAlignment() / 2)); 7911 7912 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); 7913 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); 7914 DCI.RemoveFromWorklist(LD); 7915 DAG.DeleteNode(LD); 7916 return Result; 7917 } 7918 7919 return SDValue(); 7920} 7921 7922/// PerformVMOVDRRCombine - Target-specific dag combine xforms for 7923/// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. 7924static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { 7925 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) 7926 SDValue Op0 = N->getOperand(0); 7927 SDValue Op1 = N->getOperand(1); 7928 if (Op0.getOpcode() == ISD::BITCAST) 7929 Op0 = Op0.getOperand(0); 7930 if (Op1.getOpcode() == ISD::BITCAST) 7931 Op1 = Op1.getOperand(0); 7932 if (Op0.getOpcode() == ARMISD::VMOVRRD && 7933 Op0.getNode() == Op1.getNode() && 7934 Op0.getResNo() == 0 && Op1.getResNo() == 1) 7935 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 7936 N->getValueType(0), Op0.getOperand(0)); 7937 return SDValue(); 7938} 7939 7940/// PerformSTORECombine - Target-specific dag combine xforms for 7941/// ISD::STORE. 7942static SDValue PerformSTORECombine(SDNode *N, 7943 TargetLowering::DAGCombinerInfo &DCI) { 7944 StoreSDNode *St = cast<StoreSDNode>(N); 7945 if (St->isVolatile()) 7946 return SDValue(); 7947 7948 // Optimize trunc store (of multiple scalars) to shuffle and store. First, 7949 // pack all of the elements in one place. Next, store to memory in fewer 7950 // chunks. 7951 SDValue StVal = St->getValue(); 7952 EVT VT = StVal.getValueType(); 7953 if (St->isTruncatingStore() && VT.isVector()) { 7954 SelectionDAG &DAG = DCI.DAG; 7955 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7956 EVT StVT = St->getMemoryVT(); 7957 unsigned NumElems = VT.getVectorNumElements(); 7958 assert(StVT != VT && "Cannot truncate to the same type"); 7959 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits(); 7960 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits(); 7961 7962 // From, To sizes and ElemCount must be pow of two 7963 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue(); 7964 7965 // We are going to use the original vector elt for storing. 7966 // Accumulated smaller vector elements must be a multiple of the store size. 7967 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue(); 7968 7969 unsigned SizeRatio = FromEltSz / ToEltSz; 7970 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits()); 7971 7972 // Create a type on which we perform the shuffle. 7973 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(), 7974 NumElems*SizeRatio); 7975 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 7976 7977 DebugLoc DL = St->getDebugLoc(); 7978 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); 7979 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 7980 for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio; 7981 7982 // Can't shuffle using an illegal type. 7983 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 7984 7985 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec, 7986 DAG.getUNDEF(WideVec.getValueType()), 7987 ShuffleVec.data()); 7988 // At this point all of the data is stored at the bottom of the 7989 // register. We now need to save it to mem. 7990 7991 // Find the largest store unit 7992 MVT StoreType = MVT::i8; 7993 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 7994 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 7995 MVT Tp = (MVT::SimpleValueType)tp; 7996 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz) 7997 StoreType = Tp; 7998 } 7999 // Didn't find a legal store type. 8000 if (!TLI.isTypeLegal(StoreType)) 8001 return SDValue(); 8002 8003 // Bitcast the original vector into a vector of store-size units 8004 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 8005 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 8006 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 8007 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff); 8008 SmallVector<SDValue, 8> Chains; 8009 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 8010 TLI.getPointerTy()); 8011 SDValue BasePtr = St->getBasePtr(); 8012 8013 // Perform one or more big stores into memory. 8014 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits(); 8015 for (unsigned I = 0; I < E; I++) { 8016 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 8017 StoreType, ShuffWide, 8018 DAG.getIntPtrConstant(I)); 8019 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr, 8020 St->getPointerInfo(), St->isVolatile(), 8021 St->isNonTemporal(), St->getAlignment()); 8022 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr, 8023 Increment); 8024 Chains.push_back(Ch); 8025 } 8026 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0], 8027 Chains.size()); 8028 } 8029 8030 if (!ISD::isNormalStore(St)) 8031 return SDValue(); 8032 8033 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and 8034 // ARM stores of arguments in the same cache line. 8035 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && 8036 StVal.getNode()->hasOneUse()) { 8037 SelectionDAG &DAG = DCI.DAG; 8038 DebugLoc DL = St->getDebugLoc(); 8039 SDValue BasePtr = St->getBasePtr(); 8040 SDValue NewST1 = DAG.getStore(St->getChain(), DL, 8041 StVal.getNode()->getOperand(0), BasePtr, 8042 St->getPointerInfo(), St->isVolatile(), 8043 St->isNonTemporal(), St->getAlignment()); 8044 8045 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 8046 DAG.getConstant(4, MVT::i32)); 8047 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), 8048 OffsetPtr, St->getPointerInfo(), St->isVolatile(), 8049 St->isNonTemporal(), 8050 std::min(4U, St->getAlignment() / 2)); 8051 } 8052 8053 if (StVal.getValueType() != MVT::i64 || 8054 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 8055 return SDValue(); 8056 8057 // Bitcast an i64 store extracted from a vector to f64. 8058 // Otherwise, the i64 value will be legalized to a pair of i32 values. 8059 SelectionDAG &DAG = DCI.DAG; 8060 DebugLoc dl = StVal.getDebugLoc(); 8061 SDValue IntVec = StVal.getOperand(0); 8062 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 8063 IntVec.getValueType().getVectorNumElements()); 8064 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); 8065 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 8066 Vec, StVal.getOperand(1)); 8067 dl = N->getDebugLoc(); 8068 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); 8069 // Make the DAGCombiner fold the bitcasts. 8070 DCI.AddToWorklist(Vec.getNode()); 8071 DCI.AddToWorklist(ExtElt.getNode()); 8072 DCI.AddToWorklist(V.getNode()); 8073 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), 8074 St->getPointerInfo(), St->isVolatile(), 8075 St->isNonTemporal(), St->getAlignment(), 8076 St->getTBAAInfo()); 8077} 8078 8079/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node 8080/// are normal, non-volatile loads. If so, it is profitable to bitcast an 8081/// i64 vector to have f64 elements, since the value can then be loaded 8082/// directly into a VFP register. 8083static bool hasNormalLoadOperand(SDNode *N) { 8084 unsigned NumElts = N->getValueType(0).getVectorNumElements(); 8085 for (unsigned i = 0; i < NumElts; ++i) { 8086 SDNode *Elt = N->getOperand(i).getNode(); 8087 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile()) 8088 return true; 8089 } 8090 return false; 8091} 8092 8093/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for 8094/// ISD::BUILD_VECTOR. 8095static SDValue PerformBUILD_VECTORCombine(SDNode *N, 8096 TargetLowering::DAGCombinerInfo &DCI){ 8097 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): 8098 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value 8099 // into a pair of GPRs, which is fine when the value is used as a scalar, 8100 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. 8101 SelectionDAG &DAG = DCI.DAG; 8102 if (N->getNumOperands() == 2) { 8103 SDValue RV = PerformVMOVDRRCombine(N, DAG); 8104 if (RV.getNode()) 8105 return RV; 8106 } 8107 8108 // Load i64 elements as f64 values so that type legalization does not split 8109 // them up into i32 values. 8110 EVT VT = N->getValueType(0); 8111 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) 8112 return SDValue(); 8113 DebugLoc dl = N->getDebugLoc(); 8114 SmallVector<SDValue, 8> Ops; 8115 unsigned NumElts = VT.getVectorNumElements(); 8116 for (unsigned i = 0; i < NumElts; ++i) { 8117 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); 8118 Ops.push_back(V); 8119 // Make the DAGCombiner fold the bitcast. 8120 DCI.AddToWorklist(V.getNode()); 8121 } 8122 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); 8123 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts); 8124 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 8125} 8126 8127/// PerformInsertEltCombine - Target-specific dag combine xforms for 8128/// ISD::INSERT_VECTOR_ELT. 8129static SDValue PerformInsertEltCombine(SDNode *N, 8130 TargetLowering::DAGCombinerInfo &DCI) { 8131 // Bitcast an i64 load inserted into a vector to f64. 8132 // Otherwise, the i64 value will be legalized to a pair of i32 values. 8133 EVT VT = N->getValueType(0); 8134 SDNode *Elt = N->getOperand(1).getNode(); 8135 if (VT.getVectorElementType() != MVT::i64 || 8136 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile()) 8137 return SDValue(); 8138 8139 SelectionDAG &DAG = DCI.DAG; 8140 DebugLoc dl = N->getDebugLoc(); 8141 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 8142 VT.getVectorNumElements()); 8143 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); 8144 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); 8145 // Make the DAGCombiner fold the bitcasts. 8146 DCI.AddToWorklist(Vec.getNode()); 8147 DCI.AddToWorklist(V.getNode()); 8148 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, 8149 Vec, V, N->getOperand(2)); 8150 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); 8151} 8152 8153/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for 8154/// ISD::VECTOR_SHUFFLE. 8155static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { 8156 // The LLVM shufflevector instruction does not require the shuffle mask 8157 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does 8158 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the 8159 // operands do not match the mask length, they are extended by concatenating 8160 // them with undef vectors. That is probably the right thing for other 8161 // targets, but for NEON it is better to concatenate two double-register 8162 // size vector operands into a single quad-register size vector. Do that 8163 // transformation here: 8164 // shuffle(concat(v1, undef), concat(v2, undef)) -> 8165 // shuffle(concat(v1, v2), undef) 8166 SDValue Op0 = N->getOperand(0); 8167 SDValue Op1 = N->getOperand(1); 8168 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || 8169 Op1.getOpcode() != ISD::CONCAT_VECTORS || 8170 Op0.getNumOperands() != 2 || 8171 Op1.getNumOperands() != 2) 8172 return SDValue(); 8173 SDValue Concat0Op1 = Op0.getOperand(1); 8174 SDValue Concat1Op1 = Op1.getOperand(1); 8175 if (Concat0Op1.getOpcode() != ISD::UNDEF || 8176 Concat1Op1.getOpcode() != ISD::UNDEF) 8177 return SDValue(); 8178 // Skip the transformation if any of the types are illegal. 8179 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8180 EVT VT = N->getValueType(0); 8181 if (!TLI.isTypeLegal(VT) || 8182 !TLI.isTypeLegal(Concat0Op1.getValueType()) || 8183 !TLI.isTypeLegal(Concat1Op1.getValueType())) 8184 return SDValue(); 8185 8186 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 8187 Op0.getOperand(0), Op1.getOperand(0)); 8188 // Translate the shuffle mask. 8189 SmallVector<int, 16> NewMask; 8190 unsigned NumElts = VT.getVectorNumElements(); 8191 unsigned HalfElts = NumElts/2; 8192 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8193 for (unsigned n = 0; n < NumElts; ++n) { 8194 int MaskElt = SVN->getMaskElt(n); 8195 int NewElt = -1; 8196 if (MaskElt < (int)HalfElts) 8197 NewElt = MaskElt; 8198 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts)) 8199 NewElt = HalfElts + MaskElt - NumElts; 8200 NewMask.push_back(NewElt); 8201 } 8202 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat, 8203 DAG.getUNDEF(VT), NewMask.data()); 8204} 8205 8206/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and 8207/// NEON load/store intrinsics to merge base address updates. 8208static SDValue CombineBaseUpdate(SDNode *N, 8209 TargetLowering::DAGCombinerInfo &DCI) { 8210 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 8211 return SDValue(); 8212 8213 SelectionDAG &DAG = DCI.DAG; 8214 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || 8215 N->getOpcode() == ISD::INTRINSIC_W_CHAIN); 8216 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1); 8217 SDValue Addr = N->getOperand(AddrOpIdx); 8218 8219 // Search for a use of the address operand that is an increment. 8220 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 8221 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 8222 SDNode *User = *UI; 8223 if (User->getOpcode() != ISD::ADD || 8224 UI.getUse().getResNo() != Addr.getResNo()) 8225 continue; 8226 8227 // Check that the add is independent of the load/store. Otherwise, folding 8228 // it would create a cycle. 8229 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 8230 continue; 8231 8232 // Find the new opcode for the updating load/store. 8233 bool isLoad = true; 8234 bool isLaneOp = false; 8235 unsigned NewOpc = 0; 8236 unsigned NumVecs = 0; 8237 if (isIntrinsic) { 8238 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 8239 switch (IntNo) { 8240 default: llvm_unreachable("unexpected intrinsic for Neon base update"); 8241 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; 8242 NumVecs = 1; break; 8243 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; 8244 NumVecs = 2; break; 8245 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; 8246 NumVecs = 3; break; 8247 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; 8248 NumVecs = 4; break; 8249 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; 8250 NumVecs = 2; isLaneOp = true; break; 8251 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; 8252 NumVecs = 3; isLaneOp = true; break; 8253 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; 8254 NumVecs = 4; isLaneOp = true; break; 8255 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; 8256 NumVecs = 1; isLoad = false; break; 8257 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; 8258 NumVecs = 2; isLoad = false; break; 8259 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; 8260 NumVecs = 3; isLoad = false; break; 8261 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; 8262 NumVecs = 4; isLoad = false; break; 8263 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; 8264 NumVecs = 2; isLoad = false; isLaneOp = true; break; 8265 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; 8266 NumVecs = 3; isLoad = false; isLaneOp = true; break; 8267 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; 8268 NumVecs = 4; isLoad = false; isLaneOp = true; break; 8269 } 8270 } else { 8271 isLaneOp = true; 8272 switch (N->getOpcode()) { 8273 default: llvm_unreachable("unexpected opcode for Neon base update"); 8274 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; 8275 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; 8276 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; 8277 } 8278 } 8279 8280 // Find the size of memory referenced by the load/store. 8281 EVT VecTy; 8282 if (isLoad) 8283 VecTy = N->getValueType(0); 8284 else 8285 VecTy = N->getOperand(AddrOpIdx+1).getValueType(); 8286 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 8287 if (isLaneOp) 8288 NumBytes /= VecTy.getVectorNumElements(); 8289 8290 // If the increment is a constant, it must match the memory ref size. 8291 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 8292 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 8293 uint64_t IncVal = CInc->getZExtValue(); 8294 if (IncVal != NumBytes) 8295 continue; 8296 } else if (NumBytes >= 3 * 16) { 8297 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two 8298 // separate instructions that make it harder to use a non-constant update. 8299 continue; 8300 } 8301 8302 // Create the new updating load/store node. 8303 EVT Tys[6]; 8304 unsigned NumResultVecs = (isLoad ? NumVecs : 0); 8305 unsigned n; 8306 for (n = 0; n < NumResultVecs; ++n) 8307 Tys[n] = VecTy; 8308 Tys[n++] = MVT::i32; 8309 Tys[n] = MVT::Other; 8310 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2); 8311 SmallVector<SDValue, 8> Ops; 8312 Ops.push_back(N->getOperand(0)); // incoming chain 8313 Ops.push_back(N->getOperand(AddrOpIdx)); 8314 Ops.push_back(Inc); 8315 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) { 8316 Ops.push_back(N->getOperand(i)); 8317 } 8318 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 8319 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys, 8320 Ops.data(), Ops.size(), 8321 MemInt->getMemoryVT(), 8322 MemInt->getMemOperand()); 8323 8324 // Update the uses. 8325 std::vector<SDValue> NewResults; 8326 for (unsigned i = 0; i < NumResultVecs; ++i) { 8327 NewResults.push_back(SDValue(UpdN.getNode(), i)); 8328 } 8329 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain 8330 DCI.CombineTo(N, NewResults); 8331 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 8332 8333 break; 8334 } 8335 return SDValue(); 8336} 8337 8338/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a 8339/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic 8340/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and 8341/// return true. 8342static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { 8343 SelectionDAG &DAG = DCI.DAG; 8344 EVT VT = N->getValueType(0); 8345 // vldN-dup instructions only support 64-bit vectors for N > 1. 8346 if (!VT.is64BitVector()) 8347 return false; 8348 8349 // Check if the VDUPLANE operand is a vldN-dup intrinsic. 8350 SDNode *VLD = N->getOperand(0).getNode(); 8351 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) 8352 return false; 8353 unsigned NumVecs = 0; 8354 unsigned NewOpc = 0; 8355 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); 8356 if (IntNo == Intrinsic::arm_neon_vld2lane) { 8357 NumVecs = 2; 8358 NewOpc = ARMISD::VLD2DUP; 8359 } else if (IntNo == Intrinsic::arm_neon_vld3lane) { 8360 NumVecs = 3; 8361 NewOpc = ARMISD::VLD3DUP; 8362 } else if (IntNo == Intrinsic::arm_neon_vld4lane) { 8363 NumVecs = 4; 8364 NewOpc = ARMISD::VLD4DUP; 8365 } else { 8366 return false; 8367 } 8368 8369 // First check that all the vldN-lane uses are VDUPLANEs and that the lane 8370 // numbers match the load. 8371 unsigned VLDLaneNo = 8372 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); 8373 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 8374 UI != UE; ++UI) { 8375 // Ignore uses of the chain result. 8376 if (UI.getUse().getResNo() == NumVecs) 8377 continue; 8378 SDNode *User = *UI; 8379 if (User->getOpcode() != ARMISD::VDUPLANE || 8380 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) 8381 return false; 8382 } 8383 8384 // Create the vldN-dup node. 8385 EVT Tys[5]; 8386 unsigned n; 8387 for (n = 0; n < NumVecs; ++n) 8388 Tys[n] = VT; 8389 Tys[n] = MVT::Other; 8390 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1); 8391 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; 8392 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); 8393 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, 8394 Ops, 2, VLDMemInt->getMemoryVT(), 8395 VLDMemInt->getMemOperand()); 8396 8397 // Update the uses. 8398 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 8399 UI != UE; ++UI) { 8400 unsigned ResNo = UI.getUse().getResNo(); 8401 // Ignore uses of the chain result. 8402 if (ResNo == NumVecs) 8403 continue; 8404 SDNode *User = *UI; 8405 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); 8406 } 8407 8408 // Now the vldN-lane intrinsic is dead except for its chain result. 8409 // Update uses of the chain. 8410 std::vector<SDValue> VLDDupResults; 8411 for (unsigned n = 0; n < NumVecs; ++n) 8412 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); 8413 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); 8414 DCI.CombineTo(VLD, VLDDupResults); 8415 8416 return true; 8417} 8418 8419/// PerformVDUPLANECombine - Target-specific dag combine xforms for 8420/// ARMISD::VDUPLANE. 8421static SDValue PerformVDUPLANECombine(SDNode *N, 8422 TargetLowering::DAGCombinerInfo &DCI) { 8423 SDValue Op = N->getOperand(0); 8424 8425 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses 8426 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. 8427 if (CombineVLDDUP(N, DCI)) 8428 return SDValue(N, 0); 8429 8430 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is 8431 // redundant. Ignore bit_converts for now; element sizes are checked below. 8432 while (Op.getOpcode() == ISD::BITCAST) 8433 Op = Op.getOperand(0); 8434 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) 8435 return SDValue(); 8436 8437 // Make sure the VMOV element size is not bigger than the VDUPLANE elements. 8438 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); 8439 // The canonical VMOV for a zero vector uses a 32-bit element size. 8440 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8441 unsigned EltBits; 8442 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) 8443 EltSize = 8; 8444 EVT VT = N->getValueType(0); 8445 if (EltSize > VT.getVectorElementType().getSizeInBits()) 8446 return SDValue(); 8447 8448 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 8449} 8450 8451// isConstVecPow2 - Return true if each vector element is a power of 2, all 8452// elements are the same constant, C, and Log2(C) ranges from 1 to 32. 8453static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) 8454{ 8455 integerPart cN; 8456 integerPart c0 = 0; 8457 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements(); 8458 I != E; I++) { 8459 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I)); 8460 if (!C) 8461 return false; 8462 8463 bool isExact; 8464 APFloat APF = C->getValueAPF(); 8465 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact) 8466 != APFloat::opOK || !isExact) 8467 return false; 8468 8469 c0 = (I == 0) ? cN : c0; 8470 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32) 8471 return false; 8472 } 8473 C = c0; 8474 return true; 8475} 8476 8477/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) 8478/// can replace combinations of VMUL and VCVT (floating-point to integer) 8479/// when the VMUL has a constant operand that is a power of 2. 8480/// 8481/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 8482/// vmul.f32 d16, d17, d16 8483/// vcvt.s32.f32 d16, d16 8484/// becomes: 8485/// vcvt.s32.f32 d16, d16, #3 8486static SDValue PerformVCVTCombine(SDNode *N, 8487 TargetLowering::DAGCombinerInfo &DCI, 8488 const ARMSubtarget *Subtarget) { 8489 SelectionDAG &DAG = DCI.DAG; 8490 SDValue Op = N->getOperand(0); 8491 8492 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() || 8493 Op.getOpcode() != ISD::FMUL) 8494 return SDValue(); 8495 8496 uint64_t C; 8497 SDValue N0 = Op->getOperand(0); 8498 SDValue ConstVec = Op->getOperand(1); 8499 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; 8500 8501 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 8502 !isConstVecPow2(ConstVec, isSigned, C)) 8503 return SDValue(); 8504 8505 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs : 8506 Intrinsic::arm_neon_vcvtfp2fxu; 8507 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 8508 N->getValueType(0), 8509 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 8510 DAG.getConstant(Log2_64(C), MVT::i32)); 8511} 8512 8513/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) 8514/// can replace combinations of VCVT (integer to floating-point) and VDIV 8515/// when the VDIV has a constant operand that is a power of 2. 8516/// 8517/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 8518/// vcvt.f32.s32 d16, d16 8519/// vdiv.f32 d16, d17, d16 8520/// becomes: 8521/// vcvt.f32.s32 d16, d16, #3 8522static SDValue PerformVDIVCombine(SDNode *N, 8523 TargetLowering::DAGCombinerInfo &DCI, 8524 const ARMSubtarget *Subtarget) { 8525 SelectionDAG &DAG = DCI.DAG; 8526 SDValue Op = N->getOperand(0); 8527 unsigned OpOpcode = Op.getNode()->getOpcode(); 8528 8529 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() || 8530 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) 8531 return SDValue(); 8532 8533 uint64_t C; 8534 SDValue ConstVec = N->getOperand(1); 8535 bool isSigned = OpOpcode == ISD::SINT_TO_FP; 8536 8537 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 8538 !isConstVecPow2(ConstVec, isSigned, C)) 8539 return SDValue(); 8540 8541 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 8542 Intrinsic::arm_neon_vcvtfxu2fp; 8543 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 8544 Op.getValueType(), 8545 DAG.getConstant(IntrinsicOpcode, MVT::i32), 8546 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); 8547} 8548 8549/// Getvshiftimm - Check if this is a valid build_vector for the immediate 8550/// operand of a vector shift operation, where all the elements of the 8551/// build_vector must have the same constant integer value. 8552static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 8553 // Ignore bit_converts. 8554 while (Op.getOpcode() == ISD::BITCAST) 8555 Op = Op.getOperand(0); 8556 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 8557 APInt SplatBits, SplatUndef; 8558 unsigned SplatBitSize; 8559 bool HasAnyUndefs; 8560 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 8561 HasAnyUndefs, ElementBits) || 8562 SplatBitSize > ElementBits) 8563 return false; 8564 Cnt = SplatBits.getSExtValue(); 8565 return true; 8566} 8567 8568/// isVShiftLImm - Check if this is a valid build_vector for the immediate 8569/// operand of a vector shift left operation. That value must be in the range: 8570/// 0 <= Value < ElementBits for a left shift; or 8571/// 0 <= Value <= ElementBits for a long left shift. 8572static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 8573 assert(VT.isVector() && "vector shift count is not a vector type"); 8574 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 8575 if (! getVShiftImm(Op, ElementBits, Cnt)) 8576 return false; 8577 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 8578} 8579 8580/// isVShiftRImm - Check if this is a valid build_vector for the immediate 8581/// operand of a vector shift right operation. For a shift opcode, the value 8582/// is positive, but for an intrinsic the value count must be negative. The 8583/// absolute value must be in the range: 8584/// 1 <= |Value| <= ElementBits for a right shift; or 8585/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 8586static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 8587 int64_t &Cnt) { 8588 assert(VT.isVector() && "vector shift count is not a vector type"); 8589 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 8590 if (! getVShiftImm(Op, ElementBits, Cnt)) 8591 return false; 8592 if (isIntrinsic) 8593 Cnt = -Cnt; 8594 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 8595} 8596 8597/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 8598static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 8599 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 8600 switch (IntNo) { 8601 default: 8602 // Don't do anything for most intrinsics. 8603 break; 8604 8605 // Vector shifts: check for immediate versions and lower them. 8606 // Note: This is done during DAG combining instead of DAG legalizing because 8607 // the build_vectors for 64-bit vector element shift counts are generally 8608 // not legal, and it is hard to see their values after they get legalized to 8609 // loads from a constant pool. 8610 case Intrinsic::arm_neon_vshifts: 8611 case Intrinsic::arm_neon_vshiftu: 8612 case Intrinsic::arm_neon_vshiftls: 8613 case Intrinsic::arm_neon_vshiftlu: 8614 case Intrinsic::arm_neon_vshiftn: 8615 case Intrinsic::arm_neon_vrshifts: 8616 case Intrinsic::arm_neon_vrshiftu: 8617 case Intrinsic::arm_neon_vrshiftn: 8618 case Intrinsic::arm_neon_vqshifts: 8619 case Intrinsic::arm_neon_vqshiftu: 8620 case Intrinsic::arm_neon_vqshiftsu: 8621 case Intrinsic::arm_neon_vqshiftns: 8622 case Intrinsic::arm_neon_vqshiftnu: 8623 case Intrinsic::arm_neon_vqshiftnsu: 8624 case Intrinsic::arm_neon_vqrshiftns: 8625 case Intrinsic::arm_neon_vqrshiftnu: 8626 case Intrinsic::arm_neon_vqrshiftnsu: { 8627 EVT VT = N->getOperand(1).getValueType(); 8628 int64_t Cnt; 8629 unsigned VShiftOpc = 0; 8630 8631 switch (IntNo) { 8632 case Intrinsic::arm_neon_vshifts: 8633 case Intrinsic::arm_neon_vshiftu: 8634 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 8635 VShiftOpc = ARMISD::VSHL; 8636 break; 8637 } 8638 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 8639 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 8640 ARMISD::VSHRs : ARMISD::VSHRu); 8641 break; 8642 } 8643 return SDValue(); 8644 8645 case Intrinsic::arm_neon_vshiftls: 8646 case Intrinsic::arm_neon_vshiftlu: 8647 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 8648 break; 8649 llvm_unreachable("invalid shift count for vshll intrinsic"); 8650 8651 case Intrinsic::arm_neon_vrshifts: 8652 case Intrinsic::arm_neon_vrshiftu: 8653 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 8654 break; 8655 return SDValue(); 8656 8657 case Intrinsic::arm_neon_vqshifts: 8658 case Intrinsic::arm_neon_vqshiftu: 8659 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 8660 break; 8661 return SDValue(); 8662 8663 case Intrinsic::arm_neon_vqshiftsu: 8664 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 8665 break; 8666 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 8667 8668 case Intrinsic::arm_neon_vshiftn: 8669 case Intrinsic::arm_neon_vrshiftn: 8670 case Intrinsic::arm_neon_vqshiftns: 8671 case Intrinsic::arm_neon_vqshiftnu: 8672 case Intrinsic::arm_neon_vqshiftnsu: 8673 case Intrinsic::arm_neon_vqrshiftns: 8674 case Intrinsic::arm_neon_vqrshiftnu: 8675 case Intrinsic::arm_neon_vqrshiftnsu: 8676 // Narrowing shifts require an immediate right shift. 8677 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 8678 break; 8679 llvm_unreachable("invalid shift count for narrowing vector shift " 8680 "intrinsic"); 8681 8682 default: 8683 llvm_unreachable("unhandled vector shift"); 8684 } 8685 8686 switch (IntNo) { 8687 case Intrinsic::arm_neon_vshifts: 8688 case Intrinsic::arm_neon_vshiftu: 8689 // Opcode already set above. 8690 break; 8691 case Intrinsic::arm_neon_vshiftls: 8692 case Intrinsic::arm_neon_vshiftlu: 8693 if (Cnt == VT.getVectorElementType().getSizeInBits()) 8694 VShiftOpc = ARMISD::VSHLLi; 8695 else 8696 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 8697 ARMISD::VSHLLs : ARMISD::VSHLLu); 8698 break; 8699 case Intrinsic::arm_neon_vshiftn: 8700 VShiftOpc = ARMISD::VSHRN; break; 8701 case Intrinsic::arm_neon_vrshifts: 8702 VShiftOpc = ARMISD::VRSHRs; break; 8703 case Intrinsic::arm_neon_vrshiftu: 8704 VShiftOpc = ARMISD::VRSHRu; break; 8705 case Intrinsic::arm_neon_vrshiftn: 8706 VShiftOpc = ARMISD::VRSHRN; break; 8707 case Intrinsic::arm_neon_vqshifts: 8708 VShiftOpc = ARMISD::VQSHLs; break; 8709 case Intrinsic::arm_neon_vqshiftu: 8710 VShiftOpc = ARMISD::VQSHLu; break; 8711 case Intrinsic::arm_neon_vqshiftsu: 8712 VShiftOpc = ARMISD::VQSHLsu; break; 8713 case Intrinsic::arm_neon_vqshiftns: 8714 VShiftOpc = ARMISD::VQSHRNs; break; 8715 case Intrinsic::arm_neon_vqshiftnu: 8716 VShiftOpc = ARMISD::VQSHRNu; break; 8717 case Intrinsic::arm_neon_vqshiftnsu: 8718 VShiftOpc = ARMISD::VQSHRNsu; break; 8719 case Intrinsic::arm_neon_vqrshiftns: 8720 VShiftOpc = ARMISD::VQRSHRNs; break; 8721 case Intrinsic::arm_neon_vqrshiftnu: 8722 VShiftOpc = ARMISD::VQRSHRNu; break; 8723 case Intrinsic::arm_neon_vqrshiftnsu: 8724 VShiftOpc = ARMISD::VQRSHRNsu; break; 8725 } 8726 8727 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 8728 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 8729 } 8730 8731 case Intrinsic::arm_neon_vshiftins: { 8732 EVT VT = N->getOperand(1).getValueType(); 8733 int64_t Cnt; 8734 unsigned VShiftOpc = 0; 8735 8736 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 8737 VShiftOpc = ARMISD::VSLI; 8738 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 8739 VShiftOpc = ARMISD::VSRI; 8740 else { 8741 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 8742 } 8743 8744 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 8745 N->getOperand(1), N->getOperand(2), 8746 DAG.getConstant(Cnt, MVT::i32)); 8747 } 8748 8749 case Intrinsic::arm_neon_vqrshifts: 8750 case Intrinsic::arm_neon_vqrshiftu: 8751 // No immediate versions of these to check for. 8752 break; 8753 } 8754 8755 return SDValue(); 8756} 8757 8758/// PerformShiftCombine - Checks for immediate versions of vector shifts and 8759/// lowers them. As with the vector shift intrinsics, this is done during DAG 8760/// combining instead of DAG legalizing because the build_vectors for 64-bit 8761/// vector element shift counts are generally not legal, and it is hard to see 8762/// their values after they get legalized to loads from a constant pool. 8763static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 8764 const ARMSubtarget *ST) { 8765 EVT VT = N->getValueType(0); 8766 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) { 8767 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 8768 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16. 8769 SDValue N1 = N->getOperand(1); 8770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 8771 SDValue N0 = N->getOperand(0); 8772 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP && 8773 DAG.MaskedValueIsZero(N0.getOperand(0), 8774 APInt::getHighBitsSet(32, 16))) 8775 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, N0, N1); 8776 } 8777 } 8778 8779 // Nothing to be done for scalar shifts. 8780 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8781 if (!VT.isVector() || !TLI.isTypeLegal(VT)) 8782 return SDValue(); 8783 8784 assert(ST->hasNEON() && "unexpected vector shift"); 8785 int64_t Cnt; 8786 8787 switch (N->getOpcode()) { 8788 default: llvm_unreachable("unexpected shift opcode"); 8789 8790 case ISD::SHL: 8791 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 8792 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 8793 DAG.getConstant(Cnt, MVT::i32)); 8794 break; 8795 8796 case ISD::SRA: 8797 case ISD::SRL: 8798 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 8799 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 8800 ARMISD::VSHRs : ARMISD::VSHRu); 8801 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 8802 DAG.getConstant(Cnt, MVT::i32)); 8803 } 8804 } 8805 return SDValue(); 8806} 8807 8808/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 8809/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 8810static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 8811 const ARMSubtarget *ST) { 8812 SDValue N0 = N->getOperand(0); 8813 8814 // Check for sign- and zero-extensions of vector extract operations of 8- 8815 // and 16-bit vector elements. NEON supports these directly. They are 8816 // handled during DAG combining because type legalization will promote them 8817 // to 32-bit types and it is messy to recognize the operations after that. 8818 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 8819 SDValue Vec = N0.getOperand(0); 8820 SDValue Lane = N0.getOperand(1); 8821 EVT VT = N->getValueType(0); 8822 EVT EltVT = N0.getValueType(); 8823 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8824 8825 if (VT == MVT::i32 && 8826 (EltVT == MVT::i8 || EltVT == MVT::i16) && 8827 TLI.isTypeLegal(Vec.getValueType()) && 8828 isa<ConstantSDNode>(Lane)) { 8829 8830 unsigned Opc = 0; 8831 switch (N->getOpcode()) { 8832 default: llvm_unreachable("unexpected opcode"); 8833 case ISD::SIGN_EXTEND: 8834 Opc = ARMISD::VGETLANEs; 8835 break; 8836 case ISD::ZERO_EXTEND: 8837 case ISD::ANY_EXTEND: 8838 Opc = ARMISD::VGETLANEu; 8839 break; 8840 } 8841 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 8842 } 8843 } 8844 8845 return SDValue(); 8846} 8847 8848/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 8849/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 8850static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 8851 const ARMSubtarget *ST) { 8852 // If the target supports NEON, try to use vmax/vmin instructions for f32 8853 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, 8854 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 8855 // a NaN; only do the transformation when it matches that behavior. 8856 8857 // For now only do this when using NEON for FP operations; if using VFP, it 8858 // is not obvious that the benefit outweighs the cost of switching to the 8859 // NEON pipeline. 8860 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 8861 N->getValueType(0) != MVT::f32) 8862 return SDValue(); 8863 8864 SDValue CondLHS = N->getOperand(0); 8865 SDValue CondRHS = N->getOperand(1); 8866 SDValue LHS = N->getOperand(2); 8867 SDValue RHS = N->getOperand(3); 8868 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 8869 8870 unsigned Opcode = 0; 8871 bool IsReversed; 8872 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 8873 IsReversed = false; // x CC y ? x : y 8874 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 8875 IsReversed = true ; // x CC y ? y : x 8876 } else { 8877 return SDValue(); 8878 } 8879 8880 bool IsUnordered; 8881 switch (CC) { 8882 default: break; 8883 case ISD::SETOLT: 8884 case ISD::SETOLE: 8885 case ISD::SETLT: 8886 case ISD::SETLE: 8887 case ISD::SETULT: 8888 case ISD::SETULE: 8889 // If LHS is NaN, an ordered comparison will be false and the result will 8890 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 8891 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 8892 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 8893 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 8894 break; 8895 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 8896 // will return -0, so vmin can only be used for unsafe math or if one of 8897 // the operands is known to be nonzero. 8898 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 8899 !DAG.getTarget().Options.UnsafeFPMath && 8900 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 8901 break; 8902 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 8903 break; 8904 8905 case ISD::SETOGT: 8906 case ISD::SETOGE: 8907 case ISD::SETGT: 8908 case ISD::SETGE: 8909 case ISD::SETUGT: 8910 case ISD::SETUGE: 8911 // If LHS is NaN, an ordered comparison will be false and the result will 8912 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 8913 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 8914 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 8915 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 8916 break; 8917 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 8918 // will return +0, so vmax can only be used for unsafe math or if one of 8919 // the operands is known to be nonzero. 8920 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 8921 !DAG.getTarget().Options.UnsafeFPMath && 8922 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 8923 break; 8924 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 8925 break; 8926 } 8927 8928 if (!Opcode) 8929 return SDValue(); 8930 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 8931} 8932 8933/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. 8934SDValue 8935ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { 8936 SDValue Cmp = N->getOperand(4); 8937 if (Cmp.getOpcode() != ARMISD::CMPZ) 8938 // Only looking at EQ and NE cases. 8939 return SDValue(); 8940 8941 EVT VT = N->getValueType(0); 8942 DebugLoc dl = N->getDebugLoc(); 8943 SDValue LHS = Cmp.getOperand(0); 8944 SDValue RHS = Cmp.getOperand(1); 8945 SDValue FalseVal = N->getOperand(0); 8946 SDValue TrueVal = N->getOperand(1); 8947 SDValue ARMcc = N->getOperand(2); 8948 ARMCC::CondCodes CC = 8949 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); 8950 8951 // Simplify 8952 // mov r1, r0 8953 // cmp r1, x 8954 // mov r0, y 8955 // moveq r0, x 8956 // to 8957 // cmp r0, x 8958 // movne r0, y 8959 // 8960 // mov r1, r0 8961 // cmp r1, x 8962 // mov r0, x 8963 // movne r0, y 8964 // to 8965 // cmp r0, x 8966 // movne r0, y 8967 /// FIXME: Turn this into a target neutral optimization? 8968 SDValue Res; 8969 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { 8970 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, 8971 N->getOperand(3), Cmp); 8972 } else if (CC == ARMCC::EQ && TrueVal == RHS) { 8973 SDValue ARMcc; 8974 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); 8975 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, 8976 N->getOperand(3), NewCmp); 8977 } 8978 8979 if (Res.getNode()) { 8980 APInt KnownZero, KnownOne; 8981 DAG.ComputeMaskedBits(SDValue(N,0), KnownZero, KnownOne); 8982 // Capture demanded bits information that would be otherwise lost. 8983 if (KnownZero == 0xfffffffe) 8984 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 8985 DAG.getValueType(MVT::i1)); 8986 else if (KnownZero == 0xffffff00) 8987 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 8988 DAG.getValueType(MVT::i8)); 8989 else if (KnownZero == 0xffff0000) 8990 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 8991 DAG.getValueType(MVT::i16)); 8992 } 8993 8994 return Res; 8995} 8996 8997SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 8998 DAGCombinerInfo &DCI) const { 8999 switch (N->getOpcode()) { 9000 default: break; 9001 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget); 9002 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); 9003 case ISD::SUB: return PerformSUBCombine(N, DCI); 9004 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 9005 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 9006 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget); 9007 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget); 9008 case ARMISD::BFI: return PerformBFICombine(N, DCI); 9009 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 9010 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 9011 case ISD::STORE: return PerformSTORECombine(N, DCI); 9012 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI); 9013 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); 9014 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); 9015 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); 9016 case ISD::FP_TO_SINT: 9017 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget); 9018 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget); 9019 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 9020 case ISD::SHL: 9021 case ISD::SRA: 9022 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 9023 case ISD::SIGN_EXTEND: 9024 case ISD::ZERO_EXTEND: 9025 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 9026 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 9027 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); 9028 case ARMISD::VLD2DUP: 9029 case ARMISD::VLD3DUP: 9030 case ARMISD::VLD4DUP: 9031 return CombineBaseUpdate(N, DCI); 9032 case ISD::INTRINSIC_VOID: 9033 case ISD::INTRINSIC_W_CHAIN: 9034 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 9035 case Intrinsic::arm_neon_vld1: 9036 case Intrinsic::arm_neon_vld2: 9037 case Intrinsic::arm_neon_vld3: 9038 case Intrinsic::arm_neon_vld4: 9039 case Intrinsic::arm_neon_vld2lane: 9040 case Intrinsic::arm_neon_vld3lane: 9041 case Intrinsic::arm_neon_vld4lane: 9042 case Intrinsic::arm_neon_vst1: 9043 case Intrinsic::arm_neon_vst2: 9044 case Intrinsic::arm_neon_vst3: 9045 case Intrinsic::arm_neon_vst4: 9046 case Intrinsic::arm_neon_vst2lane: 9047 case Intrinsic::arm_neon_vst3lane: 9048 case Intrinsic::arm_neon_vst4lane: 9049 return CombineBaseUpdate(N, DCI); 9050 default: break; 9051 } 9052 break; 9053 } 9054 return SDValue(); 9055} 9056 9057bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, 9058 EVT VT) const { 9059 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); 9060} 9061 9062bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 9063 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus 9064 bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); 9065 9066 switch (VT.getSimpleVT().SimpleTy) { 9067 default: 9068 return false; 9069 case MVT::i8: 9070 case MVT::i16: 9071 case MVT::i32: 9072 // Unaligned access can use (for example) LRDB, LRDH, LDR 9073 return AllowsUnaligned; 9074 case MVT::f64: 9075 case MVT::v2f64: 9076 // For any little-endian targets with neon, we can support unaligned ld/st 9077 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8. 9078 // A big-endian target may also explictly support unaligned accesses 9079 return Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian()); 9080 } 9081} 9082 9083static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, 9084 unsigned AlignCheck) { 9085 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) && 9086 (DstAlign == 0 || DstAlign % AlignCheck == 0)); 9087} 9088 9089EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size, 9090 unsigned DstAlign, unsigned SrcAlign, 9091 bool IsZeroVal, 9092 bool MemcpyStrSrc, 9093 MachineFunction &MF) const { 9094 const Function *F = MF.getFunction(); 9095 9096 // See if we can use NEON instructions for this... 9097 if (IsZeroVal && 9098 !F->getFnAttributes().hasNoImplicitFloatAttr() && 9099 Subtarget->hasNEON()) { 9100 if (memOpAlign(SrcAlign, DstAlign, 16) && Size >= 16) { 9101 return MVT::v4i32; 9102 } else if (memOpAlign(SrcAlign, DstAlign, 8) && Size >= 8) { 9103 return MVT::v2i32; 9104 } 9105 } 9106 9107 // Lowering to i32/i16 if the size permits. 9108 if (Size >= 4) { 9109 return MVT::i32; 9110 } else if (Size >= 2) { 9111 return MVT::i16; 9112 } 9113 9114 // Let the target-independent logic figure it out. 9115 return MVT::Other; 9116} 9117 9118static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 9119 if (V < 0) 9120 return false; 9121 9122 unsigned Scale = 1; 9123 switch (VT.getSimpleVT().SimpleTy) { 9124 default: return false; 9125 case MVT::i1: 9126 case MVT::i8: 9127 // Scale == 1; 9128 break; 9129 case MVT::i16: 9130 // Scale == 2; 9131 Scale = 2; 9132 break; 9133 case MVT::i32: 9134 // Scale == 4; 9135 Scale = 4; 9136 break; 9137 } 9138 9139 if ((V & (Scale - 1)) != 0) 9140 return false; 9141 V /= Scale; 9142 return V == (V & ((1LL << 5) - 1)); 9143} 9144 9145static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 9146 const ARMSubtarget *Subtarget) { 9147 bool isNeg = false; 9148 if (V < 0) { 9149 isNeg = true; 9150 V = - V; 9151 } 9152 9153 switch (VT.getSimpleVT().SimpleTy) { 9154 default: return false; 9155 case MVT::i1: 9156 case MVT::i8: 9157 case MVT::i16: 9158 case MVT::i32: 9159 // + imm12 or - imm8 9160 if (isNeg) 9161 return V == (V & ((1LL << 8) - 1)); 9162 return V == (V & ((1LL << 12) - 1)); 9163 case MVT::f32: 9164 case MVT::f64: 9165 // Same as ARM mode. FIXME: NEON? 9166 if (!Subtarget->hasVFP2()) 9167 return false; 9168 if ((V & 3) != 0) 9169 return false; 9170 V >>= 2; 9171 return V == (V & ((1LL << 8) - 1)); 9172 } 9173} 9174 9175/// isLegalAddressImmediate - Return true if the integer value can be used 9176/// as the offset of the target addressing mode for load / store of the 9177/// given type. 9178static bool isLegalAddressImmediate(int64_t V, EVT VT, 9179 const ARMSubtarget *Subtarget) { 9180 if (V == 0) 9181 return true; 9182 9183 if (!VT.isSimple()) 9184 return false; 9185 9186 if (Subtarget->isThumb1Only()) 9187 return isLegalT1AddressImmediate(V, VT); 9188 else if (Subtarget->isThumb2()) 9189 return isLegalT2AddressImmediate(V, VT, Subtarget); 9190 9191 // ARM mode. 9192 if (V < 0) 9193 V = - V; 9194 switch (VT.getSimpleVT().SimpleTy) { 9195 default: return false; 9196 case MVT::i1: 9197 case MVT::i8: 9198 case MVT::i32: 9199 // +- imm12 9200 return V == (V & ((1LL << 12) - 1)); 9201 case MVT::i16: 9202 // +- imm8 9203 return V == (V & ((1LL << 8) - 1)); 9204 case MVT::f32: 9205 case MVT::f64: 9206 if (!Subtarget->hasVFP2()) // FIXME: NEON? 9207 return false; 9208 if ((V & 3) != 0) 9209 return false; 9210 V >>= 2; 9211 return V == (V & ((1LL << 8) - 1)); 9212 } 9213} 9214 9215bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 9216 EVT VT) const { 9217 int Scale = AM.Scale; 9218 if (Scale < 0) 9219 return false; 9220 9221 switch (VT.getSimpleVT().SimpleTy) { 9222 default: return false; 9223 case MVT::i1: 9224 case MVT::i8: 9225 case MVT::i16: 9226 case MVT::i32: 9227 if (Scale == 1) 9228 return true; 9229 // r + r << imm 9230 Scale = Scale & ~1; 9231 return Scale == 2 || Scale == 4 || Scale == 8; 9232 case MVT::i64: 9233 // r + r 9234 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 9235 return true; 9236 return false; 9237 case MVT::isVoid: 9238 // Note, we allow "void" uses (basically, uses that aren't loads or 9239 // stores), because arm allows folding a scale into many arithmetic 9240 // operations. This should be made more precise and revisited later. 9241 9242 // Allow r << imm, but the imm has to be a multiple of two. 9243 if (Scale & 1) return false; 9244 return isPowerOf2_32(Scale); 9245 } 9246} 9247 9248/// isLegalAddressingMode - Return true if the addressing mode represented 9249/// by AM is legal for this target, for a load/store of the specified type. 9250bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 9251 Type *Ty) const { 9252 EVT VT = getValueType(Ty, true); 9253 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 9254 return false; 9255 9256 // Can never fold addr of global into load/store. 9257 if (AM.BaseGV) 9258 return false; 9259 9260 switch (AM.Scale) { 9261 case 0: // no scale reg, must be "r+i" or "r", or "i". 9262 break; 9263 case 1: 9264 if (Subtarget->isThumb1Only()) 9265 return false; 9266 // FALL THROUGH. 9267 default: 9268 // ARM doesn't support any R+R*scale+imm addr modes. 9269 if (AM.BaseOffs) 9270 return false; 9271 9272 if (!VT.isSimple()) 9273 return false; 9274 9275 if (Subtarget->isThumb2()) 9276 return isLegalT2ScaledAddressingMode(AM, VT); 9277 9278 int Scale = AM.Scale; 9279 switch (VT.getSimpleVT().SimpleTy) { 9280 default: return false; 9281 case MVT::i1: 9282 case MVT::i8: 9283 case MVT::i32: 9284 if (Scale < 0) Scale = -Scale; 9285 if (Scale == 1) 9286 return true; 9287 // r + r << imm 9288 return isPowerOf2_32(Scale & ~1); 9289 case MVT::i16: 9290 case MVT::i64: 9291 // r + r 9292 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 9293 return true; 9294 return false; 9295 9296 case MVT::isVoid: 9297 // Note, we allow "void" uses (basically, uses that aren't loads or 9298 // stores), because arm allows folding a scale into many arithmetic 9299 // operations. This should be made more precise and revisited later. 9300 9301 // Allow r << imm, but the imm has to be a multiple of two. 9302 if (Scale & 1) return false; 9303 return isPowerOf2_32(Scale); 9304 } 9305 } 9306 return true; 9307} 9308 9309/// isLegalICmpImmediate - Return true if the specified immediate is legal 9310/// icmp immediate, that is the target has icmp instructions which can compare 9311/// a register against the immediate without having to materialize the 9312/// immediate into a register. 9313bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 9314 // Thumb2 and ARM modes can use cmn for negative immediates. 9315 if (!Subtarget->isThumb()) 9316 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1; 9317 if (Subtarget->isThumb2()) 9318 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1; 9319 // Thumb1 doesn't have cmn, and only 8-bit immediates. 9320 return Imm >= 0 && Imm <= 255; 9321} 9322 9323/// isLegalAddImmediate - Return true if the specified immediate is a legal add 9324/// *or sub* immediate, that is the target has add or sub instructions which can 9325/// add a register with the immediate without having to materialize the 9326/// immediate into a register. 9327bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { 9328 // Same encoding for add/sub, just flip the sign. 9329 int64_t AbsImm = llvm::abs64(Imm); 9330 if (!Subtarget->isThumb()) 9331 return ARM_AM::getSOImmVal(AbsImm) != -1; 9332 if (Subtarget->isThumb2()) 9333 return ARM_AM::getT2SOImmVal(AbsImm) != -1; 9334 // Thumb1 only has 8-bit unsigned immediate. 9335 return AbsImm >= 0 && AbsImm <= 255; 9336} 9337 9338static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 9339 bool isSEXTLoad, SDValue &Base, 9340 SDValue &Offset, bool &isInc, 9341 SelectionDAG &DAG) { 9342 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 9343 return false; 9344 9345 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 9346 // AddressingMode 3 9347 Base = Ptr->getOperand(0); 9348 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 9349 int RHSC = (int)RHS->getZExtValue(); 9350 if (RHSC < 0 && RHSC > -256) { 9351 assert(Ptr->getOpcode() == ISD::ADD); 9352 isInc = false; 9353 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 9354 return true; 9355 } 9356 } 9357 isInc = (Ptr->getOpcode() == ISD::ADD); 9358 Offset = Ptr->getOperand(1); 9359 return true; 9360 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 9361 // AddressingMode 2 9362 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 9363 int RHSC = (int)RHS->getZExtValue(); 9364 if (RHSC < 0 && RHSC > -0x1000) { 9365 assert(Ptr->getOpcode() == ISD::ADD); 9366 isInc = false; 9367 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 9368 Base = Ptr->getOperand(0); 9369 return true; 9370 } 9371 } 9372 9373 if (Ptr->getOpcode() == ISD::ADD) { 9374 isInc = true; 9375 ARM_AM::ShiftOpc ShOpcVal= 9376 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode()); 9377 if (ShOpcVal != ARM_AM::no_shift) { 9378 Base = Ptr->getOperand(1); 9379 Offset = Ptr->getOperand(0); 9380 } else { 9381 Base = Ptr->getOperand(0); 9382 Offset = Ptr->getOperand(1); 9383 } 9384 return true; 9385 } 9386 9387 isInc = (Ptr->getOpcode() == ISD::ADD); 9388 Base = Ptr->getOperand(0); 9389 Offset = Ptr->getOperand(1); 9390 return true; 9391 } 9392 9393 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 9394 return false; 9395} 9396 9397static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 9398 bool isSEXTLoad, SDValue &Base, 9399 SDValue &Offset, bool &isInc, 9400 SelectionDAG &DAG) { 9401 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 9402 return false; 9403 9404 Base = Ptr->getOperand(0); 9405 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 9406 int RHSC = (int)RHS->getZExtValue(); 9407 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 9408 assert(Ptr->getOpcode() == ISD::ADD); 9409 isInc = false; 9410 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 9411 return true; 9412 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 9413 isInc = Ptr->getOpcode() == ISD::ADD; 9414 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 9415 return true; 9416 } 9417 } 9418 9419 return false; 9420} 9421 9422/// getPreIndexedAddressParts - returns true by value, base pointer and 9423/// offset pointer and addressing mode by reference if the node's address 9424/// can be legally represented as pre-indexed load / store address. 9425bool 9426ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 9427 SDValue &Offset, 9428 ISD::MemIndexedMode &AM, 9429 SelectionDAG &DAG) const { 9430 if (Subtarget->isThumb1Only()) 9431 return false; 9432 9433 EVT VT; 9434 SDValue Ptr; 9435 bool isSEXTLoad = false; 9436 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 9437 Ptr = LD->getBasePtr(); 9438 VT = LD->getMemoryVT(); 9439 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 9440 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 9441 Ptr = ST->getBasePtr(); 9442 VT = ST->getMemoryVT(); 9443 } else 9444 return false; 9445 9446 bool isInc; 9447 bool isLegal = false; 9448 if (Subtarget->isThumb2()) 9449 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 9450 Offset, isInc, DAG); 9451 else 9452 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 9453 Offset, isInc, DAG); 9454 if (!isLegal) 9455 return false; 9456 9457 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 9458 return true; 9459} 9460 9461/// getPostIndexedAddressParts - returns true by value, base pointer and 9462/// offset pointer and addressing mode by reference if this node can be 9463/// combined with a load / store to form a post-indexed load / store. 9464bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 9465 SDValue &Base, 9466 SDValue &Offset, 9467 ISD::MemIndexedMode &AM, 9468 SelectionDAG &DAG) const { 9469 if (Subtarget->isThumb1Only()) 9470 return false; 9471 9472 EVT VT; 9473 SDValue Ptr; 9474 bool isSEXTLoad = false; 9475 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 9476 VT = LD->getMemoryVT(); 9477 Ptr = LD->getBasePtr(); 9478 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 9479 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 9480 VT = ST->getMemoryVT(); 9481 Ptr = ST->getBasePtr(); 9482 } else 9483 return false; 9484 9485 bool isInc; 9486 bool isLegal = false; 9487 if (Subtarget->isThumb2()) 9488 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 9489 isInc, DAG); 9490 else 9491 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 9492 isInc, DAG); 9493 if (!isLegal) 9494 return false; 9495 9496 if (Ptr != Base) { 9497 // Swap base ptr and offset to catch more post-index load / store when 9498 // it's legal. In Thumb2 mode, offset must be an immediate. 9499 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 9500 !Subtarget->isThumb2()) 9501 std::swap(Base, Offset); 9502 9503 // Post-indexed load / store update the base pointer. 9504 if (Ptr != Base) 9505 return false; 9506 } 9507 9508 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 9509 return true; 9510} 9511 9512void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 9513 APInt &KnownZero, 9514 APInt &KnownOne, 9515 const SelectionDAG &DAG, 9516 unsigned Depth) const { 9517 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 9518 switch (Op.getOpcode()) { 9519 default: break; 9520 case ARMISD::CMOV: { 9521 // Bits are known zero/one if known on the LHS and RHS. 9522 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); 9523 if (KnownZero == 0 && KnownOne == 0) return; 9524 9525 APInt KnownZeroRHS, KnownOneRHS; 9526 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1); 9527 KnownZero &= KnownZeroRHS; 9528 KnownOne &= KnownOneRHS; 9529 return; 9530 } 9531 } 9532} 9533 9534//===----------------------------------------------------------------------===// 9535// ARM Inline Assembly Support 9536//===----------------------------------------------------------------------===// 9537 9538bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { 9539 // Looking for "rev" which is V6+. 9540 if (!Subtarget->hasV6Ops()) 9541 return false; 9542 9543 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 9544 std::string AsmStr = IA->getAsmString(); 9545 SmallVector<StringRef, 4> AsmPieces; 9546 SplitString(AsmStr, AsmPieces, ";\n"); 9547 9548 switch (AsmPieces.size()) { 9549 default: return false; 9550 case 1: 9551 AsmStr = AsmPieces[0]; 9552 AsmPieces.clear(); 9553 SplitString(AsmStr, AsmPieces, " \t,"); 9554 9555 // rev $0, $1 9556 if (AsmPieces.size() == 3 && 9557 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" && 9558 IA->getConstraintString().compare(0, 4, "=l,l") == 0) { 9559 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 9560 if (Ty && Ty->getBitWidth() == 32) 9561 return IntrinsicLowering::LowerToByteSwap(CI); 9562 } 9563 break; 9564 } 9565 9566 return false; 9567} 9568 9569/// getConstraintType - Given a constraint letter, return the type of 9570/// constraint it is for this target. 9571ARMTargetLowering::ConstraintType 9572ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 9573 if (Constraint.size() == 1) { 9574 switch (Constraint[0]) { 9575 default: break; 9576 case 'l': return C_RegisterClass; 9577 case 'w': return C_RegisterClass; 9578 case 'h': return C_RegisterClass; 9579 case 'x': return C_RegisterClass; 9580 case 't': return C_RegisterClass; 9581 case 'j': return C_Other; // Constant for movw. 9582 // An address with a single base register. Due to the way we 9583 // currently handle addresses it is the same as an 'r' memory constraint. 9584 case 'Q': return C_Memory; 9585 } 9586 } else if (Constraint.size() == 2) { 9587 switch (Constraint[0]) { 9588 default: break; 9589 // All 'U+' constraints are addresses. 9590 case 'U': return C_Memory; 9591 } 9592 } 9593 return TargetLowering::getConstraintType(Constraint); 9594} 9595 9596/// Examine constraint type and operand type and determine a weight value. 9597/// This object must already have been set up with the operand type 9598/// and the current alternative constraint selected. 9599TargetLowering::ConstraintWeight 9600ARMTargetLowering::getSingleConstraintMatchWeight( 9601 AsmOperandInfo &info, const char *constraint) const { 9602 ConstraintWeight weight = CW_Invalid; 9603 Value *CallOperandVal = info.CallOperandVal; 9604 // If we don't have a value, we can't do a match, 9605 // but allow it at the lowest weight. 9606 if (CallOperandVal == NULL) 9607 return CW_Default; 9608 Type *type = CallOperandVal->getType(); 9609 // Look at the constraint type. 9610 switch (*constraint) { 9611 default: 9612 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 9613 break; 9614 case 'l': 9615 if (type->isIntegerTy()) { 9616 if (Subtarget->isThumb()) 9617 weight = CW_SpecificReg; 9618 else 9619 weight = CW_Register; 9620 } 9621 break; 9622 case 'w': 9623 if (type->isFloatingPointTy()) 9624 weight = CW_Register; 9625 break; 9626 } 9627 return weight; 9628} 9629 9630typedef std::pair<unsigned, const TargetRegisterClass*> RCPair; 9631RCPair 9632ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 9633 EVT VT) const { 9634 if (Constraint.size() == 1) { 9635 // GCC ARM Constraint Letters 9636 switch (Constraint[0]) { 9637 case 'l': // Low regs or general regs. 9638 if (Subtarget->isThumb()) 9639 return RCPair(0U, &ARM::tGPRRegClass); 9640 return RCPair(0U, &ARM::GPRRegClass); 9641 case 'h': // High regs or no regs. 9642 if (Subtarget->isThumb()) 9643 return RCPair(0U, &ARM::hGPRRegClass); 9644 break; 9645 case 'r': 9646 return RCPair(0U, &ARM::GPRRegClass); 9647 case 'w': 9648 if (VT == MVT::f32) 9649 return RCPair(0U, &ARM::SPRRegClass); 9650 if (VT.getSizeInBits() == 64) 9651 return RCPair(0U, &ARM::DPRRegClass); 9652 if (VT.getSizeInBits() == 128) 9653 return RCPair(0U, &ARM::QPRRegClass); 9654 break; 9655 case 'x': 9656 if (VT == MVT::f32) 9657 return RCPair(0U, &ARM::SPR_8RegClass); 9658 if (VT.getSizeInBits() == 64) 9659 return RCPair(0U, &ARM::DPR_8RegClass); 9660 if (VT.getSizeInBits() == 128) 9661 return RCPair(0U, &ARM::QPR_8RegClass); 9662 break; 9663 case 't': 9664 if (VT == MVT::f32) 9665 return RCPair(0U, &ARM::SPRRegClass); 9666 break; 9667 } 9668 } 9669 if (StringRef("{cc}").equals_lower(Constraint)) 9670 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass); 9671 9672 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 9673} 9674 9675/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 9676/// vector. If it is invalid, don't add anything to Ops. 9677void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 9678 std::string &Constraint, 9679 std::vector<SDValue>&Ops, 9680 SelectionDAG &DAG) const { 9681 SDValue Result(0, 0); 9682 9683 // Currently only support length 1 constraints. 9684 if (Constraint.length() != 1) return; 9685 9686 char ConstraintLetter = Constraint[0]; 9687 switch (ConstraintLetter) { 9688 default: break; 9689 case 'j': 9690 case 'I': case 'J': case 'K': case 'L': 9691 case 'M': case 'N': case 'O': 9692 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 9693 if (!C) 9694 return; 9695 9696 int64_t CVal64 = C->getSExtValue(); 9697 int CVal = (int) CVal64; 9698 // None of these constraints allow values larger than 32 bits. Check 9699 // that the value fits in an int. 9700 if (CVal != CVal64) 9701 return; 9702 9703 switch (ConstraintLetter) { 9704 case 'j': 9705 // Constant suitable for movw, must be between 0 and 9706 // 65535. 9707 if (Subtarget->hasV6T2Ops()) 9708 if (CVal >= 0 && CVal <= 65535) 9709 break; 9710 return; 9711 case 'I': 9712 if (Subtarget->isThumb1Only()) { 9713 // This must be a constant between 0 and 255, for ADD 9714 // immediates. 9715 if (CVal >= 0 && CVal <= 255) 9716 break; 9717 } else if (Subtarget->isThumb2()) { 9718 // A constant that can be used as an immediate value in a 9719 // data-processing instruction. 9720 if (ARM_AM::getT2SOImmVal(CVal) != -1) 9721 break; 9722 } else { 9723 // A constant that can be used as an immediate value in a 9724 // data-processing instruction. 9725 if (ARM_AM::getSOImmVal(CVal) != -1) 9726 break; 9727 } 9728 return; 9729 9730 case 'J': 9731 if (Subtarget->isThumb()) { // FIXME thumb2 9732 // This must be a constant between -255 and -1, for negated ADD 9733 // immediates. This can be used in GCC with an "n" modifier that 9734 // prints the negated value, for use with SUB instructions. It is 9735 // not useful otherwise but is implemented for compatibility. 9736 if (CVal >= -255 && CVal <= -1) 9737 break; 9738 } else { 9739 // This must be a constant between -4095 and 4095. It is not clear 9740 // what this constraint is intended for. Implemented for 9741 // compatibility with GCC. 9742 if (CVal >= -4095 && CVal <= 4095) 9743 break; 9744 } 9745 return; 9746 9747 case 'K': 9748 if (Subtarget->isThumb1Only()) { 9749 // A 32-bit value where only one byte has a nonzero value. Exclude 9750 // zero to match GCC. This constraint is used by GCC internally for 9751 // constants that can be loaded with a move/shift combination. 9752 // It is not useful otherwise but is implemented for compatibility. 9753 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 9754 break; 9755 } else if (Subtarget->isThumb2()) { 9756 // A constant whose bitwise inverse can be used as an immediate 9757 // value in a data-processing instruction. This can be used in GCC 9758 // with a "B" modifier that prints the inverted value, for use with 9759 // BIC and MVN instructions. It is not useful otherwise but is 9760 // implemented for compatibility. 9761 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 9762 break; 9763 } else { 9764 // A constant whose bitwise inverse can be used as an immediate 9765 // value in a data-processing instruction. This can be used in GCC 9766 // with a "B" modifier that prints the inverted value, for use with 9767 // BIC and MVN instructions. It is not useful otherwise but is 9768 // implemented for compatibility. 9769 if (ARM_AM::getSOImmVal(~CVal) != -1) 9770 break; 9771 } 9772 return; 9773 9774 case 'L': 9775 if (Subtarget->isThumb1Only()) { 9776 // This must be a constant between -7 and 7, 9777 // for 3-operand ADD/SUB immediate instructions. 9778 if (CVal >= -7 && CVal < 7) 9779 break; 9780 } else if (Subtarget->isThumb2()) { 9781 // A constant whose negation can be used as an immediate value in a 9782 // data-processing instruction. This can be used in GCC with an "n" 9783 // modifier that prints the negated value, for use with SUB 9784 // instructions. It is not useful otherwise but is implemented for 9785 // compatibility. 9786 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 9787 break; 9788 } else { 9789 // A constant whose negation can be used as an immediate value in a 9790 // data-processing instruction. This can be used in GCC with an "n" 9791 // modifier that prints the negated value, for use with SUB 9792 // instructions. It is not useful otherwise but is implemented for 9793 // compatibility. 9794 if (ARM_AM::getSOImmVal(-CVal) != -1) 9795 break; 9796 } 9797 return; 9798 9799 case 'M': 9800 if (Subtarget->isThumb()) { // FIXME thumb2 9801 // This must be a multiple of 4 between 0 and 1020, for 9802 // ADD sp + immediate. 9803 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 9804 break; 9805 } else { 9806 // A power of two or a constant between 0 and 32. This is used in 9807 // GCC for the shift amount on shifted register operands, but it is 9808 // useful in general for any shift amounts. 9809 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 9810 break; 9811 } 9812 return; 9813 9814 case 'N': 9815 if (Subtarget->isThumb()) { // FIXME thumb2 9816 // This must be a constant between 0 and 31, for shift amounts. 9817 if (CVal >= 0 && CVal <= 31) 9818 break; 9819 } 9820 return; 9821 9822 case 'O': 9823 if (Subtarget->isThumb()) { // FIXME thumb2 9824 // This must be a multiple of 4 between -508 and 508, for 9825 // ADD/SUB sp = sp + immediate. 9826 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 9827 break; 9828 } 9829 return; 9830 } 9831 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 9832 break; 9833 } 9834 9835 if (Result.getNode()) { 9836 Ops.push_back(Result); 9837 return; 9838 } 9839 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 9840} 9841 9842bool 9843ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 9844 // The ARM target isn't yet aware of offsets. 9845 return false; 9846} 9847 9848bool ARM::isBitFieldInvertedMask(unsigned v) { 9849 if (v == 0xffffffff) 9850 return 0; 9851 // there can be 1's on either or both "outsides", all the "inside" 9852 // bits must be 0's 9853 unsigned int lsb = 0, msb = 31; 9854 while (v & (1 << msb)) --msb; 9855 while (v & (1 << lsb)) ++lsb; 9856 for (unsigned int i = lsb; i <= msb; ++i) { 9857 if (v & (1 << i)) 9858 return 0; 9859 } 9860 return 1; 9861} 9862 9863/// isFPImmLegal - Returns true if the target can instruction select the 9864/// specified FP immediate natively. If false, the legalizer will 9865/// materialize the FP immediate as a load from a constant pool. 9866bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 9867 if (!Subtarget->hasVFP3()) 9868 return false; 9869 if (VT == MVT::f32) 9870 return ARM_AM::getFP32Imm(Imm) != -1; 9871 if (VT == MVT::f64) 9872 return ARM_AM::getFP64Imm(Imm) != -1; 9873 return false; 9874} 9875 9876/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 9877/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 9878/// specified in the intrinsic calls. 9879bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 9880 const CallInst &I, 9881 unsigned Intrinsic) const { 9882 switch (Intrinsic) { 9883 case Intrinsic::arm_neon_vld1: 9884 case Intrinsic::arm_neon_vld2: 9885 case Intrinsic::arm_neon_vld3: 9886 case Intrinsic::arm_neon_vld4: 9887 case Intrinsic::arm_neon_vld2lane: 9888 case Intrinsic::arm_neon_vld3lane: 9889 case Intrinsic::arm_neon_vld4lane: { 9890 Info.opc = ISD::INTRINSIC_W_CHAIN; 9891 // Conservatively set memVT to the entire set of vectors loaded. 9892 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8; 9893 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 9894 Info.ptrVal = I.getArgOperand(0); 9895 Info.offset = 0; 9896 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 9897 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 9898 Info.vol = false; // volatile loads with NEON intrinsics not supported 9899 Info.readMem = true; 9900 Info.writeMem = false; 9901 return true; 9902 } 9903 case Intrinsic::arm_neon_vst1: 9904 case Intrinsic::arm_neon_vst2: 9905 case Intrinsic::arm_neon_vst3: 9906 case Intrinsic::arm_neon_vst4: 9907 case Intrinsic::arm_neon_vst2lane: 9908 case Intrinsic::arm_neon_vst3lane: 9909 case Intrinsic::arm_neon_vst4lane: { 9910 Info.opc = ISD::INTRINSIC_VOID; 9911 // Conservatively set memVT to the entire set of vectors stored. 9912 unsigned NumElts = 0; 9913 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 9914 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 9915 if (!ArgTy->isVectorTy()) 9916 break; 9917 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8; 9918 } 9919 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 9920 Info.ptrVal = I.getArgOperand(0); 9921 Info.offset = 0; 9922 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 9923 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 9924 Info.vol = false; // volatile stores with NEON intrinsics not supported 9925 Info.readMem = false; 9926 Info.writeMem = true; 9927 return true; 9928 } 9929 case Intrinsic::arm_strexd: { 9930 Info.opc = ISD::INTRINSIC_W_CHAIN; 9931 Info.memVT = MVT::i64; 9932 Info.ptrVal = I.getArgOperand(2); 9933 Info.offset = 0; 9934 Info.align = 8; 9935 Info.vol = true; 9936 Info.readMem = false; 9937 Info.writeMem = true; 9938 return true; 9939 } 9940 case Intrinsic::arm_ldrexd: { 9941 Info.opc = ISD::INTRINSIC_W_CHAIN; 9942 Info.memVT = MVT::i64; 9943 Info.ptrVal = I.getArgOperand(0); 9944 Info.offset = 0; 9945 Info.align = 8; 9946 Info.vol = true; 9947 Info.readMem = true; 9948 Info.writeMem = false; 9949 return true; 9950 } 9951 default: 9952 break; 9953 } 9954 9955 return false; 9956} 9957