1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "mips-lower"
16#include "MipsISelLowering.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "MipsTargetObjectFile.h"
20#include "MipsSubtarget.h"
21#include "InstPrinter/MipsInstPrinter.h"
22#include "MCTargetDesc/MipsBaseInfo.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/Intrinsics.h"
27#include "llvm/CallingConv.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38
39using namespace llvm;
40
41// If I is a shifted mask, set the size (Size) and the first bit of the
42// mask (Pos), and return true.
43// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
44static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
45  if (!isShiftedMask_64(I))
46     return false;
47
48  Size = CountPopulation_64(I);
49  Pos = CountTrailingZeros_64(I);
50  return true;
51}
52
53static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
54  MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55  return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
56}
57
58const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
59  switch (Opcode) {
60  case MipsISD::JmpLink:           return "MipsISD::JmpLink";
61  case MipsISD::Hi:                return "MipsISD::Hi";
62  case MipsISD::Lo:                return "MipsISD::Lo";
63  case MipsISD::GPRel:             return "MipsISD::GPRel";
64  case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
65  case MipsISD::Ret:               return "MipsISD::Ret";
66  case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
67  case MipsISD::FPCmp:             return "MipsISD::FPCmp";
68  case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
69  case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
70  case MipsISD::FPRound:           return "MipsISD::FPRound";
71  case MipsISD::MAdd:              return "MipsISD::MAdd";
72  case MipsISD::MAddu:             return "MipsISD::MAddu";
73  case MipsISD::MSub:              return "MipsISD::MSub";
74  case MipsISD::MSubu:             return "MipsISD::MSubu";
75  case MipsISD::DivRem:            return "MipsISD::DivRem";
76  case MipsISD::DivRemU:           return "MipsISD::DivRemU";
77  case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
78  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
79  case MipsISD::Wrapper:           return "MipsISD::Wrapper";
80  case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
81  case MipsISD::Sync:              return "MipsISD::Sync";
82  case MipsISD::Ext:               return "MipsISD::Ext";
83  case MipsISD::Ins:               return "MipsISD::Ins";
84  case MipsISD::LWL:               return "MipsISD::LWL";
85  case MipsISD::LWR:               return "MipsISD::LWR";
86  case MipsISD::SWL:               return "MipsISD::SWL";
87  case MipsISD::SWR:               return "MipsISD::SWR";
88  case MipsISD::LDL:               return "MipsISD::LDL";
89  case MipsISD::LDR:               return "MipsISD::LDR";
90  case MipsISD::SDL:               return "MipsISD::SDL";
91  case MipsISD::SDR:               return "MipsISD::SDR";
92  case MipsISD::EXTP:              return "MipsISD::EXTP";
93  case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
94  case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
95  case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
96  case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
97  case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
98  case MipsISD::SHILO:             return "MipsISD::SHILO";
99  case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
100  case MipsISD::MULT:              return "MipsISD::MULT";
101  case MipsISD::MULTU:             return "MipsISD::MULTU";
102  case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSPDSP";
103  case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
104  case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
105  case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
106  default:                         return NULL;
107  }
108}
109
110MipsTargetLowering::
111MipsTargetLowering(MipsTargetMachine &TM)
112  : TargetLowering(TM, new MipsTargetObjectFile()),
113    Subtarget(&TM.getSubtarget<MipsSubtarget>()),
114    HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
115    IsO32(Subtarget->isABI_O32()) {
116
117  // Mips does not have i1 type, so use i32 for
118  // setcc operations results (slt, sgt, ...).
119  setBooleanContents(ZeroOrOneBooleanContent);
120  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
121
122  // Set up the register classes
123  addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
124
125  if (HasMips64)
126    addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
127
128  if (Subtarget->inMips16Mode()) {
129    addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
130  }
131
132  if (Subtarget->hasDSP()) {
133    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
134
135    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
136      addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
137
138      // Expand all builtin opcodes.
139      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
140        setOperationAction(Opc, VecTys[i], Expand);
141
142      setOperationAction(ISD::LOAD, VecTys[i], Legal);
143      setOperationAction(ISD::STORE, VecTys[i], Legal);
144      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
145    }
146  }
147
148  if (!TM.Options.UseSoftFloat) {
149    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
150
151    // When dealing with single precision only, use libcalls
152    if (!Subtarget->isSingleFloat()) {
153      if (HasMips64)
154        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
155      else
156        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
157    }
158  }
159
160  // Load extented operations for i1 types must be promoted
161  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
162  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
163  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
164
165  // MIPS doesn't have extending float->double load/store
166  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
167  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
168
169  // Used by legalize types to correctly generate the setcc result.
170  // Without this, every float setcc comes with a AND/OR with the result,
171  // we don't want this, since the fpcmp result goes to a flag register,
172  // which is used implicitly by brcond and select operations.
173  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
174
175  // Mips Custom Operations
176  setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
177  setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
178  setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
179  setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
180  setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
181  setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
182  setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
183  setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
184  setOperationAction(ISD::SELECT_CC,          MVT::f32,   Custom);
185  setOperationAction(ISD::SELECT_CC,          MVT::f64,   Custom);
186  setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
187  setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
188  setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
189  setOperationAction(ISD::VASTART,            MVT::Other, Custom);
190  setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
191  setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
192  setOperationAction(ISD::MEMBARRIER,         MVT::Other, Custom);
193  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
194  if (!Subtarget->inMips16Mode()) {
195    setOperationAction(ISD::LOAD,               MVT::i32, Custom);
196    setOperationAction(ISD::STORE,              MVT::i32, Custom);
197  }
198
199  if (!TM.Options.NoNaNsFPMath) {
200    setOperationAction(ISD::FABS,             MVT::f32,   Custom);
201    setOperationAction(ISD::FABS,             MVT::f64,   Custom);
202  }
203
204  if (HasMips64) {
205    setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
206    setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
207    setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
208    setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
209    setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
210    setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
211    setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
212    setOperationAction(ISD::STORE,              MVT::i64,   Custom);
213  }
214
215  if (!HasMips64) {
216    setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
217    setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
218    setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
219  }
220
221  setOperationAction(ISD::SDIV, MVT::i32, Expand);
222  setOperationAction(ISD::SREM, MVT::i32, Expand);
223  setOperationAction(ISD::UDIV, MVT::i32, Expand);
224  setOperationAction(ISD::UREM, MVT::i32, Expand);
225  setOperationAction(ISD::SDIV, MVT::i64, Expand);
226  setOperationAction(ISD::SREM, MVT::i64, Expand);
227  setOperationAction(ISD::UDIV, MVT::i64, Expand);
228  setOperationAction(ISD::UREM, MVT::i64, Expand);
229
230  // Operations not directly supported by Mips.
231  setOperationAction(ISD::BR_JT,             MVT::Other, Expand);
232  setOperationAction(ISD::BR_CC,             MVT::Other, Expand);
233  setOperationAction(ISD::SELECT_CC,         MVT::Other, Expand);
234  setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
235  setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
236  setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
237  setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
238  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
239  setOperationAction(ISD::CTPOP,             MVT::i32,   Expand);
240  setOperationAction(ISD::CTPOP,             MVT::i64,   Expand);
241  setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
242  setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
243  setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i32,   Expand);
244  setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i64,   Expand);
245  setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i32,   Expand);
246  setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i64,   Expand);
247  setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
248  setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
249  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
250  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
251
252  if (!Subtarget->hasMips32r2())
253    setOperationAction(ISD::ROTR, MVT::i32,   Expand);
254
255  if (!Subtarget->hasMips64r2())
256    setOperationAction(ISD::ROTR, MVT::i64,   Expand);
257
258  setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
259  setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
260  setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
261  setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
262  setOperationAction(ISD::FPOWI,             MVT::f32,   Expand);
263  setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
264  setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
265  setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
266  setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
267  setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
268  setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
269  setOperationAction(ISD::FMA,               MVT::f32,   Expand);
270  setOperationAction(ISD::FMA,               MVT::f64,   Expand);
271  setOperationAction(ISD::FREM,              MVT::f32,   Expand);
272  setOperationAction(ISD::FREM,              MVT::f64,   Expand);
273
274  if (!TM.Options.NoNaNsFPMath) {
275    setOperationAction(ISD::FNEG,             MVT::f32,   Expand);
276    setOperationAction(ISD::FNEG,             MVT::f64,   Expand);
277  }
278
279  setOperationAction(ISD::EXCEPTIONADDR,     MVT::i32, Expand);
280  setOperationAction(ISD::EXCEPTIONADDR,     MVT::i64, Expand);
281  setOperationAction(ISD::EHSELECTION,       MVT::i32, Expand);
282  setOperationAction(ISD::EHSELECTION,       MVT::i64, Expand);
283
284  setOperationAction(ISD::VAARG,             MVT::Other, Expand);
285  setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
286  setOperationAction(ISD::VAEND,             MVT::Other, Expand);
287
288  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
289  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
290
291  // Use the default for now
292  setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
293  setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
294
295  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i32,    Expand);
296  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i64,    Expand);
297  setOperationAction(ISD::ATOMIC_STORE,      MVT::i32,    Expand);
298  setOperationAction(ISD::ATOMIC_STORE,      MVT::i64,    Expand);
299
300  setInsertFencesForAtomic(true);
301
302  if (!Subtarget->hasSEInReg()) {
303    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
304    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
305  }
306
307  if (!Subtarget->hasBitCount()) {
308    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
309    setOperationAction(ISD::CTLZ, MVT::i64, Expand);
310  }
311
312  if (!Subtarget->hasSwap()) {
313    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
314    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
315  }
316
317  if (HasMips64) {
318    setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
319    setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
320    setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
321    setTruncStoreAction(MVT::i64, MVT::i32, Custom);
322  }
323
324  setTargetDAGCombine(ISD::ADDE);
325  setTargetDAGCombine(ISD::SUBE);
326  setTargetDAGCombine(ISD::SDIVREM);
327  setTargetDAGCombine(ISD::UDIVREM);
328  setTargetDAGCombine(ISD::SELECT);
329  setTargetDAGCombine(ISD::AND);
330  setTargetDAGCombine(ISD::OR);
331  setTargetDAGCombine(ISD::ADD);
332
333  setMinFunctionAlignment(HasMips64 ? 3 : 2);
334
335  setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
336  computeRegisterProperties();
337
338  setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
339  setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
340
341  maxStoresPerMemcpy = 16;
342}
343
344bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
345  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
346
347  if (Subtarget->inMips16Mode())
348    return false;
349
350  switch (SVT) {
351  case MVT::i64:
352  case MVT::i32:
353    return true;
354  default:
355    return false;
356  }
357}
358
359EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
360  return MVT::i32;
361}
362
363// SelectMadd -
364// Transforms a subgraph in CurDAG if the following pattern is found:
365//  (addc multLo, Lo0), (adde multHi, Hi0),
366// where,
367//  multHi/Lo: product of multiplication
368//  Lo0: initial value of Lo register
369//  Hi0: initial value of Hi register
370// Return true if pattern matching was successful.
371static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
372  // ADDENode's second operand must be a flag output of an ADDC node in order
373  // for the matching to be successful.
374  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
375
376  if (ADDCNode->getOpcode() != ISD::ADDC)
377    return false;
378
379  SDValue MultHi = ADDENode->getOperand(0);
380  SDValue MultLo = ADDCNode->getOperand(0);
381  SDNode *MultNode = MultHi.getNode();
382  unsigned MultOpc = MultHi.getOpcode();
383
384  // MultHi and MultLo must be generated by the same node,
385  if (MultLo.getNode() != MultNode)
386    return false;
387
388  // and it must be a multiplication.
389  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
390    return false;
391
392  // MultLo amd MultHi must be the first and second output of MultNode
393  // respectively.
394  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
395    return false;
396
397  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
398  // of the values of MultNode, in which case MultNode will be removed in later
399  // phases.
400  // If there exist users other than ADDENode or ADDCNode, this function returns
401  // here, which will result in MultNode being mapped to a single MULT
402  // instruction node rather than a pair of MULT and MADD instructions being
403  // produced.
404  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
405    return false;
406
407  SDValue Chain = CurDAG->getEntryNode();
408  DebugLoc dl = ADDENode->getDebugLoc();
409
410  // create MipsMAdd(u) node
411  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
412
413  SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
414                                 MultNode->getOperand(0),// Factor 0
415                                 MultNode->getOperand(1),// Factor 1
416                                 ADDCNode->getOperand(1),// Lo0
417                                 ADDENode->getOperand(1));// Hi0
418
419  // create CopyFromReg nodes
420  SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
421                                              MAdd);
422  SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
423                                              Mips::HI, MVT::i32,
424                                              CopyFromLo.getValue(2));
425
426  // replace uses of adde and addc here
427  if (!SDValue(ADDCNode, 0).use_empty())
428    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
429
430  if (!SDValue(ADDENode, 0).use_empty())
431    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
432
433  return true;
434}
435
436// SelectMsub -
437// Transforms a subgraph in CurDAG if the following pattern is found:
438//  (addc Lo0, multLo), (sube Hi0, multHi),
439// where,
440//  multHi/Lo: product of multiplication
441//  Lo0: initial value of Lo register
442//  Hi0: initial value of Hi register
443// Return true if pattern matching was successful.
444static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
445  // SUBENode's second operand must be a flag output of an SUBC node in order
446  // for the matching to be successful.
447  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
448
449  if (SUBCNode->getOpcode() != ISD::SUBC)
450    return false;
451
452  SDValue MultHi = SUBENode->getOperand(1);
453  SDValue MultLo = SUBCNode->getOperand(1);
454  SDNode *MultNode = MultHi.getNode();
455  unsigned MultOpc = MultHi.getOpcode();
456
457  // MultHi and MultLo must be generated by the same node,
458  if (MultLo.getNode() != MultNode)
459    return false;
460
461  // and it must be a multiplication.
462  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
463    return false;
464
465  // MultLo amd MultHi must be the first and second output of MultNode
466  // respectively.
467  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
468    return false;
469
470  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
471  // of the values of MultNode, in which case MultNode will be removed in later
472  // phases.
473  // If there exist users other than SUBENode or SUBCNode, this function returns
474  // here, which will result in MultNode being mapped to a single MULT
475  // instruction node rather than a pair of MULT and MSUB instructions being
476  // produced.
477  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
478    return false;
479
480  SDValue Chain = CurDAG->getEntryNode();
481  DebugLoc dl = SUBENode->getDebugLoc();
482
483  // create MipsSub(u) node
484  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
485
486  SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
487                                 MultNode->getOperand(0),// Factor 0
488                                 MultNode->getOperand(1),// Factor 1
489                                 SUBCNode->getOperand(0),// Lo0
490                                 SUBENode->getOperand(0));// Hi0
491
492  // create CopyFromReg nodes
493  SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
494                                              MSub);
495  SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
496                                              Mips::HI, MVT::i32,
497                                              CopyFromLo.getValue(2));
498
499  // replace uses of sube and subc here
500  if (!SDValue(SUBCNode, 0).use_empty())
501    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
502
503  if (!SDValue(SUBENode, 0).use_empty())
504    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
505
506  return true;
507}
508
509static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
510                                  TargetLowering::DAGCombinerInfo &DCI,
511                                  const MipsSubtarget *Subtarget) {
512  if (DCI.isBeforeLegalize())
513    return SDValue();
514
515  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
516      SelectMadd(N, &DAG))
517    return SDValue(N, 0);
518
519  return SDValue();
520}
521
522static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
523                                  TargetLowering::DAGCombinerInfo &DCI,
524                                  const MipsSubtarget *Subtarget) {
525  if (DCI.isBeforeLegalize())
526    return SDValue();
527
528  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
529      SelectMsub(N, &DAG))
530    return SDValue(N, 0);
531
532  return SDValue();
533}
534
535static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
536                                    TargetLowering::DAGCombinerInfo &DCI,
537                                    const MipsSubtarget *Subtarget) {
538  if (DCI.isBeforeLegalizeOps())
539    return SDValue();
540
541  EVT Ty = N->getValueType(0);
542  unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
543  unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
544  unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
545                                                  MipsISD::DivRemU;
546  DebugLoc dl = N->getDebugLoc();
547
548  SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
549                               N->getOperand(0), N->getOperand(1));
550  SDValue InChain = DAG.getEntryNode();
551  SDValue InGlue = DivRem;
552
553  // insert MFLO
554  if (N->hasAnyUseOfValue(0)) {
555    SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
556                                            InGlue);
557    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
558    InChain = CopyFromLo.getValue(1);
559    InGlue = CopyFromLo.getValue(2);
560  }
561
562  // insert MFHI
563  if (N->hasAnyUseOfValue(1)) {
564    SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
565                                            HI, Ty, InGlue);
566    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
567  }
568
569  return SDValue();
570}
571
572static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
573  switch (CC) {
574  default: llvm_unreachable("Unknown fp condition code!");
575  case ISD::SETEQ:
576  case ISD::SETOEQ: return Mips::FCOND_OEQ;
577  case ISD::SETUNE: return Mips::FCOND_UNE;
578  case ISD::SETLT:
579  case ISD::SETOLT: return Mips::FCOND_OLT;
580  case ISD::SETGT:
581  case ISD::SETOGT: return Mips::FCOND_OGT;
582  case ISD::SETLE:
583  case ISD::SETOLE: return Mips::FCOND_OLE;
584  case ISD::SETGE:
585  case ISD::SETOGE: return Mips::FCOND_OGE;
586  case ISD::SETULT: return Mips::FCOND_ULT;
587  case ISD::SETULE: return Mips::FCOND_ULE;
588  case ISD::SETUGT: return Mips::FCOND_UGT;
589  case ISD::SETUGE: return Mips::FCOND_UGE;
590  case ISD::SETUO:  return Mips::FCOND_UN;
591  case ISD::SETO:   return Mips::FCOND_OR;
592  case ISD::SETNE:
593  case ISD::SETONE: return Mips::FCOND_ONE;
594  case ISD::SETUEQ: return Mips::FCOND_UEQ;
595  }
596}
597
598
599// Returns true if condition code has to be inverted.
600static bool InvertFPCondCode(Mips::CondCode CC) {
601  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
602    return false;
603
604  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
605         "Illegal Condition Code");
606
607  return true;
608}
609
610// Creates and returns an FPCmp node from a setcc node.
611// Returns Op if setcc is not a floating point comparison.
612static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
613  // must be a SETCC node
614  if (Op.getOpcode() != ISD::SETCC)
615    return Op;
616
617  SDValue LHS = Op.getOperand(0);
618
619  if (!LHS.getValueType().isFloatingPoint())
620    return Op;
621
622  SDValue RHS = Op.getOperand(1);
623  DebugLoc dl = Op.getDebugLoc();
624
625  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
626  // node if necessary.
627  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
628
629  return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
630                     DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
631}
632
633// Creates and returns a CMovFPT/F node.
634static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
635                            SDValue False, DebugLoc DL) {
636  bool invert = InvertFPCondCode((Mips::CondCode)
637                                 cast<ConstantSDNode>(Cond.getOperand(2))
638                                 ->getSExtValue());
639
640  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
641                     True.getValueType(), True, False, Cond);
642}
643
644static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
645                                    TargetLowering::DAGCombinerInfo &DCI,
646                                    const MipsSubtarget *Subtarget) {
647  if (DCI.isBeforeLegalizeOps())
648    return SDValue();
649
650  SDValue SetCC = N->getOperand(0);
651
652  if ((SetCC.getOpcode() != ISD::SETCC) ||
653      !SetCC.getOperand(0).getValueType().isInteger())
654    return SDValue();
655
656  SDValue False = N->getOperand(2);
657  EVT FalseTy = False.getValueType();
658
659  if (!FalseTy.isInteger())
660    return SDValue();
661
662  ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
663
664  if (!CN || CN->getZExtValue())
665    return SDValue();
666
667  const DebugLoc DL = N->getDebugLoc();
668  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
669  SDValue True = N->getOperand(1);
670
671  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
672                       SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
673
674  return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
675}
676
677static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
678                                 TargetLowering::DAGCombinerInfo &DCI,
679                                 const MipsSubtarget *Subtarget) {
680  // Pattern match EXT.
681  //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
682  //  => ext $dst, $src, size, pos
683  if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
684    return SDValue();
685
686  SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
687  unsigned ShiftRightOpc = ShiftRight.getOpcode();
688
689  // Op's first operand must be a shift right.
690  if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
691    return SDValue();
692
693  // The second operand of the shift must be an immediate.
694  ConstantSDNode *CN;
695  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
696    return SDValue();
697
698  uint64_t Pos = CN->getZExtValue();
699  uint64_t SMPos, SMSize;
700
701  // Op's second operand must be a shifted mask.
702  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
703      !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
704    return SDValue();
705
706  // Return if the shifted mask does not start at bit 0 or the sum of its size
707  // and Pos exceeds the word's size.
708  EVT ValTy = N->getValueType(0);
709  if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
710    return SDValue();
711
712  return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
713                     ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
714                     DAG.getConstant(SMSize, MVT::i32));
715}
716
717static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
718                                TargetLowering::DAGCombinerInfo &DCI,
719                                const MipsSubtarget *Subtarget) {
720  // Pattern match INS.
721  //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
722  //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
723  //  => ins $dst, $src, size, pos, $src1
724  if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
725    return SDValue();
726
727  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
728  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
729  ConstantSDNode *CN;
730
731  // See if Op's first operand matches (and $src1 , mask0).
732  if (And0.getOpcode() != ISD::AND)
733    return SDValue();
734
735  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
736      !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
737    return SDValue();
738
739  // See if Op's second operand matches (and (shl $src, pos), mask1).
740  if (And1.getOpcode() != ISD::AND)
741    return SDValue();
742
743  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
744      !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
745    return SDValue();
746
747  // The shift masks must have the same position and size.
748  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
749    return SDValue();
750
751  SDValue Shl = And1.getOperand(0);
752  if (Shl.getOpcode() != ISD::SHL)
753    return SDValue();
754
755  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
756    return SDValue();
757
758  unsigned Shamt = CN->getZExtValue();
759
760  // Return if the shift amount and the first bit position of mask are not the
761  // same.
762  EVT ValTy = N->getValueType(0);
763  if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
764    return SDValue();
765
766  return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
767                     DAG.getConstant(SMPos0, MVT::i32),
768                     DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
769}
770
771static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
772                                 TargetLowering::DAGCombinerInfo &DCI,
773                                 const MipsSubtarget *Subtarget) {
774  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
775
776  if (DCI.isBeforeLegalizeOps())
777    return SDValue();
778
779  SDValue Add = N->getOperand(1);
780
781  if (Add.getOpcode() != ISD::ADD)
782    return SDValue();
783
784  SDValue Lo = Add.getOperand(1);
785
786  if ((Lo.getOpcode() != MipsISD::Lo) ||
787      (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
788    return SDValue();
789
790  EVT ValTy = N->getValueType(0);
791  DebugLoc DL = N->getDebugLoc();
792
793  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
794                             Add.getOperand(0));
795  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
796}
797
798SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
799  const {
800  SelectionDAG &DAG = DCI.DAG;
801  unsigned opc = N->getOpcode();
802
803  switch (opc) {
804  default: break;
805  case ISD::ADDE:
806    return PerformADDECombine(N, DAG, DCI, Subtarget);
807  case ISD::SUBE:
808    return PerformSUBECombine(N, DAG, DCI, Subtarget);
809  case ISD::SDIVREM:
810  case ISD::UDIVREM:
811    return PerformDivRemCombine(N, DAG, DCI, Subtarget);
812  case ISD::SELECT:
813    return PerformSELECTCombine(N, DAG, DCI, Subtarget);
814  case ISD::AND:
815    return PerformANDCombine(N, DAG, DCI, Subtarget);
816  case ISD::OR:
817    return PerformORCombine(N, DAG, DCI, Subtarget);
818  case ISD::ADD:
819    return PerformADDCombine(N, DAG, DCI, Subtarget);
820  }
821
822  return SDValue();
823}
824
825void
826MipsTargetLowering::LowerOperationWrapper(SDNode *N,
827                                          SmallVectorImpl<SDValue> &Results,
828                                          SelectionDAG &DAG) const {
829  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
830
831  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
832    Results.push_back(Res.getValue(I));
833}
834
835void
836MipsTargetLowering::ReplaceNodeResults(SDNode *N,
837                                       SmallVectorImpl<SDValue> &Results,
838                                       SelectionDAG &DAG) const {
839  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
840
841  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
842    Results.push_back(Res.getValue(I));
843}
844
845SDValue MipsTargetLowering::
846LowerOperation(SDValue Op, SelectionDAG &DAG) const
847{
848  switch (Op.getOpcode())
849  {
850    case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
851    case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
852    case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
853    case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
854    case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
855    case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
856    case ISD::SELECT:             return LowerSELECT(Op, DAG);
857    case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
858    case ISD::SETCC:              return LowerSETCC(Op, DAG);
859    case ISD::VASTART:            return LowerVASTART(Op, DAG);
860    case ISD::FCOPYSIGN:          return LowerFCOPYSIGN(Op, DAG);
861    case ISD::FABS:               return LowerFABS(Op, DAG);
862    case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
863    case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG);
864    case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
865    case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
866    case ISD::SHL_PARTS:          return LowerShiftLeftParts(Op, DAG);
867    case ISD::SRA_PARTS:          return LowerShiftRightParts(Op, DAG, true);
868    case ISD::SRL_PARTS:          return LowerShiftRightParts(Op, DAG, false);
869    case ISD::LOAD:               return LowerLOAD(Op, DAG);
870    case ISD::STORE:              return LowerSTORE(Op, DAG);
871    case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
872    case ISD::INTRINSIC_W_CHAIN:  return LowerINTRINSIC_W_CHAIN(Op, DAG);
873  }
874  return SDValue();
875}
876
877//===----------------------------------------------------------------------===//
878//  Lower helper functions
879//===----------------------------------------------------------------------===//
880
881// AddLiveIn - This helper function adds the specified physical register to the
882// MachineFunction as a live in value.  It also creates a corresponding
883// virtual register for it.
884static unsigned
885AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
886{
887  assert(RC->contains(PReg) && "Not the correct regclass!");
888  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
889  MF.getRegInfo().addLiveIn(PReg, VReg);
890  return VReg;
891}
892
893// Get fp branch code (not opcode) from condition code.
894static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
895  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
896    return Mips::BRANCH_T;
897
898  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
899         "Invalid CondCode.");
900
901  return Mips::BRANCH_F;
902}
903
904/*
905static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
906                                        DebugLoc dl,
907                                        const MipsSubtarget *Subtarget,
908                                        const TargetInstrInfo *TII,
909                                        bool isFPCmp, unsigned Opc) {
910  // There is no need to expand CMov instructions if target has
911  // conditional moves.
912  if (Subtarget->hasCondMov())
913    return BB;
914
915  // To "insert" a SELECT_CC instruction, we actually have to insert the
916  // diamond control-flow pattern.  The incoming instruction knows the
917  // destination vreg to set, the condition code register to branch on, the
918  // true/false values to select between, and a branch opcode to use.
919  const BasicBlock *LLVM_BB = BB->getBasicBlock();
920  MachineFunction::iterator It = BB;
921  ++It;
922
923  //  thisMBB:
924  //  ...
925  //   TrueVal = ...
926  //   setcc r1, r2, r3
927  //   bNE   r1, r0, copy1MBB
928  //   fallthrough --> copy0MBB
929  MachineBasicBlock *thisMBB  = BB;
930  MachineFunction *F = BB->getParent();
931  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
932  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
933  F->insert(It, copy0MBB);
934  F->insert(It, sinkMBB);
935
936  // Transfer the remainder of BB and its successor edges to sinkMBB.
937  sinkMBB->splice(sinkMBB->begin(), BB,
938                  llvm::next(MachineBasicBlock::iterator(MI)),
939                  BB->end());
940  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
941
942  // Next, add the true and fallthrough blocks as its successors.
943  BB->addSuccessor(copy0MBB);
944  BB->addSuccessor(sinkMBB);
945
946  // Emit the right instruction according to the type of the operands compared
947  if (isFPCmp)
948    BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
949  else
950    BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
951      .addReg(Mips::ZERO).addMBB(sinkMBB);
952
953  //  copy0MBB:
954  //   %FalseValue = ...
955  //   # fallthrough to sinkMBB
956  BB = copy0MBB;
957
958  // Update machine-CFG edges
959  BB->addSuccessor(sinkMBB);
960
961  //  sinkMBB:
962  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
963  //  ...
964  BB = sinkMBB;
965
966  if (isFPCmp)
967    BuildMI(*BB, BB->begin(), dl,
968            TII->get(Mips::PHI), MI->getOperand(0).getReg())
969      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
970      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
971  else
972    BuildMI(*BB, BB->begin(), dl,
973            TII->get(Mips::PHI), MI->getOperand(0).getReg())
974      .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
975      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
976
977  MI->eraseFromParent();   // The pseudo instruction is gone now.
978  return BB;
979}
980*/
981
982MachineBasicBlock *
983MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
984  // $bb:
985  //  bposge32_pseudo $vr0
986  //  =>
987  // $bb:
988  //  bposge32 $tbb
989  // $fbb:
990  //  li $vr2, 0
991  //  b $sink
992  // $tbb:
993  //  li $vr1, 1
994  // $sink:
995  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
996
997  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
998  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
999  const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
1000  DebugLoc DL = MI->getDebugLoc();
1001  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1002  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1003  MachineFunction *F = BB->getParent();
1004  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1005  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1006  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1007  F->insert(It, FBB);
1008  F->insert(It, TBB);
1009  F->insert(It, Sink);
1010
1011  // Transfer the remainder of BB and its successor edges to Sink.
1012  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1013               BB->end());
1014  Sink->transferSuccessorsAndUpdatePHIs(BB);
1015
1016  // Add successors.
1017  BB->addSuccessor(FBB);
1018  BB->addSuccessor(TBB);
1019  FBB->addSuccessor(Sink);
1020  TBB->addSuccessor(Sink);
1021
1022  // Insert the real bposge32 instruction to $BB.
1023  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1024
1025  // Fill $FBB.
1026  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1027  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1028    .addReg(Mips::ZERO).addImm(0);
1029  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1030
1031  // Fill $TBB.
1032  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1033  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1034    .addReg(Mips::ZERO).addImm(1);
1035
1036  // Insert phi function to $Sink.
1037  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1038          MI->getOperand(0).getReg())
1039    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1040
1041  MI->eraseFromParent();   // The pseudo instruction is gone now.
1042  return Sink;
1043}
1044
1045MachineBasicBlock *
1046MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1047                                                MachineBasicBlock *BB) const {
1048  switch (MI->getOpcode()) {
1049  default: llvm_unreachable("Unexpected instr type to insert");
1050  case Mips::ATOMIC_LOAD_ADD_I8:
1051  case Mips::ATOMIC_LOAD_ADD_I8_P8:
1052    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1053  case Mips::ATOMIC_LOAD_ADD_I16:
1054  case Mips::ATOMIC_LOAD_ADD_I16_P8:
1055    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1056  case Mips::ATOMIC_LOAD_ADD_I32:
1057  case Mips::ATOMIC_LOAD_ADD_I32_P8:
1058    return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
1059  case Mips::ATOMIC_LOAD_ADD_I64:
1060  case Mips::ATOMIC_LOAD_ADD_I64_P8:
1061    return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
1062
1063  case Mips::ATOMIC_LOAD_AND_I8:
1064  case Mips::ATOMIC_LOAD_AND_I8_P8:
1065    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1066  case Mips::ATOMIC_LOAD_AND_I16:
1067  case Mips::ATOMIC_LOAD_AND_I16_P8:
1068    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1069  case Mips::ATOMIC_LOAD_AND_I32:
1070  case Mips::ATOMIC_LOAD_AND_I32_P8:
1071    return EmitAtomicBinary(MI, BB, 4, Mips::AND);
1072  case Mips::ATOMIC_LOAD_AND_I64:
1073  case Mips::ATOMIC_LOAD_AND_I64_P8:
1074    return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
1075
1076  case Mips::ATOMIC_LOAD_OR_I8:
1077  case Mips::ATOMIC_LOAD_OR_I8_P8:
1078    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1079  case Mips::ATOMIC_LOAD_OR_I16:
1080  case Mips::ATOMIC_LOAD_OR_I16_P8:
1081    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1082  case Mips::ATOMIC_LOAD_OR_I32:
1083  case Mips::ATOMIC_LOAD_OR_I32_P8:
1084    return EmitAtomicBinary(MI, BB, 4, Mips::OR);
1085  case Mips::ATOMIC_LOAD_OR_I64:
1086  case Mips::ATOMIC_LOAD_OR_I64_P8:
1087    return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
1088
1089  case Mips::ATOMIC_LOAD_XOR_I8:
1090  case Mips::ATOMIC_LOAD_XOR_I8_P8:
1091    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1092  case Mips::ATOMIC_LOAD_XOR_I16:
1093  case Mips::ATOMIC_LOAD_XOR_I16_P8:
1094    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1095  case Mips::ATOMIC_LOAD_XOR_I32:
1096  case Mips::ATOMIC_LOAD_XOR_I32_P8:
1097    return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
1098  case Mips::ATOMIC_LOAD_XOR_I64:
1099  case Mips::ATOMIC_LOAD_XOR_I64_P8:
1100    return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
1101
1102  case Mips::ATOMIC_LOAD_NAND_I8:
1103  case Mips::ATOMIC_LOAD_NAND_I8_P8:
1104    return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1105  case Mips::ATOMIC_LOAD_NAND_I16:
1106  case Mips::ATOMIC_LOAD_NAND_I16_P8:
1107    return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1108  case Mips::ATOMIC_LOAD_NAND_I32:
1109  case Mips::ATOMIC_LOAD_NAND_I32_P8:
1110    return EmitAtomicBinary(MI, BB, 4, 0, true);
1111  case Mips::ATOMIC_LOAD_NAND_I64:
1112  case Mips::ATOMIC_LOAD_NAND_I64_P8:
1113    return EmitAtomicBinary(MI, BB, 8, 0, true);
1114
1115  case Mips::ATOMIC_LOAD_SUB_I8:
1116  case Mips::ATOMIC_LOAD_SUB_I8_P8:
1117    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1118  case Mips::ATOMIC_LOAD_SUB_I16:
1119  case Mips::ATOMIC_LOAD_SUB_I16_P8:
1120    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1121  case Mips::ATOMIC_LOAD_SUB_I32:
1122  case Mips::ATOMIC_LOAD_SUB_I32_P8:
1123    return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
1124  case Mips::ATOMIC_LOAD_SUB_I64:
1125  case Mips::ATOMIC_LOAD_SUB_I64_P8:
1126    return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1127
1128  case Mips::ATOMIC_SWAP_I8:
1129  case Mips::ATOMIC_SWAP_I8_P8:
1130    return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1131  case Mips::ATOMIC_SWAP_I16:
1132  case Mips::ATOMIC_SWAP_I16_P8:
1133    return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1134  case Mips::ATOMIC_SWAP_I32:
1135  case Mips::ATOMIC_SWAP_I32_P8:
1136    return EmitAtomicBinary(MI, BB, 4, 0);
1137  case Mips::ATOMIC_SWAP_I64:
1138  case Mips::ATOMIC_SWAP_I64_P8:
1139    return EmitAtomicBinary(MI, BB, 8, 0);
1140
1141  case Mips::ATOMIC_CMP_SWAP_I8:
1142  case Mips::ATOMIC_CMP_SWAP_I8_P8:
1143    return EmitAtomicCmpSwapPartword(MI, BB, 1);
1144  case Mips::ATOMIC_CMP_SWAP_I16:
1145  case Mips::ATOMIC_CMP_SWAP_I16_P8:
1146    return EmitAtomicCmpSwapPartword(MI, BB, 2);
1147  case Mips::ATOMIC_CMP_SWAP_I32:
1148  case Mips::ATOMIC_CMP_SWAP_I32_P8:
1149    return EmitAtomicCmpSwap(MI, BB, 4);
1150  case Mips::ATOMIC_CMP_SWAP_I64:
1151  case Mips::ATOMIC_CMP_SWAP_I64_P8:
1152    return EmitAtomicCmpSwap(MI, BB, 8);
1153  case Mips::BPOSGE32_PSEUDO:
1154    return EmitBPOSGE32(MI, BB);
1155  }
1156}
1157
1158// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1159// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1160MachineBasicBlock *
1161MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1162                                     unsigned Size, unsigned BinOpcode,
1163                                     bool Nand) const {
1164  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1165
1166  MachineFunction *MF = BB->getParent();
1167  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1168  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1169  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1170  DebugLoc dl = MI->getDebugLoc();
1171  unsigned LL, SC, AND, NOR, ZERO, BEQ;
1172
1173  if (Size == 4) {
1174    LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1175    SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1176    AND = Mips::AND;
1177    NOR = Mips::NOR;
1178    ZERO = Mips::ZERO;
1179    BEQ = Mips::BEQ;
1180  }
1181  else {
1182    LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1183    SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1184    AND = Mips::AND64;
1185    NOR = Mips::NOR64;
1186    ZERO = Mips::ZERO_64;
1187    BEQ = Mips::BEQ64;
1188  }
1189
1190  unsigned OldVal = MI->getOperand(0).getReg();
1191  unsigned Ptr = MI->getOperand(1).getReg();
1192  unsigned Incr = MI->getOperand(2).getReg();
1193
1194  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1195  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1196  unsigned Success = RegInfo.createVirtualRegister(RC);
1197
1198  // insert new blocks after the current block
1199  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1200  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1201  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1202  MachineFunction::iterator It = BB;
1203  ++It;
1204  MF->insert(It, loopMBB);
1205  MF->insert(It, exitMBB);
1206
1207  // Transfer the remainder of BB and its successor edges to exitMBB.
1208  exitMBB->splice(exitMBB->begin(), BB,
1209                  llvm::next(MachineBasicBlock::iterator(MI)),
1210                  BB->end());
1211  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1212
1213  //  thisMBB:
1214  //    ...
1215  //    fallthrough --> loopMBB
1216  BB->addSuccessor(loopMBB);
1217  loopMBB->addSuccessor(loopMBB);
1218  loopMBB->addSuccessor(exitMBB);
1219
1220  //  loopMBB:
1221  //    ll oldval, 0(ptr)
1222  //    <binop> storeval, oldval, incr
1223  //    sc success, storeval, 0(ptr)
1224  //    beq success, $0, loopMBB
1225  BB = loopMBB;
1226  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1227  if (Nand) {
1228    //  and andres, oldval, incr
1229    //  nor storeval, $0, andres
1230    BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1231    BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1232  } else if (BinOpcode) {
1233    //  <binop> storeval, oldval, incr
1234    BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1235  } else {
1236    StoreVal = Incr;
1237  }
1238  BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1239  BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1240
1241  MI->eraseFromParent();   // The instruction is gone now.
1242
1243  return exitMBB;
1244}
1245
1246MachineBasicBlock *
1247MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
1248                                             MachineBasicBlock *BB,
1249                                             unsigned Size, unsigned BinOpcode,
1250                                             bool Nand) const {
1251  assert((Size == 1 || Size == 2) &&
1252      "Unsupported size for EmitAtomicBinaryPartial.");
1253
1254  MachineFunction *MF = BB->getParent();
1255  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1256  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1257  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1258  DebugLoc dl = MI->getDebugLoc();
1259  unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1260  unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1261
1262  unsigned Dest = MI->getOperand(0).getReg();
1263  unsigned Ptr = MI->getOperand(1).getReg();
1264  unsigned Incr = MI->getOperand(2).getReg();
1265
1266  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1267  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1268  unsigned Mask = RegInfo.createVirtualRegister(RC);
1269  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1270  unsigned NewVal = RegInfo.createVirtualRegister(RC);
1271  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1272  unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1273  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1274  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1275  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1276  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1277  unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1278  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1279  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1280  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1281  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1282  unsigned SllRes = RegInfo.createVirtualRegister(RC);
1283  unsigned Success = RegInfo.createVirtualRegister(RC);
1284
1285  // insert new blocks after the current block
1286  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1287  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1288  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1289  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1290  MachineFunction::iterator It = BB;
1291  ++It;
1292  MF->insert(It, loopMBB);
1293  MF->insert(It, sinkMBB);
1294  MF->insert(It, exitMBB);
1295
1296  // Transfer the remainder of BB and its successor edges to exitMBB.
1297  exitMBB->splice(exitMBB->begin(), BB,
1298                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1299  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1300
1301  BB->addSuccessor(loopMBB);
1302  loopMBB->addSuccessor(loopMBB);
1303  loopMBB->addSuccessor(sinkMBB);
1304  sinkMBB->addSuccessor(exitMBB);
1305
1306  //  thisMBB:
1307  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1308  //    and     alignedaddr,ptr,masklsb2
1309  //    andi    ptrlsb2,ptr,3
1310  //    sll     shiftamt,ptrlsb2,3
1311  //    ori     maskupper,$0,255               # 0xff
1312  //    sll     mask,maskupper,shiftamt
1313  //    nor     mask2,$0,mask
1314  //    sll     incr2,incr,shiftamt
1315
1316  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1317  BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1318    .addReg(Mips::ZERO).addImm(-4);
1319  BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1320    .addReg(Ptr).addReg(MaskLSB2);
1321  BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1322  BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1323  BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1324    .addReg(Mips::ZERO).addImm(MaskImm);
1325  BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1326    .addReg(ShiftAmt).addReg(MaskUpper);
1327  BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1328  BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1329
1330  // atomic.load.binop
1331  // loopMBB:
1332  //   ll      oldval,0(alignedaddr)
1333  //   binop   binopres,oldval,incr2
1334  //   and     newval,binopres,mask
1335  //   and     maskedoldval0,oldval,mask2
1336  //   or      storeval,maskedoldval0,newval
1337  //   sc      success,storeval,0(alignedaddr)
1338  //   beq     success,$0,loopMBB
1339
1340  // atomic.swap
1341  // loopMBB:
1342  //   ll      oldval,0(alignedaddr)
1343  //   and     newval,incr2,mask
1344  //   and     maskedoldval0,oldval,mask2
1345  //   or      storeval,maskedoldval0,newval
1346  //   sc      success,storeval,0(alignedaddr)
1347  //   beq     success,$0,loopMBB
1348
1349  BB = loopMBB;
1350  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1351  if (Nand) {
1352    //  and andres, oldval, incr2
1353    //  nor binopres, $0, andres
1354    //  and newval, binopres, mask
1355    BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1356    BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1357      .addReg(Mips::ZERO).addReg(AndRes);
1358    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1359  } else if (BinOpcode) {
1360    //  <binop> binopres, oldval, incr2
1361    //  and newval, binopres, mask
1362    BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1363    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1364  } else {// atomic.swap
1365    //  and newval, incr2, mask
1366    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1367  }
1368
1369  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1370    .addReg(OldVal).addReg(Mask2);
1371  BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1372    .addReg(MaskedOldVal0).addReg(NewVal);
1373  BuildMI(BB, dl, TII->get(SC), Success)
1374    .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1375  BuildMI(BB, dl, TII->get(Mips::BEQ))
1376    .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1377
1378  //  sinkMBB:
1379  //    and     maskedoldval1,oldval,mask
1380  //    srl     srlres,maskedoldval1,shiftamt
1381  //    sll     sllres,srlres,24
1382  //    sra     dest,sllres,24
1383  BB = sinkMBB;
1384  int64_t ShiftImm = (Size == 1) ? 24 : 16;
1385
1386  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1387    .addReg(OldVal).addReg(Mask);
1388  BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1389      .addReg(ShiftAmt).addReg(MaskedOldVal1);
1390  BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1391      .addReg(SrlRes).addImm(ShiftImm);
1392  BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1393      .addReg(SllRes).addImm(ShiftImm);
1394
1395  MI->eraseFromParent();   // The instruction is gone now.
1396
1397  return exitMBB;
1398}
1399
1400MachineBasicBlock *
1401MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1402                                      MachineBasicBlock *BB,
1403                                      unsigned Size) const {
1404  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1405
1406  MachineFunction *MF = BB->getParent();
1407  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1408  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1409  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1410  DebugLoc dl = MI->getDebugLoc();
1411  unsigned LL, SC, ZERO, BNE, BEQ;
1412
1413  if (Size == 4) {
1414    LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1415    SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1416    ZERO = Mips::ZERO;
1417    BNE = Mips::BNE;
1418    BEQ = Mips::BEQ;
1419  }
1420  else {
1421    LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1422    SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1423    ZERO = Mips::ZERO_64;
1424    BNE = Mips::BNE64;
1425    BEQ = Mips::BEQ64;
1426  }
1427
1428  unsigned Dest    = MI->getOperand(0).getReg();
1429  unsigned Ptr     = MI->getOperand(1).getReg();
1430  unsigned OldVal  = MI->getOperand(2).getReg();
1431  unsigned NewVal  = MI->getOperand(3).getReg();
1432
1433  unsigned Success = RegInfo.createVirtualRegister(RC);
1434
1435  // insert new blocks after the current block
1436  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1437  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1438  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1439  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1440  MachineFunction::iterator It = BB;
1441  ++It;
1442  MF->insert(It, loop1MBB);
1443  MF->insert(It, loop2MBB);
1444  MF->insert(It, exitMBB);
1445
1446  // Transfer the remainder of BB and its successor edges to exitMBB.
1447  exitMBB->splice(exitMBB->begin(), BB,
1448                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1449  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1450
1451  //  thisMBB:
1452  //    ...
1453  //    fallthrough --> loop1MBB
1454  BB->addSuccessor(loop1MBB);
1455  loop1MBB->addSuccessor(exitMBB);
1456  loop1MBB->addSuccessor(loop2MBB);
1457  loop2MBB->addSuccessor(loop1MBB);
1458  loop2MBB->addSuccessor(exitMBB);
1459
1460  // loop1MBB:
1461  //   ll dest, 0(ptr)
1462  //   bne dest, oldval, exitMBB
1463  BB = loop1MBB;
1464  BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1465  BuildMI(BB, dl, TII->get(BNE))
1466    .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1467
1468  // loop2MBB:
1469  //   sc success, newval, 0(ptr)
1470  //   beq success, $0, loop1MBB
1471  BB = loop2MBB;
1472  BuildMI(BB, dl, TII->get(SC), Success)
1473    .addReg(NewVal).addReg(Ptr).addImm(0);
1474  BuildMI(BB, dl, TII->get(BEQ))
1475    .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1476
1477  MI->eraseFromParent();   // The instruction is gone now.
1478
1479  return exitMBB;
1480}
1481
1482MachineBasicBlock *
1483MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1484                                              MachineBasicBlock *BB,
1485                                              unsigned Size) const {
1486  assert((Size == 1 || Size == 2) &&
1487      "Unsupported size for EmitAtomicCmpSwapPartial.");
1488
1489  MachineFunction *MF = BB->getParent();
1490  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1491  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1492  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1493  DebugLoc dl = MI->getDebugLoc();
1494  unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1495  unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1496
1497  unsigned Dest    = MI->getOperand(0).getReg();
1498  unsigned Ptr     = MI->getOperand(1).getReg();
1499  unsigned CmpVal  = MI->getOperand(2).getReg();
1500  unsigned NewVal  = MI->getOperand(3).getReg();
1501
1502  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1503  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1504  unsigned Mask = RegInfo.createVirtualRegister(RC);
1505  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1506  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1507  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1508  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1509  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1510  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1511  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1512  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1513  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1514  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1515  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1516  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1517  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1518  unsigned SllRes = RegInfo.createVirtualRegister(RC);
1519  unsigned Success = RegInfo.createVirtualRegister(RC);
1520
1521  // insert new blocks after the current block
1522  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1523  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1524  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1525  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1526  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1527  MachineFunction::iterator It = BB;
1528  ++It;
1529  MF->insert(It, loop1MBB);
1530  MF->insert(It, loop2MBB);
1531  MF->insert(It, sinkMBB);
1532  MF->insert(It, exitMBB);
1533
1534  // Transfer the remainder of BB and its successor edges to exitMBB.
1535  exitMBB->splice(exitMBB->begin(), BB,
1536                  llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1537  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1538
1539  BB->addSuccessor(loop1MBB);
1540  loop1MBB->addSuccessor(sinkMBB);
1541  loop1MBB->addSuccessor(loop2MBB);
1542  loop2MBB->addSuccessor(loop1MBB);
1543  loop2MBB->addSuccessor(sinkMBB);
1544  sinkMBB->addSuccessor(exitMBB);
1545
1546  // FIXME: computation of newval2 can be moved to loop2MBB.
1547  //  thisMBB:
1548  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1549  //    and     alignedaddr,ptr,masklsb2
1550  //    andi    ptrlsb2,ptr,3
1551  //    sll     shiftamt,ptrlsb2,3
1552  //    ori     maskupper,$0,255               # 0xff
1553  //    sll     mask,maskupper,shiftamt
1554  //    nor     mask2,$0,mask
1555  //    andi    maskedcmpval,cmpval,255
1556  //    sll     shiftedcmpval,maskedcmpval,shiftamt
1557  //    andi    maskednewval,newval,255
1558  //    sll     shiftednewval,maskednewval,shiftamt
1559  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1560  BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1561    .addReg(Mips::ZERO).addImm(-4);
1562  BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1563    .addReg(Ptr).addReg(MaskLSB2);
1564  BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1565  BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1566  BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1567    .addReg(Mips::ZERO).addImm(MaskImm);
1568  BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1569    .addReg(ShiftAmt).addReg(MaskUpper);
1570  BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1571  BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1572    .addReg(CmpVal).addImm(MaskImm);
1573  BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1574    .addReg(ShiftAmt).addReg(MaskedCmpVal);
1575  BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1576    .addReg(NewVal).addImm(MaskImm);
1577  BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1578    .addReg(ShiftAmt).addReg(MaskedNewVal);
1579
1580  //  loop1MBB:
1581  //    ll      oldval,0(alginedaddr)
1582  //    and     maskedoldval0,oldval,mask
1583  //    bne     maskedoldval0,shiftedcmpval,sinkMBB
1584  BB = loop1MBB;
1585  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1586  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1587    .addReg(OldVal).addReg(Mask);
1588  BuildMI(BB, dl, TII->get(Mips::BNE))
1589    .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1590
1591  //  loop2MBB:
1592  //    and     maskedoldval1,oldval,mask2
1593  //    or      storeval,maskedoldval1,shiftednewval
1594  //    sc      success,storeval,0(alignedaddr)
1595  //    beq     success,$0,loop1MBB
1596  BB = loop2MBB;
1597  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1598    .addReg(OldVal).addReg(Mask2);
1599  BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1600    .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1601  BuildMI(BB, dl, TII->get(SC), Success)
1602      .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1603  BuildMI(BB, dl, TII->get(Mips::BEQ))
1604      .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1605
1606  //  sinkMBB:
1607  //    srl     srlres,maskedoldval0,shiftamt
1608  //    sll     sllres,srlres,24
1609  //    sra     dest,sllres,24
1610  BB = sinkMBB;
1611  int64_t ShiftImm = (Size == 1) ? 24 : 16;
1612
1613  BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1614      .addReg(ShiftAmt).addReg(MaskedOldVal0);
1615  BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1616      .addReg(SrlRes).addImm(ShiftImm);
1617  BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1618      .addReg(SllRes).addImm(ShiftImm);
1619
1620  MI->eraseFromParent();   // The instruction is gone now.
1621
1622  return exitMBB;
1623}
1624
1625//===----------------------------------------------------------------------===//
1626//  Misc Lower Operation implementation
1627//===----------------------------------------------------------------------===//
1628SDValue MipsTargetLowering::
1629LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1630{
1631  // The first operand is the chain, the second is the condition, the third is
1632  // the block to branch to if the condition is true.
1633  SDValue Chain = Op.getOperand(0);
1634  SDValue Dest = Op.getOperand(2);
1635  DebugLoc dl = Op.getDebugLoc();
1636
1637  SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1638
1639  // Return if flag is not set by a floating point comparison.
1640  if (CondRes.getOpcode() != MipsISD::FPCmp)
1641    return Op;
1642
1643  SDValue CCNode  = CondRes.getOperand(2);
1644  Mips::CondCode CC =
1645    (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1646  SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
1647
1648  return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
1649                     Dest, CondRes);
1650}
1651
1652SDValue MipsTargetLowering::
1653LowerSELECT(SDValue Op, SelectionDAG &DAG) const
1654{
1655  SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
1656
1657  // Return if flag is not set by a floating point comparison.
1658  if (Cond.getOpcode() != MipsISD::FPCmp)
1659    return Op;
1660
1661  return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1662                      Op.getDebugLoc());
1663}
1664
1665SDValue MipsTargetLowering::
1666LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1667{
1668  DebugLoc DL = Op.getDebugLoc();
1669  EVT Ty = Op.getOperand(0).getValueType();
1670  SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
1671                             Op.getOperand(0), Op.getOperand(1),
1672                             Op.getOperand(4));
1673
1674  return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1675                     Op.getOperand(3));
1676}
1677
1678SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1679  SDValue Cond = CreateFPCmp(DAG, Op);
1680
1681  assert(Cond.getOpcode() == MipsISD::FPCmp &&
1682         "Floating point operand expected.");
1683
1684  SDValue True  = DAG.getConstant(1, MVT::i32);
1685  SDValue False = DAG.getConstant(0, MVT::i32);
1686
1687  return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1688}
1689
1690SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1691                                               SelectionDAG &DAG) const {
1692  // FIXME there isn't actually debug info here
1693  DebugLoc dl = Op.getDebugLoc();
1694  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1695
1696  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1697    SDVTList VTs = DAG.getVTList(MVT::i32);
1698
1699    const MipsTargetObjectFile &TLOF =
1700      (const MipsTargetObjectFile&)getObjFileLowering();
1701
1702    // %gp_rel relocation
1703    if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1704      SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1705                                              MipsII::MO_GPREL);
1706      SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1707      SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1708      return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
1709    }
1710    // %hi/%lo relocation
1711    SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1712                                              MipsII::MO_ABS_HI);
1713    SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1714                                              MipsII::MO_ABS_LO);
1715    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1716    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1717    return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1718  }
1719
1720  EVT ValTy = Op.getValueType();
1721  bool HasGotOfst = (GV->hasInternalLinkage() ||
1722                     (GV->hasLocalLinkage() && !isa<Function>(GV)));
1723  unsigned GotFlag = HasMips64 ?
1724                     (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
1725                     (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
1726  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
1727  GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
1728  SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1729                                MachinePointerInfo(), false, false, false, 0);
1730  // On functions and global targets not internal linked only
1731  // a load from got/GP is necessary for PIC to work.
1732  if (!HasGotOfst)
1733    return ResNode;
1734  SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
1735                                            HasMips64 ? MipsII::MO_GOT_OFST :
1736                                                        MipsII::MO_ABS_LO);
1737  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1738  return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
1739}
1740
1741SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1742                                              SelectionDAG &DAG) const {
1743  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1744  // FIXME there isn't actually debug info here
1745  DebugLoc dl = Op.getDebugLoc();
1746
1747  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1748    // %hi/%lo relocation
1749    SDValue BAHi = DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_HI);
1750    SDValue BALo = DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_LO);
1751    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1752    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1753    return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1754  }
1755
1756  EVT ValTy = Op.getValueType();
1757  unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1758  unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1759  SDValue BAGOTOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, GOTFlag);
1760  BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1761                            GetGlobalReg(DAG, ValTy), BAGOTOffset);
1762  SDValue BALOOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, OFSTFlag);
1763  SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
1764                             MachinePointerInfo(), false, false, false, 0);
1765  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1766  return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
1767}
1768
1769SDValue MipsTargetLowering::
1770LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1771{
1772  // If the relocation model is PIC, use the General Dynamic TLS Model or
1773  // Local Dynamic TLS model, otherwise use the Initial Exec or
1774  // Local Exec TLS Model.
1775
1776  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1777  DebugLoc dl = GA->getDebugLoc();
1778  const GlobalValue *GV = GA->getGlobal();
1779  EVT PtrVT = getPointerTy();
1780
1781  TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1782
1783  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1784    // General Dynamic and Local Dynamic TLS Model.
1785    unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1786                                                      : MipsII::MO_TLSGD;
1787
1788    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
1789    SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1790                                   GetGlobalReg(DAG, PtrVT), TGA);
1791    unsigned PtrSize = PtrVT.getSizeInBits();
1792    IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1793
1794    SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1795
1796    ArgListTy Args;
1797    ArgListEntry Entry;
1798    Entry.Node = Argument;
1799    Entry.Ty = PtrTy;
1800    Args.push_back(Entry);
1801
1802    TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1803                  false, false, false, false, 0, CallingConv::C,
1804                  /*isTailCall=*/false, /*doesNotRet=*/false,
1805                  /*isReturnValueUsed=*/true,
1806                  TlsGetAddr, Args, DAG, dl);
1807    std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1808
1809    SDValue Ret = CallResult.first;
1810
1811    if (model != TLSModel::LocalDynamic)
1812      return Ret;
1813
1814    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1815                                               MipsII::MO_DTPREL_HI);
1816    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1817    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1818                                               MipsII::MO_DTPREL_LO);
1819    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1820    SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1821    return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
1822  }
1823
1824  SDValue Offset;
1825  if (model == TLSModel::InitialExec) {
1826    // Initial Exec TLS Model
1827    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1828                                             MipsII::MO_GOTTPREL);
1829    TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1830                      TGA);
1831    Offset = DAG.getLoad(PtrVT, dl,
1832                         DAG.getEntryNode(), TGA, MachinePointerInfo(),
1833                         false, false, false, 0);
1834  } else {
1835    // Local Exec TLS Model
1836    assert(model == TLSModel::LocalExec);
1837    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1838                                               MipsII::MO_TPREL_HI);
1839    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1840                                               MipsII::MO_TPREL_LO);
1841    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1842    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1843    Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1844  }
1845
1846  SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1847  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1848}
1849
1850SDValue MipsTargetLowering::
1851LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1852{
1853  SDValue HiPart, JTI, JTILo;
1854  // FIXME there isn't actually debug info here
1855  DebugLoc dl = Op.getDebugLoc();
1856  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1857  EVT PtrVT = Op.getValueType();
1858  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1859
1860  if (!IsPIC && !IsN64) {
1861    JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1862    HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1863    JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
1864  } else {// Emit Load from Global Pointer
1865    unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1866    unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1867    JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
1868    JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1869                      JTI);
1870    HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1871                         MachinePointerInfo(), false, false, false, 0);
1872    JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
1873  }
1874
1875  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1876  return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
1877}
1878
1879SDValue MipsTargetLowering::
1880LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1881{
1882  SDValue ResNode;
1883  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1884  const Constant *C = N->getConstVal();
1885  // FIXME there isn't actually debug info here
1886  DebugLoc dl = Op.getDebugLoc();
1887
1888  // gp_rel relocation
1889  // FIXME: we should reference the constant pool using small data sections,
1890  // but the asm printer currently doesn't support this feature without
1891  // hacking it. This feature should come soon so we can uncomment the
1892  // stuff below.
1893  //if (IsInSmallSection(C->getType())) {
1894  //  SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1895  //  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1896  //  ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1897
1898  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1899    SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1900                                             N->getOffset(), MipsII::MO_ABS_HI);
1901    SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1902                                             N->getOffset(), MipsII::MO_ABS_LO);
1903    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1904    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1905    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1906  } else {
1907    EVT ValTy = Op.getValueType();
1908    unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1909    unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1910    SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1911                                           N->getOffset(), GOTFlag);
1912    CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
1913    SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1914                               MachinePointerInfo::getConstantPool(), false,
1915                               false, false, 0);
1916    SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1917                                             N->getOffset(), OFSTFlag);
1918    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1919    ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
1920  }
1921
1922  return ResNode;
1923}
1924
1925SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1926  MachineFunction &MF = DAG.getMachineFunction();
1927  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1928
1929  DebugLoc dl = Op.getDebugLoc();
1930  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1931                                 getPointerTy());
1932
1933  // vastart just stores the address of the VarArgsFrameIndex slot into the
1934  // memory location argument.
1935  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1936  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1937                      MachinePointerInfo(SV), false, false, 0);
1938}
1939
1940static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1941  EVT TyX = Op.getOperand(0).getValueType();
1942  EVT TyY = Op.getOperand(1).getValueType();
1943  SDValue Const1 = DAG.getConstant(1, MVT::i32);
1944  SDValue Const31 = DAG.getConstant(31, MVT::i32);
1945  DebugLoc DL = Op.getDebugLoc();
1946  SDValue Res;
1947
1948  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1949  // to i32.
1950  SDValue X = (TyX == MVT::f32) ?
1951    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1952    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1953                Const1);
1954  SDValue Y = (TyY == MVT::f32) ?
1955    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1956    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1957                Const1);
1958
1959  if (HasR2) {
1960    // ext  E, Y, 31, 1  ; extract bit31 of Y
1961    // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
1962    SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1963    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1964  } else {
1965    // sll SllX, X, 1
1966    // srl SrlX, SllX, 1
1967    // srl SrlY, Y, 31
1968    // sll SllY, SrlX, 31
1969    // or  Or, SrlX, SllY
1970    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1971    SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1972    SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1973    SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1974    Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1975  }
1976
1977  if (TyX == MVT::f32)
1978    return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1979
1980  SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1981                             Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1982  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1983}
1984
1985static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1986  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1987  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1988  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1989  SDValue Const1 = DAG.getConstant(1, MVT::i32);
1990  DebugLoc DL = Op.getDebugLoc();
1991
1992  // Bitcast to integer nodes.
1993  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1994  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1995
1996  if (HasR2) {
1997    // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
1998    // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
1999    SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2000                            DAG.getConstant(WidthY - 1, MVT::i32), Const1);
2001
2002    if (WidthX > WidthY)
2003      E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2004    else if (WidthY > WidthX)
2005      E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2006
2007    SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2008                            DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
2009    return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2010  }
2011
2012  // (d)sll SllX, X, 1
2013  // (d)srl SrlX, SllX, 1
2014  // (d)srl SrlY, Y, width(Y)-1
2015  // (d)sll SllY, SrlX, width(Y)-1
2016  // or     Or, SrlX, SllY
2017  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2018  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2019  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2020                             DAG.getConstant(WidthY - 1, MVT::i32));
2021
2022  if (WidthX > WidthY)
2023    SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2024  else if (WidthY > WidthX)
2025    SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2026
2027  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2028                             DAG.getConstant(WidthX - 1, MVT::i32));
2029  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2030  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2031}
2032
2033SDValue
2034MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2035  if (Subtarget->hasMips64())
2036    return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
2037
2038  return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
2039}
2040
2041static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2042  SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2043  DebugLoc DL = Op.getDebugLoc();
2044
2045  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2046  // to i32.
2047  SDValue X = (Op.getValueType() == MVT::f32) ?
2048    DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2049    DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2050                Const1);
2051
2052  // Clear MSB.
2053  if (HasR2)
2054    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2055                      DAG.getRegister(Mips::ZERO, MVT::i32),
2056                      DAG.getConstant(31, MVT::i32), Const1, X);
2057  else {
2058    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2059    Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2060  }
2061
2062  if (Op.getValueType() == MVT::f32)
2063    return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2064
2065  SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2066                             Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2067  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2068}
2069
2070static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2071  SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2072  DebugLoc DL = Op.getDebugLoc();
2073
2074  // Bitcast to integer node.
2075  SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2076
2077  // Clear MSB.
2078  if (HasR2)
2079    Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2080                      DAG.getRegister(Mips::ZERO_64, MVT::i64),
2081                      DAG.getConstant(63, MVT::i32), Const1, X);
2082  else {
2083    SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2084    Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2085  }
2086
2087  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2088}
2089
2090SDValue
2091MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2092  if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2093    return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2094
2095  return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2096}
2097
2098SDValue MipsTargetLowering::
2099LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2100  // check the depth
2101  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2102         "Frame address can only be determined for current frame.");
2103
2104  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2105  MFI->setFrameAddressIsTaken(true);
2106  EVT VT = Op.getValueType();
2107  DebugLoc dl = Op.getDebugLoc();
2108  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2109                                         IsN64 ? Mips::FP_64 : Mips::FP, VT);
2110  return FrameAddr;
2111}
2112
2113SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2114                                            SelectionDAG &DAG) const {
2115  // check the depth
2116  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2117         "Return address can be determined only for current frame.");
2118
2119  MachineFunction &MF = DAG.getMachineFunction();
2120  MachineFrameInfo *MFI = MF.getFrameInfo();
2121  EVT VT = Op.getValueType();
2122  unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2123  MFI->setReturnAddressIsTaken(true);
2124
2125  // Return RA, which contains the return address. Mark it an implicit live-in.
2126  unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2127  return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2128}
2129
2130// TODO: set SType according to the desired memory barrier behavior.
2131SDValue
2132MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
2133  unsigned SType = 0;
2134  DebugLoc dl = Op.getDebugLoc();
2135  return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2136                     DAG.getConstant(SType, MVT::i32));
2137}
2138
2139SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
2140                                              SelectionDAG &DAG) const {
2141  // FIXME: Need pseudo-fence for 'singlethread' fences
2142  // FIXME: Set SType for weaker fences where supported/appropriate.
2143  unsigned SType = 0;
2144  DebugLoc dl = Op.getDebugLoc();
2145  return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2146                     DAG.getConstant(SType, MVT::i32));
2147}
2148
2149SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
2150                                                SelectionDAG &DAG) const {
2151  DebugLoc DL = Op.getDebugLoc();
2152  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2153  SDValue Shamt = Op.getOperand(2);
2154
2155  // if shamt < 32:
2156  //  lo = (shl lo, shamt)
2157  //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2158  // else:
2159  //  lo = 0
2160  //  hi = (shl lo, shamt[4:0])
2161  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2162                            DAG.getConstant(-1, MVT::i32));
2163  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2164                                      DAG.getConstant(1, MVT::i32));
2165  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2166                                     Not);
2167  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2168  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2169  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2170  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2171                             DAG.getConstant(0x20, MVT::i32));
2172  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2173                   DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2174  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2175
2176  SDValue Ops[2] = {Lo, Hi};
2177  return DAG.getMergeValues(Ops, 2, DL);
2178}
2179
2180SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2181                                                 bool IsSRA) const {
2182  DebugLoc DL = Op.getDebugLoc();
2183  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2184  SDValue Shamt = Op.getOperand(2);
2185
2186  // if shamt < 32:
2187  //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2188  //  if isSRA:
2189  //    hi = (sra hi, shamt)
2190  //  else:
2191  //    hi = (srl hi, shamt)
2192  // else:
2193  //  if isSRA:
2194  //   lo = (sra hi, shamt[4:0])
2195  //   hi = (sra hi, 31)
2196  //  else:
2197  //   lo = (srl hi, shamt[4:0])
2198  //   hi = 0
2199  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2200                            DAG.getConstant(-1, MVT::i32));
2201  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2202                                     DAG.getConstant(1, MVT::i32));
2203  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2204  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2205  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2206  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2207                                     Hi, Shamt);
2208  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2209                             DAG.getConstant(0x20, MVT::i32));
2210  SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2211                                DAG.getConstant(31, MVT::i32));
2212  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2213  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2214                   IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2215                   ShiftRightHi);
2216
2217  SDValue Ops[2] = {Lo, Hi};
2218  return DAG.getMergeValues(Ops, 2, DL);
2219}
2220
2221static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2222                            SDValue Chain, SDValue Src, unsigned Offset) {
2223  SDValue Ptr = LD->getBasePtr();
2224  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2225  EVT BasePtrVT = Ptr.getValueType();
2226  DebugLoc DL = LD->getDebugLoc();
2227  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2228
2229  if (Offset)
2230    Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2231                      DAG.getConstant(Offset, BasePtrVT));
2232
2233  SDValue Ops[] = { Chain, Ptr, Src };
2234  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2235                                 LD->getMemOperand());
2236}
2237
2238// Expand an unaligned 32 or 64-bit integer load node.
2239SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2240  LoadSDNode *LD = cast<LoadSDNode>(Op);
2241  EVT MemVT = LD->getMemoryVT();
2242
2243  // Return if load is aligned or if MemVT is neither i32 nor i64.
2244  if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2245      ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2246    return SDValue();
2247
2248  bool IsLittle = Subtarget->isLittle();
2249  EVT VT = Op.getValueType();
2250  ISD::LoadExtType ExtType = LD->getExtensionType();
2251  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2252
2253  assert((VT == MVT::i32) || (VT == MVT::i64));
2254
2255  // Expand
2256  //  (set dst, (i64 (load baseptr)))
2257  // to
2258  //  (set tmp, (ldl (add baseptr, 7), undef))
2259  //  (set dst, (ldr baseptr, tmp))
2260  if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2261    SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2262                               IsLittle ? 7 : 0);
2263    return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2264                        IsLittle ? 0 : 7);
2265  }
2266
2267  SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2268                             IsLittle ? 3 : 0);
2269  SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2270                             IsLittle ? 0 : 3);
2271
2272  // Expand
2273  //  (set dst, (i32 (load baseptr))) or
2274  //  (set dst, (i64 (sextload baseptr))) or
2275  //  (set dst, (i64 (extload baseptr)))
2276  // to
2277  //  (set tmp, (lwl (add baseptr, 3), undef))
2278  //  (set dst, (lwr baseptr, tmp))
2279  if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2280      (ExtType == ISD::EXTLOAD))
2281    return LWR;
2282
2283  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2284
2285  // Expand
2286  //  (set dst, (i64 (zextload baseptr)))
2287  // to
2288  //  (set tmp0, (lwl (add baseptr, 3), undef))
2289  //  (set tmp1, (lwr baseptr, tmp0))
2290  //  (set tmp2, (shl tmp1, 32))
2291  //  (set dst, (srl tmp2, 32))
2292  DebugLoc DL = LD->getDebugLoc();
2293  SDValue Const32 = DAG.getConstant(32, MVT::i32);
2294  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2295  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2296  SDValue Ops[] = { SRL, LWR.getValue(1) };
2297  return DAG.getMergeValues(Ops, 2, DL);
2298}
2299
2300static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2301                             SDValue Chain, unsigned Offset) {
2302  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2303  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2304  DebugLoc DL = SD->getDebugLoc();
2305  SDVTList VTList = DAG.getVTList(MVT::Other);
2306
2307  if (Offset)
2308    Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2309                      DAG.getConstant(Offset, BasePtrVT));
2310
2311  SDValue Ops[] = { Chain, Value, Ptr };
2312  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2313                                 SD->getMemOperand());
2314}
2315
2316// Expand an unaligned 32 or 64-bit integer store node.
2317SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2318  StoreSDNode *SD = cast<StoreSDNode>(Op);
2319  EVT MemVT = SD->getMemoryVT();
2320
2321  // Return if store is aligned or if MemVT is neither i32 nor i64.
2322  if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2323      ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2324    return SDValue();
2325
2326  bool IsLittle = Subtarget->isLittle();
2327  SDValue Value = SD->getValue(), Chain = SD->getChain();
2328  EVT VT = Value.getValueType();
2329
2330  // Expand
2331  //  (store val, baseptr) or
2332  //  (truncstore val, baseptr)
2333  // to
2334  //  (swl val, (add baseptr, 3))
2335  //  (swr val, baseptr)
2336  if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2337    SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2338                                IsLittle ? 3 : 0);
2339    return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2340  }
2341
2342  assert(VT == MVT::i64);
2343
2344  // Expand
2345  //  (store val, baseptr)
2346  // to
2347  //  (sdl val, (add baseptr, 7))
2348  //  (sdr val, baseptr)
2349  SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2350  return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2351}
2352
2353// This function expands mips intrinsic nodes which have 64-bit input operands
2354// or output values.
2355//
2356// out64 = intrinsic-node in64
2357// =>
2358// lo = copy (extract-element (in64, 0))
2359// hi = copy (extract-element (in64, 1))
2360// mips-specific-node
2361// v0 = copy lo
2362// v1 = copy hi
2363// out64 = merge-values (v0, v1)
2364//
2365static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
2366                            unsigned Opc, bool HasI64In, bool HasI64Out) {
2367  DebugLoc DL = Op.getDebugLoc();
2368  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
2369  SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
2370  SmallVector<SDValue, 3> Ops;
2371
2372  if (HasI64In) {
2373    SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2374                               Op->getOperand(1 + HasChainIn),
2375                               DAG.getConstant(0, MVT::i32));
2376    SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2377                               Op->getOperand(1 + HasChainIn),
2378                               DAG.getConstant(1, MVT::i32));
2379
2380    Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
2381    Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
2382
2383    Ops.push_back(Chain);
2384    Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
2385    Ops.push_back(Chain.getValue(1));
2386  } else {
2387    Ops.push_back(Chain);
2388    Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
2389  }
2390
2391  if (!HasI64Out)
2392    return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
2393                       Ops.begin(), Ops.size());
2394
2395  SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2396                             Ops.begin(), Ops.size());
2397  SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
2398                                     Intr.getValue(1));
2399  SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
2400                                     OutLo.getValue(2));
2401  SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2402
2403  if (!HasChainIn)
2404    return Out;
2405
2406  SDValue Vals[] = { Out, OutHi.getValue(1) };
2407  return DAG.getMergeValues(Vals, 2, DL);
2408}
2409
2410SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2411                                                    SelectionDAG &DAG) const {
2412  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
2413  default:
2414    return SDValue();
2415  case Intrinsic::mips_shilo:
2416    return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true);
2417  case Intrinsic::mips_dpau_h_qbl:
2418    return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true);
2419  case Intrinsic::mips_dpau_h_qbr:
2420    return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true);
2421  case Intrinsic::mips_dpsu_h_qbl:
2422    return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true);
2423  case Intrinsic::mips_dpsu_h_qbr:
2424    return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true);
2425  case Intrinsic::mips_dpa_w_ph:
2426    return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true);
2427  case Intrinsic::mips_dps_w_ph:
2428    return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true);
2429  case Intrinsic::mips_dpax_w_ph:
2430    return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true);
2431  case Intrinsic::mips_dpsx_w_ph:
2432    return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true);
2433  case Intrinsic::mips_mulsa_w_ph:
2434    return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true);
2435  case Intrinsic::mips_mult:
2436    return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true);
2437  case Intrinsic::mips_multu:
2438    return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true);
2439  case Intrinsic::mips_madd:
2440    return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true);
2441  case Intrinsic::mips_maddu:
2442    return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true);
2443  case Intrinsic::mips_msub:
2444    return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true);
2445  case Intrinsic::mips_msubu:
2446    return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true);
2447  }
2448}
2449
2450SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2451                                                   SelectionDAG &DAG) const {
2452  switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
2453  default:
2454    return SDValue();
2455  case Intrinsic::mips_extp:
2456    return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
2457  case Intrinsic::mips_extpdp:
2458    return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
2459  case Intrinsic::mips_extr_w:
2460    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
2461  case Intrinsic::mips_extr_r_w:
2462    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
2463  case Intrinsic::mips_extr_rs_w:
2464    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
2465  case Intrinsic::mips_extr_s_h:
2466    return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
2467  case Intrinsic::mips_mthlip:
2468    return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true);
2469  case Intrinsic::mips_mulsaq_s_w_ph:
2470    return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true);
2471  case Intrinsic::mips_maq_s_w_phl:
2472    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true);
2473  case Intrinsic::mips_maq_s_w_phr:
2474    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true);
2475  case Intrinsic::mips_maq_sa_w_phl:
2476    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true);
2477  case Intrinsic::mips_maq_sa_w_phr:
2478    return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true);
2479  case Intrinsic::mips_dpaq_s_w_ph:
2480    return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true);
2481  case Intrinsic::mips_dpsq_s_w_ph:
2482    return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true);
2483  case Intrinsic::mips_dpaq_sa_l_w:
2484    return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true);
2485  case Intrinsic::mips_dpsq_sa_l_w:
2486    return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true);
2487  case Intrinsic::mips_dpaqx_s_w_ph:
2488    return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true);
2489  case Intrinsic::mips_dpaqx_sa_w_ph:
2490    return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true);
2491  case Intrinsic::mips_dpsqx_s_w_ph:
2492    return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true);
2493  case Intrinsic::mips_dpsqx_sa_w_ph:
2494    return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true);
2495  }
2496}
2497
2498//===----------------------------------------------------------------------===//
2499//                      Calling Convention Implementation
2500//===----------------------------------------------------------------------===//
2501
2502//===----------------------------------------------------------------------===//
2503// TODO: Implement a generic logic using tblgen that can support this.
2504// Mips O32 ABI rules:
2505// ---
2506// i32 - Passed in A0, A1, A2, A3 and stack
2507// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2508//       an argument. Otherwise, passed in A1, A2, A3 and stack.
2509// f64 - Only passed in two aliased f32 registers if no int reg has been used
2510//       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2511//       not used, it must be shadowed. If only A3 is avaiable, shadow it and
2512//       go to stack.
2513//
2514//  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2515//===----------------------------------------------------------------------===//
2516
2517static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2518                       MVT LocVT, CCValAssign::LocInfo LocInfo,
2519                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
2520
2521  static const unsigned IntRegsSize=4, FloatRegsSize=2;
2522
2523  static const uint16_t IntRegs[] = {
2524      Mips::A0, Mips::A1, Mips::A2, Mips::A3
2525  };
2526  static const uint16_t F32Regs[] = {
2527      Mips::F12, Mips::F14
2528  };
2529  static const uint16_t F64Regs[] = {
2530      Mips::D6, Mips::D7
2531  };
2532
2533  // ByVal Args
2534  if (ArgFlags.isByVal()) {
2535    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
2536                      1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
2537    unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
2538    for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
2539         r < std::min(IntRegsSize, NextReg); ++r)
2540      State.AllocateReg(IntRegs[r]);
2541    return false;
2542  }
2543
2544  // Promote i8 and i16
2545  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2546    LocVT = MVT::i32;
2547    if (ArgFlags.isSExt())
2548      LocInfo = CCValAssign::SExt;
2549    else if (ArgFlags.isZExt())
2550      LocInfo = CCValAssign::ZExt;
2551    else
2552      LocInfo = CCValAssign::AExt;
2553  }
2554
2555  unsigned Reg;
2556
2557  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2558  // is true: function is vararg, argument is 3rd or higher, there is previous
2559  // argument which is not f32 or f64.
2560  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2561      || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2562  unsigned OrigAlign = ArgFlags.getOrigAlign();
2563  bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2564
2565  if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2566    Reg = State.AllocateReg(IntRegs, IntRegsSize);
2567    // If this is the first part of an i64 arg,
2568    // the allocated register must be either A0 or A2.
2569    if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2570      Reg = State.AllocateReg(IntRegs, IntRegsSize);
2571    LocVT = MVT::i32;
2572  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2573    // Allocate int register and shadow next int register. If first
2574    // available register is Mips::A1 or Mips::A3, shadow it too.
2575    Reg = State.AllocateReg(IntRegs, IntRegsSize);
2576    if (Reg == Mips::A1 || Reg == Mips::A3)
2577      Reg = State.AllocateReg(IntRegs, IntRegsSize);
2578    State.AllocateReg(IntRegs, IntRegsSize);
2579    LocVT = MVT::i32;
2580  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2581    // we are guaranteed to find an available float register
2582    if (ValVT == MVT::f32) {
2583      Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2584      // Shadow int register
2585      State.AllocateReg(IntRegs, IntRegsSize);
2586    } else {
2587      Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2588      // Shadow int registers
2589      unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2590      if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2591        State.AllocateReg(IntRegs, IntRegsSize);
2592      State.AllocateReg(IntRegs, IntRegsSize);
2593    }
2594  } else
2595    llvm_unreachable("Cannot handle this ValVT.");
2596
2597  unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
2598  unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
2599
2600  if (!Reg)
2601    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2602  else
2603    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2604
2605  return false; // CC must always match
2606}
2607
2608static const uint16_t Mips64IntRegs[8] =
2609  {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
2610   Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
2611static const uint16_t Mips64DPRegs[8] =
2612  {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
2613   Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
2614
2615static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT,
2616                           CCValAssign::LocInfo LocInfo,
2617                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2618  unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8);
2619  unsigned Size  = (ArgFlags.getByValSize() + 7) / 8 * 8;
2620  unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8);
2621
2622  assert(Align <= 16 && "Cannot handle alignments larger than 16.");
2623
2624  // If byval is 16-byte aligned, the first arg register must be even.
2625  if ((Align == 16) && (FirstIdx % 2)) {
2626    State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]);
2627    ++FirstIdx;
2628  }
2629
2630  // Mark the registers allocated.
2631  for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I)
2632    State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]);
2633
2634  // Allocate space on caller's stack.
2635  unsigned Offset = State.AllocateStack(Size, Align);
2636
2637  if (FirstIdx < 8)
2638    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx],
2639                                     LocVT, LocInfo));
2640  else
2641    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2642
2643  return true;
2644}
2645
2646#include "MipsGenCallingConv.inc"
2647
2648static void
2649AnalyzeMips64CallOperands(CCState &CCInfo,
2650                          const SmallVectorImpl<ISD::OutputArg> &Outs) {
2651  unsigned NumOps = Outs.size();
2652  for (unsigned i = 0; i != NumOps; ++i) {
2653    MVT ArgVT = Outs[i].VT;
2654    ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2655    bool R;
2656
2657    if (Outs[i].IsFixed)
2658      R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2659    else
2660      R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2661
2662    if (R) {
2663#ifndef NDEBUG
2664      dbgs() << "Call operand #" << i << " has unhandled type "
2665             << EVT(ArgVT).getEVTString();
2666#endif
2667      llvm_unreachable(0);
2668    }
2669  }
2670}
2671
2672//===----------------------------------------------------------------------===//
2673//                  Call Calling Convention Implementation
2674//===----------------------------------------------------------------------===//
2675
2676static const unsigned O32IntRegsSize = 4;
2677
2678static const uint16_t O32IntRegs[] = {
2679  Mips::A0, Mips::A1, Mips::A2, Mips::A3
2680};
2681
2682// Return next O32 integer argument register.
2683static unsigned getNextIntArgReg(unsigned Reg) {
2684  assert((Reg == Mips::A0) || (Reg == Mips::A2));
2685  return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2686}
2687
2688// Write ByVal Arg to arg registers and stack.
2689static void
2690WriteByValArg(SDValue Chain, DebugLoc dl,
2691              SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
2692              SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
2693              MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
2694              const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
2695              MVT PtrType, bool isLittle) {
2696  unsigned LocMemOffset = VA.getLocMemOffset();
2697  unsigned Offset = 0;
2698  uint32_t RemainingSize = Flags.getByValSize();
2699  unsigned ByValAlign = Flags.getByValAlign();
2700
2701  // Copy the first 4 words of byval arg to registers A0 - A3.
2702  // FIXME: Use a stricter alignment if it enables better optimization in passes
2703  //        run later.
2704  for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
2705       Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
2706    SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2707                                  DAG.getConstant(Offset, MVT::i32));
2708    SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
2709                                  MachinePointerInfo(), false, false, false,
2710                                  std::min(ByValAlign, (unsigned )4));
2711    MemOpChains.push_back(LoadVal.getValue(1));
2712    unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2713    RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2714  }
2715
2716  if (RemainingSize == 0)
2717    return;
2718
2719  // If there still is a register available for argument passing, write the
2720  // remaining part of the structure to it using subword loads and shifts.
2721  if (LocMemOffset < 4 * 4) {
2722    assert(RemainingSize <= 3 && RemainingSize >= 1 &&
2723           "There must be one to three bytes remaining.");
2724    unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
2725    SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2726                                  DAG.getConstant(Offset, MVT::i32));
2727    unsigned Alignment = std::min(ByValAlign, (unsigned )4);
2728    SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2729                                     LoadPtr, MachinePointerInfo(),
2730                                     MVT::getIntegerVT(LoadSize * 8), false,
2731                                     false, Alignment);
2732    MemOpChains.push_back(LoadVal.getValue(1));
2733
2734    // If target is big endian, shift it to the most significant half-word or
2735    // byte.
2736    if (!isLittle)
2737      LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
2738                            DAG.getConstant(32 - LoadSize * 8, MVT::i32));
2739
2740    Offset += LoadSize;
2741    RemainingSize -= LoadSize;
2742
2743    // Read second subword if necessary.
2744    if (RemainingSize != 0)  {
2745      assert(RemainingSize == 1 && "There must be one byte remaining.");
2746      LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2747                            DAG.getConstant(Offset, MVT::i32));
2748      unsigned Alignment = std::min(ByValAlign, (unsigned )2);
2749      SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2750                                       LoadPtr, MachinePointerInfo(),
2751                                       MVT::i8, false, false, Alignment);
2752      MemOpChains.push_back(Subword.getValue(1));
2753      // Insert the loaded byte to LoadVal.
2754      // FIXME: Use INS if supported by target.
2755      unsigned ShiftAmt = isLittle ? 16 : 8;
2756      SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
2757                                  DAG.getConstant(ShiftAmt, MVT::i32));
2758      LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
2759    }
2760
2761    unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2762    RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2763    return;
2764  }
2765
2766  // Copy remaining part of byval arg using memcpy.
2767  SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2768                            DAG.getConstant(Offset, MVT::i32));
2769  SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr,
2770                            DAG.getIntPtrConstant(LocMemOffset));
2771  Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2772                        DAG.getConstant(RemainingSize, MVT::i32),
2773                        std::min(ByValAlign, (unsigned)4),
2774                        /*isVolatile=*/false, /*AlwaysInline=*/false,
2775                        MachinePointerInfo(0), MachinePointerInfo(0));
2776  MemOpChains.push_back(Chain);
2777}
2778
2779// Copy Mips64 byVal arg to registers and stack.
2780void static
2781PassByValArg64(SDValue Chain, DebugLoc dl,
2782               SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
2783               SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
2784               MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
2785               const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
2786               EVT PtrTy, bool isLittle) {
2787  unsigned ByValSize = Flags.getByValSize();
2788  unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
2789  bool IsRegLoc = VA.isRegLoc();
2790  unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
2791  unsigned LocMemOffset = 0;
2792  unsigned MemCpySize = ByValSize;
2793
2794  if (!IsRegLoc)
2795    LocMemOffset = VA.getLocMemOffset();
2796  else {
2797    const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
2798                                    VA.getLocReg());
2799    const uint16_t *RegEnd = Mips64IntRegs + 8;
2800
2801    // Copy double words to registers.
2802    for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
2803      SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2804                                    DAG.getConstant(Offset, PtrTy));
2805      SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr,
2806                                    MachinePointerInfo(), false, false, false,
2807                                    Alignment);
2808      MemOpChains.push_back(LoadVal.getValue(1));
2809      RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
2810    }
2811
2812    // Return if the struct has been fully copied.
2813    if (!(MemCpySize = ByValSize - Offset))
2814      return;
2815
2816    // If there is an argument register available, copy the remainder of the
2817    // byval argument with sub-doubleword loads and shifts.
2818    if (Reg != RegEnd) {
2819      assert((ByValSize < Offset + 8) &&
2820             "Size of the remainder should be smaller than 8-byte.");
2821      SDValue Val;
2822      for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) {
2823        unsigned RemSize = ByValSize - Offset;
2824
2825        if (RemSize < LoadSize)
2826          continue;
2827
2828        SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2829                                      DAG.getConstant(Offset, PtrTy));
2830        SDValue LoadVal =
2831          DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr,
2832                         MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
2833                         false, false, Alignment);
2834        MemOpChains.push_back(LoadVal.getValue(1));
2835
2836        // Offset in number of bits from double word boundary.
2837        unsigned OffsetDW = (Offset % 8) * 8;
2838        unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8);
2839        SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal,
2840                                    DAG.getConstant(Shamt, MVT::i32));
2841
2842        Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) :
2843                              Shift;
2844        Offset += LoadSize;
2845        Alignment = std::min(Alignment, LoadSize);
2846      }
2847
2848      RegsToPass.push_back(std::make_pair(*Reg, Val));
2849      return;
2850    }
2851  }
2852
2853  assert(MemCpySize && "MemCpySize must not be zero.");
2854
2855  // Copy remainder of byval arg to it with memcpy.
2856  SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2857                            DAG.getConstant(Offset, PtrTy));
2858  SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr,
2859                            DAG.getIntPtrConstant(LocMemOffset));
2860  Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2861                        DAG.getConstant(MemCpySize, PtrTy), Alignment,
2862                        /*isVolatile=*/false, /*AlwaysInline=*/false,
2863                        MachinePointerInfo(0), MachinePointerInfo(0));
2864  MemOpChains.push_back(Chain);
2865}
2866
2867/// LowerCall - functions arguments are copied from virtual regs to
2868/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2869/// TODO: isTailCall.
2870SDValue
2871MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2872                              SmallVectorImpl<SDValue> &InVals) const {
2873  SelectionDAG &DAG                     = CLI.DAG;
2874  DebugLoc &dl                          = CLI.DL;
2875  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2876  SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
2877  SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
2878  SDValue Chain                         = CLI.Chain;
2879  SDValue Callee                        = CLI.Callee;
2880  bool &isTailCall                      = CLI.IsTailCall;
2881  CallingConv::ID CallConv              = CLI.CallConv;
2882  bool isVarArg                         = CLI.IsVarArg;
2883
2884  // MIPs target does not yet support tail call optimization.
2885  isTailCall = false;
2886
2887  MachineFunction &MF = DAG.getMachineFunction();
2888  MachineFrameInfo *MFI = MF.getFrameInfo();
2889  const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2890  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2891  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2892
2893  // Analyze operands of the call, assigning locations to each operand.
2894  SmallVector<CCValAssign, 16> ArgLocs;
2895  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2896                 getTargetMachine(), ArgLocs, *DAG.getContext());
2897
2898  if (CallConv == CallingConv::Fast)
2899    CCInfo.AnalyzeCallOperands(Outs, CC_Mips_FastCC);
2900  else if (IsO32)
2901    CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
2902  else if (HasMips64)
2903    AnalyzeMips64CallOperands(CCInfo, Outs);
2904  else
2905    CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
2906
2907  // Get a count of how many bytes are to be pushed on the stack.
2908  unsigned NextStackOffset = CCInfo.getNextStackOffset();
2909  unsigned StackAlignment = TFL->getStackAlignment();
2910  NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2911
2912  // Update size of the maximum argument space.
2913  // For O32, a minimum of four words (16 bytes) of argument space is
2914  // allocated.
2915  if (IsO32 && (CallConv != CallingConv::Fast))
2916    NextStackOffset = std::max(NextStackOffset, (unsigned)16);
2917
2918  // Chain is the output chain of the last Load/Store or CopyToReg node.
2919  // ByValChain is the output chain of the last Memcpy node created for copying
2920  // byval arguments to the stack.
2921  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2922  Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
2923
2924  SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
2925                                        IsN64 ? Mips::SP_64 : Mips::SP,
2926                                        getPointerTy());
2927
2928  if (MipsFI->getMaxCallFrameSize() < NextStackOffset)
2929    MipsFI->setMaxCallFrameSize(NextStackOffset);
2930
2931  // With EABI is it possible to have 16 args on registers.
2932  SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2933  SmallVector<SDValue, 8> MemOpChains;
2934
2935  // Walk the register/memloc assignments, inserting copies/loads.
2936  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2937    SDValue Arg = OutVals[i];
2938    CCValAssign &VA = ArgLocs[i];
2939    MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2940    ISD::ArgFlagsTy Flags = Outs[i].Flags;
2941
2942    // ByVal Arg.
2943    if (Flags.isByVal()) {
2944      assert(Flags.getByValSize() &&
2945             "ByVal args of size 0 should have been ignored by front-end.");
2946      if (IsO32)
2947        WriteByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr,
2948                      MFI, DAG, Arg, VA, Flags, getPointerTy(),
2949                      Subtarget->isLittle());
2950      else
2951        PassByValArg64(Chain, dl, RegsToPass, MemOpChains, StackPtr,
2952                       MFI, DAG, Arg, VA, Flags, getPointerTy(),
2953                       Subtarget->isLittle());
2954      continue;
2955    }
2956
2957    // Promote the value if needed.
2958    switch (VA.getLocInfo()) {
2959    default: llvm_unreachable("Unknown loc info!");
2960    case CCValAssign::Full:
2961      if (VA.isRegLoc()) {
2962        if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2963            (ValVT == MVT::f64 && LocVT == MVT::i64))
2964          Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2965        else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2966          SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2967                                   Arg, DAG.getConstant(0, MVT::i32));
2968          SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2969                                   Arg, DAG.getConstant(1, MVT::i32));
2970          if (!Subtarget->isLittle())
2971            std::swap(Lo, Hi);
2972          unsigned LocRegLo = VA.getLocReg();
2973          unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2974          RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2975          RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2976          continue;
2977        }
2978      }
2979      break;
2980    case CCValAssign::SExt:
2981      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
2982      break;
2983    case CCValAssign::ZExt:
2984      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
2985      break;
2986    case CCValAssign::AExt:
2987      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
2988      break;
2989    }
2990
2991    // Arguments that can be passed on register must be kept at
2992    // RegsToPass vector
2993    if (VA.isRegLoc()) {
2994      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2995      continue;
2996    }
2997
2998    // Register can't get to this point...
2999    assert(VA.isMemLoc());
3000
3001    // emit ISD::STORE whichs stores the
3002    // parameter value to a stack Location
3003    SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
3004                                 DAG.getIntPtrConstant(VA.getLocMemOffset()));
3005    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3006                                       MachinePointerInfo(), false, false, 0));
3007  }
3008
3009  // Transform all store nodes into one single node because all store
3010  // nodes are independent of each other.
3011  if (!MemOpChains.empty())
3012    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3013                        &MemOpChains[0], MemOpChains.size());
3014
3015  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3016  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3017  // node so that legalize doesn't hack it.
3018  unsigned char OpFlag;
3019  bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
3020  bool GlobalOrExternal = false;
3021  SDValue CalleeLo;
3022
3023  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3024    if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
3025      OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
3026      unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
3027      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
3028                                          OpFlag);
3029      CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
3030                                            0, LoFlag);
3031    } else {
3032      OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
3033      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3034                                          getPointerTy(), 0, OpFlag);
3035    }
3036
3037    GlobalOrExternal = true;
3038  }
3039  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3040    if (IsN64 || (!IsO32 && IsPIC))
3041      OpFlag = MipsII::MO_GOT_DISP;
3042    else if (!IsPIC) // !N64 && static
3043      OpFlag = MipsII::MO_NO_FLAG;
3044    else // O32 & PIC
3045      OpFlag = MipsII::MO_GOT_CALL;
3046    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3047                                         OpFlag);
3048    GlobalOrExternal = true;
3049  }
3050
3051  SDValue InFlag;
3052
3053  // Create nodes that load address of callee and copy it to T9
3054  if (IsPICCall) {
3055    if (GlobalOrExternal) {
3056      // Load callee address
3057      Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
3058                           GetGlobalReg(DAG, getPointerTy()), Callee);
3059      SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
3060                                      Callee, MachinePointerInfo::getGOT(),
3061                                      false, false, false, 0);
3062
3063      // Use GOT+LO if callee has internal linkage.
3064      if (CalleeLo.getNode()) {
3065        SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
3066        Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
3067      } else
3068        Callee = LoadValue;
3069    }
3070  }
3071
3072  // T9 register operand.
3073  SDValue T9;
3074
3075  // T9 should contain the address of the callee function if
3076  // -reloction-model=pic or it is an indirect call.
3077  if (IsPICCall || !GlobalOrExternal) {
3078    // copy to T9
3079    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
3080    Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
3081    InFlag = Chain.getValue(1);
3082
3083    if (Subtarget->inMips16Mode())
3084      T9 = DAG.getRegister(T9Reg, getPointerTy());
3085    else
3086      Callee = DAG.getRegister(T9Reg, getPointerTy());
3087  }
3088
3089  // Insert node "GP copy globalreg" before call to function.
3090  // Lazy-binding stubs require GP to point to the GOT.
3091  if (IsPICCall) {
3092    unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
3093    EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
3094    RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
3095  }
3096
3097  // Build a sequence of copy-to-reg nodes chained together with token
3098  // chain and flag operands which copy the outgoing args into registers.
3099  // The InFlag in necessary since all emitted instructions must be
3100  // stuck together.
3101  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3102    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3103                             RegsToPass[i].second, InFlag);
3104    InFlag = Chain.getValue(1);
3105  }
3106
3107  // MipsJmpLink = #chain, #target_address, #opt_in_flags...
3108  //             = Chain, Callee, Reg#1, Reg#2, ...
3109  //
3110  // Returns a chain & a flag for retval copy to use.
3111  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3112  SmallVector<SDValue, 8> Ops;
3113  Ops.push_back(Chain);
3114  Ops.push_back(Callee);
3115
3116  // Add argument registers to the end of the list so that they are
3117  // known live into the call.
3118  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3119    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3120                                  RegsToPass[i].second.getValueType()));
3121
3122  // Add T9 register operand.
3123  if (T9.getNode())
3124    Ops.push_back(T9);
3125
3126  // Add a register mask operand representing the call-preserved registers.
3127  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3128  const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3129  assert(Mask && "Missing call preserved mask for calling convention");
3130  Ops.push_back(DAG.getRegisterMask(Mask));
3131
3132  if (InFlag.getNode())
3133    Ops.push_back(InFlag);
3134
3135  Chain  = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
3136  InFlag = Chain.getValue(1);
3137
3138  // Create the CALLSEQ_END node.
3139  Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3140                             DAG.getIntPtrConstant(0, true), InFlag);
3141  InFlag = Chain.getValue(1);
3142
3143  // Handle result values, copying them out of physregs into vregs that we
3144  // return.
3145  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3146                         Ins, dl, DAG, InVals);
3147}
3148
3149/// LowerCallResult - Lower the result values of a call into the
3150/// appropriate copies out of appropriate physical registers.
3151SDValue
3152MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3153                                    CallingConv::ID CallConv, bool isVarArg,
3154                                    const SmallVectorImpl<ISD::InputArg> &Ins,
3155                                    DebugLoc dl, SelectionDAG &DAG,
3156                                    SmallVectorImpl<SDValue> &InVals) const {
3157  // Assign locations to each value returned by this call.
3158  SmallVector<CCValAssign, 16> RVLocs;
3159  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3160                 getTargetMachine(), RVLocs, *DAG.getContext());
3161
3162  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
3163
3164  // Copy all of the result registers out of their specified physreg.
3165  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3166    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
3167                               RVLocs[i].getValVT(), InFlag).getValue(1);
3168    InFlag = Chain.getValue(2);
3169    InVals.push_back(Chain.getValue(0));
3170  }
3171
3172  return Chain;
3173}
3174
3175//===----------------------------------------------------------------------===//
3176//             Formal Arguments Calling Convention Implementation
3177//===----------------------------------------------------------------------===//
3178static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
3179                         std::vector<SDValue> &OutChains,
3180                         SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
3181                         const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
3182                         const Argument *FuncArg) {
3183  unsigned LocMem = VA.getLocMemOffset();
3184  unsigned FirstWord = LocMem / 4;
3185
3186  // copy register A0 - A3 to frame object
3187  for (unsigned i = 0; i < NumWords; ++i) {
3188    unsigned CurWord = FirstWord + i;
3189    if (CurWord >= O32IntRegsSize)
3190      break;
3191
3192    unsigned SrcReg = O32IntRegs[CurWord];
3193    unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
3194    SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
3195                                   DAG.getConstant(i * 4, MVT::i32));
3196    SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
3197                                 StorePtr, MachinePointerInfo(FuncArg, i * 4),
3198                                 false, false, 0);
3199    OutChains.push_back(Store);
3200  }
3201}
3202
3203// Create frame object on stack and copy registers used for byval passing to it.
3204static unsigned
3205CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
3206                    std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3207                    const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
3208                    MachineFrameInfo *MFI, bool IsRegLoc,
3209                    SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
3210                    EVT PtrTy, const Argument *FuncArg) {
3211  const uint16_t *Reg = Mips64IntRegs + 8;
3212  int FOOffset; // Frame object offset from virtual frame pointer.
3213
3214  if (IsRegLoc) {
3215    Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
3216    FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
3217  }
3218  else
3219    FOOffset = VA.getLocMemOffset();
3220
3221  // Create frame object.
3222  unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
3223  unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
3224  SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
3225  InVals.push_back(FIN);
3226
3227  // Copy arg registers.
3228  for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
3229       ++Reg, ++I) {
3230    unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
3231    SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
3232                                   DAG.getConstant(I * 8, PtrTy));
3233    SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
3234                                 StorePtr, MachinePointerInfo(FuncArg, I * 8),
3235                                 false, false, 0);
3236    OutChains.push_back(Store);
3237  }
3238
3239  return LastFI;
3240}
3241
3242/// LowerFormalArguments - transform physical registers into virtual registers
3243/// and generate load operations for arguments places on the stack.
3244SDValue
3245MipsTargetLowering::LowerFormalArguments(SDValue Chain,
3246                                         CallingConv::ID CallConv,
3247                                         bool isVarArg,
3248                                      const SmallVectorImpl<ISD::InputArg> &Ins,
3249                                         DebugLoc dl, SelectionDAG &DAG,
3250                                         SmallVectorImpl<SDValue> &InVals)
3251                                          const {
3252  MachineFunction &MF = DAG.getMachineFunction();
3253  MachineFrameInfo *MFI = MF.getFrameInfo();
3254  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3255
3256  MipsFI->setVarArgsFrameIndex(0);
3257
3258  // Used with vargs to acumulate store chains.
3259  std::vector<SDValue> OutChains;
3260
3261  // Assign locations to all of the incoming arguments.
3262  SmallVector<CCValAssign, 16> ArgLocs;
3263  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3264                 getTargetMachine(), ArgLocs, *DAG.getContext());
3265
3266  if (CallConv == CallingConv::Fast)
3267    CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FastCC);
3268  else if (IsO32)
3269    CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
3270  else
3271    CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
3272
3273  Function::const_arg_iterator FuncArg =
3274    DAG.getMachineFunction().getFunction()->arg_begin();
3275  int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
3276
3277  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
3278    CCValAssign &VA = ArgLocs[i];
3279    EVT ValVT = VA.getValVT();
3280    ISD::ArgFlagsTy Flags = Ins[i].Flags;
3281    bool IsRegLoc = VA.isRegLoc();
3282
3283    if (Flags.isByVal()) {
3284      assert(Flags.getByValSize() &&
3285             "ByVal args of size 0 should have been ignored by front-end.");
3286      if (IsO32) {
3287        unsigned NumWords = (Flags.getByValSize() + 3) / 4;
3288        LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
3289                                        true);
3290        SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
3291        InVals.push_back(FIN);
3292        ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags,
3293                     &*FuncArg);
3294      } else // N32/64
3295        LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags,
3296                                     MFI, IsRegLoc, InVals, MipsFI,
3297                                     getPointerTy(), &*FuncArg);
3298      continue;
3299    }
3300
3301    // Arguments stored on registers
3302    if (IsRegLoc) {
3303      EVT RegVT = VA.getLocVT();
3304      unsigned ArgReg = VA.getLocReg();
3305      const TargetRegisterClass *RC;
3306
3307      if (RegVT == MVT::i32)
3308        RC = &Mips::CPURegsRegClass;
3309      else if (RegVT == MVT::i64)
3310        RC = &Mips::CPU64RegsRegClass;
3311      else if (RegVT == MVT::f32)
3312        RC = &Mips::FGR32RegClass;
3313      else if (RegVT == MVT::f64)
3314        RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
3315      else
3316        llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3317
3318      // Transform the arguments stored on
3319      // physical registers into virtual ones
3320      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3321      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3322
3323      // If this is an 8 or 16-bit value, it has been passed promoted
3324      // to 32 bits.  Insert an assert[sz]ext to capture this, then
3325      // truncate to the right size.
3326      if (VA.getLocInfo() != CCValAssign::Full) {
3327        unsigned Opcode = 0;
3328        if (VA.getLocInfo() == CCValAssign::SExt)
3329          Opcode = ISD::AssertSext;
3330        else if (VA.getLocInfo() == CCValAssign::ZExt)
3331          Opcode = ISD::AssertZext;
3332        if (Opcode)
3333          ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3334                                 DAG.getValueType(ValVT));
3335        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
3336      }
3337
3338      // Handle floating point arguments passed in integer registers.
3339      if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3340          (RegVT == MVT::i64 && ValVT == MVT::f64))
3341        ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3342      else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3343        unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3344                                  getNextIntArgReg(ArgReg), RC);
3345        SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3346        if (!Subtarget->isLittle())
3347          std::swap(ArgValue, ArgValue2);
3348        ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3349                               ArgValue, ArgValue2);
3350      }
3351
3352      InVals.push_back(ArgValue);
3353    } else { // VA.isRegLoc()
3354
3355      // sanity check
3356      assert(VA.isMemLoc());
3357
3358      // The stack pointer offset is relative to the caller stack frame.
3359      LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
3360                                      VA.getLocMemOffset(), true);
3361
3362      // Create load nodes to retrieve arguments from the stack
3363      SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
3364      InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
3365                                   MachinePointerInfo::getFixedStack(LastFI),
3366                                   false, false, false, 0));
3367    }
3368  }
3369
3370  // The mips ABIs for returning structs by value requires that we copy
3371  // the sret argument into $v0 for the return. Save the argument into
3372  // a virtual register so that we can access it from the return points.
3373  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3374    unsigned Reg = MipsFI->getSRetReturnReg();
3375    if (!Reg) {
3376      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
3377      MipsFI->setSRetReturnReg(Reg);
3378    }
3379    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
3380    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3381  }
3382
3383  if (isVarArg) {
3384    unsigned NumOfRegs = IsO32 ? 4 : 8;
3385    const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
3386    unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
3387    int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
3388    const TargetRegisterClass *RC = IsO32 ?
3389      (const TargetRegisterClass*)&Mips::CPURegsRegClass :
3390      (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
3391    unsigned RegSize = RC->getSize();
3392    int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
3393
3394    // Offset of the first variable argument from stack pointer.
3395    int FirstVaArgOffset;
3396
3397    if (IsO32 || (Idx == NumOfRegs)) {
3398      FirstVaArgOffset =
3399        (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
3400    } else
3401      FirstVaArgOffset = RegSlotOffset;
3402
3403    // Record the frame index of the first variable argument
3404    // which is a value necessary to VASTART.
3405    LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
3406    MipsFI->setVarArgsFrameIndex(LastFI);
3407
3408    // Copy the integer registers that have not been used for argument passing
3409    // to the argument register save area. For O32, the save area is allocated
3410    // in the caller's stack frame, while for N32/64, it is allocated in the
3411    // callee's stack frame.
3412    for (int StackOffset = RegSlotOffset;
3413         Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
3414      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
3415      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3416                                            MVT::getIntegerVT(RegSize * 8));
3417      LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
3418      SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
3419      OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
3420                                       MachinePointerInfo(), false, false, 0));
3421    }
3422  }
3423
3424  MipsFI->setLastInArgFI(LastFI);
3425
3426  // All stores are grouped in one node to allow the matching between
3427  // the size of Ins and InVals. This only happens when on varg functions
3428  if (!OutChains.empty()) {
3429    OutChains.push_back(Chain);
3430    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3431                        &OutChains[0], OutChains.size());
3432  }
3433
3434  return Chain;
3435}
3436
3437//===----------------------------------------------------------------------===//
3438//               Return Value Calling Convention Implementation
3439//===----------------------------------------------------------------------===//
3440
3441SDValue
3442MipsTargetLowering::LowerReturn(SDValue Chain,
3443                                CallingConv::ID CallConv, bool isVarArg,
3444                                const SmallVectorImpl<ISD::OutputArg> &Outs,
3445                                const SmallVectorImpl<SDValue> &OutVals,
3446                                DebugLoc dl, SelectionDAG &DAG) const {
3447
3448  // CCValAssign - represent the assignment of
3449  // the return value to a location
3450  SmallVector<CCValAssign, 16> RVLocs;
3451
3452  // CCState - Info about the registers and stack slot.
3453  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3454                 getTargetMachine(), RVLocs, *DAG.getContext());
3455
3456  // Analize return values.
3457  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3458
3459  // If this is the first return lowered for this function, add
3460  // the regs to the liveout set for the function.
3461  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3462    for (unsigned i = 0; i != RVLocs.size(); ++i)
3463      if (RVLocs[i].isRegLoc())
3464        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3465  }
3466
3467  SDValue Flag;
3468
3469  // Copy the result values into the output registers.
3470  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3471    CCValAssign &VA = RVLocs[i];
3472    assert(VA.isRegLoc() && "Can only return in registers!");
3473
3474    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
3475
3476    // guarantee that all emitted copies are
3477    // stuck together, avoiding something bad
3478    Flag = Chain.getValue(1);
3479  }
3480
3481  // The mips ABIs for returning structs by value requires that we copy
3482  // the sret argument into $v0 for the return. We saved the argument into
3483  // a virtual register in the entry block, so now we copy the value out
3484  // and into $v0.
3485  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3486    MachineFunction &MF      = DAG.getMachineFunction();
3487    MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3488    unsigned Reg = MipsFI->getSRetReturnReg();
3489
3490    if (!Reg)
3491      llvm_unreachable("sret virtual register not created in the entry block");
3492    SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
3493
3494    Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
3495    Flag = Chain.getValue(1);
3496  }
3497
3498  // Return on Mips is always a "jr $ra"
3499  if (Flag.getNode())
3500    return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag);
3501
3502  // Return Void
3503  return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain);
3504}
3505
3506//===----------------------------------------------------------------------===//
3507//                           Mips Inline Assembly Support
3508//===----------------------------------------------------------------------===//
3509
3510/// getConstraintType - Given a constraint letter, return the type of
3511/// constraint it is for this target.
3512MipsTargetLowering::ConstraintType MipsTargetLowering::
3513getConstraintType(const std::string &Constraint) const
3514{
3515  // Mips specific constrainy
3516  // GCC config/mips/constraints.md
3517  //
3518  // 'd' : An address register. Equivalent to r
3519  //       unless generating MIPS16 code.
3520  // 'y' : Equivalent to r; retained for
3521  //       backwards compatibility.
3522  // 'c' : A register suitable for use in an indirect
3523  //       jump. This will always be $25 for -mabicalls.
3524  // 'l' : The lo register. 1 word storage.
3525  // 'x' : The hilo register pair. Double word storage.
3526  if (Constraint.size() == 1) {
3527    switch (Constraint[0]) {
3528      default : break;
3529      case 'd':
3530      case 'y':
3531      case 'f':
3532      case 'c':
3533      case 'l':
3534      case 'x':
3535        return C_RegisterClass;
3536    }
3537  }
3538  return TargetLowering::getConstraintType(Constraint);
3539}
3540
3541/// Examine constraint type and operand type and determine a weight value.
3542/// This object must already have been set up with the operand type
3543/// and the current alternative constraint selected.
3544TargetLowering::ConstraintWeight
3545MipsTargetLowering::getSingleConstraintMatchWeight(
3546    AsmOperandInfo &info, const char *constraint) const {
3547  ConstraintWeight weight = CW_Invalid;
3548  Value *CallOperandVal = info.CallOperandVal;
3549    // If we don't have a value, we can't do a match,
3550    // but allow it at the lowest weight.
3551  if (CallOperandVal == NULL)
3552    return CW_Default;
3553  Type *type = CallOperandVal->getType();
3554  // Look at the constraint type.
3555  switch (*constraint) {
3556  default:
3557    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3558    break;
3559  case 'd':
3560  case 'y':
3561    if (type->isIntegerTy())
3562      weight = CW_Register;
3563    break;
3564  case 'f':
3565    if (type->isFloatTy())
3566      weight = CW_Register;
3567    break;
3568  case 'c': // $25 for indirect jumps
3569  case 'l': // lo register
3570  case 'x': // hilo register pair
3571      if (type->isIntegerTy())
3572      weight = CW_SpecificReg;
3573      break;
3574  case 'I': // signed 16 bit immediate
3575  case 'J': // integer zero
3576  case 'K': // unsigned 16 bit immediate
3577  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3578  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3579  case 'O': // signed 15 bit immediate (+- 16383)
3580  case 'P': // immediate in the range of 65535 to 1 (inclusive)
3581    if (isa<ConstantInt>(CallOperandVal))
3582      weight = CW_Constant;
3583    break;
3584  }
3585  return weight;
3586}
3587
3588/// Given a register class constraint, like 'r', if this corresponds directly
3589/// to an LLVM register class, return a register of 0 and the register class
3590/// pointer.
3591std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3592getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
3593{
3594  if (Constraint.size() == 1) {
3595    switch (Constraint[0]) {
3596    case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3597    case 'y': // Same as 'r'. Exists for compatibility.
3598    case 'r':
3599      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3600        if (Subtarget->inMips16Mode())
3601          return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3602        return std::make_pair(0U, &Mips::CPURegsRegClass);
3603      }
3604      if (VT == MVT::i64 && !HasMips64)
3605        return std::make_pair(0U, &Mips::CPURegsRegClass);
3606      if (VT == MVT::i64 && HasMips64)
3607        return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3608      // This will generate an error message
3609      return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3610    case 'f':
3611      if (VT == MVT::f32)
3612        return std::make_pair(0U, &Mips::FGR32RegClass);
3613      if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3614        if (Subtarget->isFP64bit())
3615          return std::make_pair(0U, &Mips::FGR64RegClass);
3616        return std::make_pair(0U, &Mips::AFGR64RegClass);
3617      }
3618      break;
3619    case 'c': // register suitable for indirect jump
3620      if (VT == MVT::i32)
3621        return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3622      assert(VT == MVT::i64 && "Unexpected type.");
3623      return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
3624    case 'l': // register suitable for indirect jump
3625      if (VT == MVT::i32)
3626        return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3627      return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
3628    case 'x': // register suitable for indirect jump
3629      // Fixme: Not triggering the use of both hi and low
3630      // This will generate an error message
3631      return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3632    }
3633  }
3634  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3635}
3636
3637/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3638/// vector.  If it is invalid, don't add anything to Ops.
3639void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3640                                                     std::string &Constraint,
3641                                                     std::vector<SDValue>&Ops,
3642                                                     SelectionDAG &DAG) const {
3643  SDValue Result(0, 0);
3644
3645  // Only support length 1 constraints for now.
3646  if (Constraint.length() > 1) return;
3647
3648  char ConstraintLetter = Constraint[0];
3649  switch (ConstraintLetter) {
3650  default: break; // This will fall through to the generic implementation
3651  case 'I': // Signed 16 bit constant
3652    // If this fails, the parent routine will give an error
3653    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3654      EVT Type = Op.getValueType();
3655      int64_t Val = C->getSExtValue();
3656      if (isInt<16>(Val)) {
3657        Result = DAG.getTargetConstant(Val, Type);
3658        break;
3659      }
3660    }
3661    return;
3662  case 'J': // integer zero
3663    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3664      EVT Type = Op.getValueType();
3665      int64_t Val = C->getZExtValue();
3666      if (Val == 0) {
3667        Result = DAG.getTargetConstant(0, Type);
3668        break;
3669      }
3670    }
3671    return;
3672  case 'K': // unsigned 16 bit immediate
3673    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3674      EVT Type = Op.getValueType();
3675      uint64_t Val = (uint64_t)C->getZExtValue();
3676      if (isUInt<16>(Val)) {
3677        Result = DAG.getTargetConstant(Val, Type);
3678        break;
3679      }
3680    }
3681    return;
3682  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3683    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3684      EVT Type = Op.getValueType();
3685      int64_t Val = C->getSExtValue();
3686      if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3687        Result = DAG.getTargetConstant(Val, Type);
3688        break;
3689      }
3690    }
3691    return;
3692  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3693    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3694      EVT Type = Op.getValueType();
3695      int64_t Val = C->getSExtValue();
3696      if ((Val >= -65535) && (Val <= -1)) {
3697        Result = DAG.getTargetConstant(Val, Type);
3698        break;
3699      }
3700    }
3701    return;
3702  case 'O': // signed 15 bit immediate
3703    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3704      EVT Type = Op.getValueType();
3705      int64_t Val = C->getSExtValue();
3706      if ((isInt<15>(Val))) {
3707        Result = DAG.getTargetConstant(Val, Type);
3708        break;
3709      }
3710    }
3711    return;
3712  case 'P': // immediate in the range of 1 to 65535 (inclusive)
3713    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3714      EVT Type = Op.getValueType();
3715      int64_t Val = C->getSExtValue();
3716      if ((Val <= 65535) && (Val >= 1)) {
3717        Result = DAG.getTargetConstant(Val, Type);
3718        break;
3719      }
3720    }
3721    return;
3722  }
3723
3724  if (Result.getNode()) {
3725    Ops.push_back(Result);
3726    return;
3727  }
3728
3729  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3730}
3731
3732bool
3733MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3734  // The Mips target isn't yet aware of offsets.
3735  return false;
3736}
3737
3738EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3739                                            unsigned SrcAlign, bool IsZeroVal,
3740                                            bool MemcpyStrSrc,
3741                                            MachineFunction &MF) const {
3742  if (Subtarget->hasMips64())
3743    return MVT::i64;
3744
3745  return MVT::i32;
3746}
3747
3748bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3749  if (VT != MVT::f32 && VT != MVT::f64)
3750    return false;
3751  if (Imm.isNegZero())
3752    return false;
3753  return Imm.isZero();
3754}
3755
3756unsigned MipsTargetLowering::getJumpTableEncoding() const {
3757  if (IsN64)
3758    return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3759
3760  return TargetLowering::getJumpTableEncoding();
3761}
3762