1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPerfectShuffle.h" 17#include "PPCTargetMachine.h" 18#include "MCTargetDesc/PPCPredicates.h" 19#include "llvm/CallingConv.h" 20#include "llvm/Constants.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/Intrinsics.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/CodeGen/CallingConvLower.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/Target/TargetOptions.h" 37using namespace llvm; 38 39static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 40 CCValAssign::LocInfo &LocInfo, 41 ISD::ArgFlagsTy &ArgFlags, 42 CCState &State); 43static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 44 MVT &LocVT, 45 CCValAssign::LocInfo &LocInfo, 46 ISD::ArgFlagsTy &ArgFlags, 47 CCState &State); 48static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 49 MVT &LocVT, 50 CCValAssign::LocInfo &LocInfo, 51 ISD::ArgFlagsTy &ArgFlags, 52 CCState &State); 53 54static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", 55cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); 56 57static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", 58cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>(); 70 71 setPow2DivIsCheap(); 72 73 // Use _setjmp/_longjmp instead of setjmp/longjmp. 74 setUseUnderscoreSetJmp(true); 75 setUseUnderscoreLongJmp(true); 76 77 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 78 // arguments are at least 4/8 bytes aligned. 79 bool isPPC64 = Subtarget->isPPC64(); 80 setMinStackArgumentAlignment(isPPC64 ? 8:4); 81 82 // Set up the register classes. 83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); 84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); 85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); 86 87 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 90 91 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 92 93 // PowerPC has pre-inc load and store's. 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 97 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 100 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 101 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 102 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 103 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 104 105 // This is used in the ppcf128->int sequence. Note it has different semantics 106 // from FP_ROUND: that rounds to nearest, this rounds to zero. 107 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 108 109 // We do not currently implement these libm ops for PowerPC. 110 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); 111 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); 112 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); 113 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); 114 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); 115 116 // PowerPC has no SREM/UREM instructions 117 setOperationAction(ISD::SREM, MVT::i32, Expand); 118 setOperationAction(ISD::UREM, MVT::i32, Expand); 119 setOperationAction(ISD::SREM, MVT::i64, Expand); 120 setOperationAction(ISD::UREM, MVT::i64, Expand); 121 122 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 123 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 124 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 126 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 127 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 128 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 129 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 130 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 131 132 // We don't support sin/cos/sqrt/fmod/pow 133 setOperationAction(ISD::FSIN , MVT::f64, Expand); 134 setOperationAction(ISD::FCOS , MVT::f64, Expand); 135 setOperationAction(ISD::FREM , MVT::f64, Expand); 136 setOperationAction(ISD::FPOW , MVT::f64, Expand); 137 setOperationAction(ISD::FMA , MVT::f64, Legal); 138 setOperationAction(ISD::FSIN , MVT::f32, Expand); 139 setOperationAction(ISD::FCOS , MVT::f32, Expand); 140 setOperationAction(ISD::FREM , MVT::f32, Expand); 141 setOperationAction(ISD::FPOW , MVT::f32, Expand); 142 setOperationAction(ISD::FMA , MVT::f32, Legal); 143 144 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 145 146 // If we're enabling GP optimizations, use hardware square root 147 if (!Subtarget->hasFSQRT()) { 148 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 149 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 150 } 151 152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 154 155 // PowerPC does not have BSWAP, CTPOP or CTTZ 156 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 157 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 158 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 160 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 161 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 162 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 163 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 164 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 165 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 166 167 // PowerPC does not have ROTR 168 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 169 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 170 171 // PowerPC does not have Select 172 setOperationAction(ISD::SELECT, MVT::i32, Expand); 173 setOperationAction(ISD::SELECT, MVT::i64, Expand); 174 setOperationAction(ISD::SELECT, MVT::f32, Expand); 175 setOperationAction(ISD::SELECT, MVT::f64, Expand); 176 177 // PowerPC wants to turn select_cc of FP into fsel when possible. 178 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 179 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 180 181 // PowerPC wants to optimize integer setcc a bit 182 setOperationAction(ISD::SETCC, MVT::i32, Custom); 183 184 // PowerPC does not have BRCOND which requires SetCC 185 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 186 187 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 188 189 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 190 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 191 192 // PowerPC does not have [U|S]INT_TO_FP 193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 194 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 195 196 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 197 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 198 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 199 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 200 201 // We cannot sextinreg(i1). Expand to shifts. 202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 203 204 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 205 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 206 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 207 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 208 209 210 // We want to legalize GlobalAddress and ConstantPool nodes into the 211 // appropriate instructions to materialize the address. 212 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 213 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 214 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 216 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 217 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 218 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 219 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 220 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 221 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 222 223 // TRAP is legal. 224 setOperationAction(ISD::TRAP, MVT::Other, Legal); 225 226 // TRAMPOLINE is custom lowered. 227 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 228 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 229 230 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 231 setOperationAction(ISD::VASTART , MVT::Other, Custom); 232 233 if (Subtarget->isSVR4ABI()) { 234 if (isPPC64) { 235 // VAARG always uses double-word chunks, so promote anything smaller. 236 setOperationAction(ISD::VAARG, MVT::i1, Promote); 237 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); 238 setOperationAction(ISD::VAARG, MVT::i8, Promote); 239 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); 240 setOperationAction(ISD::VAARG, MVT::i16, Promote); 241 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); 242 setOperationAction(ISD::VAARG, MVT::i32, Promote); 243 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); 244 setOperationAction(ISD::VAARG, MVT::Other, Expand); 245 } else { 246 // VAARG is custom lowered with the 32-bit SVR4 ABI. 247 setOperationAction(ISD::VAARG, MVT::Other, Custom); 248 setOperationAction(ISD::VAARG, MVT::i64, Custom); 249 } 250 } else 251 setOperationAction(ISD::VAARG, MVT::Other, Expand); 252 253 // Use the default implementation. 254 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 255 setOperationAction(ISD::VAEND , MVT::Other, Expand); 256 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 257 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 258 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 259 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 260 261 // We want to custom lower some of our intrinsics. 262 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 263 264 // Comparisons that require checking two conditions. 265 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 266 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 267 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 268 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 269 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 270 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 271 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 272 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 273 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 274 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 275 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 276 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 277 278 if (Subtarget->has64BitSupport()) { 279 // They also have instructions for converting between i64 and fp. 280 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 281 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 282 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 283 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 284 // This is just the low 32 bits of a (signed) fp->i64 conversion. 285 // We cannot do this with Promote because i64 is not a legal type. 286 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 287 288 // FIXME: disable this lowered code. This generates 64-bit register values, 289 // and we don't model the fact that the top part is clobbered by calls. We 290 // need to flag these together so that the value isn't live across a call. 291 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 292 } else { 293 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 294 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 295 } 296 297 if (Subtarget->use64BitRegs()) { 298 // 64-bit PowerPC implementations can support i64 types directly 299 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); 300 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 301 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 302 // 64-bit PowerPC wants to expand i128 shifts itself. 303 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 304 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 305 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 306 } else { 307 // 32-bit PowerPC wants to expand i64 shifts itself. 308 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 309 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 310 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 311 } 312 313 if (Subtarget->hasAltivec()) { 314 // First set operation action for all vector types to expand. Then we 315 // will selectively turn on ones that can be effectively codegen'd. 316 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 317 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 318 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 319 320 // add/sub are legal for all supported vector VT's. 321 setOperationAction(ISD::ADD , VT, Legal); 322 setOperationAction(ISD::SUB , VT, Legal); 323 324 // We promote all shuffles to v16i8. 325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 326 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 327 328 // We promote all non-typed operations to v4i32. 329 setOperationAction(ISD::AND , VT, Promote); 330 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 331 setOperationAction(ISD::OR , VT, Promote); 332 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 333 setOperationAction(ISD::XOR , VT, Promote); 334 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 335 setOperationAction(ISD::LOAD , VT, Promote); 336 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 337 setOperationAction(ISD::SELECT, VT, Promote); 338 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 339 setOperationAction(ISD::STORE, VT, Promote); 340 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 341 342 // No other operations are legal. 343 setOperationAction(ISD::MUL , VT, Expand); 344 setOperationAction(ISD::SDIV, VT, Expand); 345 setOperationAction(ISD::SREM, VT, Expand); 346 setOperationAction(ISD::UDIV, VT, Expand); 347 setOperationAction(ISD::UREM, VT, Expand); 348 setOperationAction(ISD::FDIV, VT, Expand); 349 setOperationAction(ISD::FNEG, VT, Expand); 350 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 351 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 352 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 353 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 354 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 355 setOperationAction(ISD::UDIVREM, VT, Expand); 356 setOperationAction(ISD::SDIVREM, VT, Expand); 357 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 358 setOperationAction(ISD::FPOW, VT, Expand); 359 setOperationAction(ISD::CTPOP, VT, Expand); 360 setOperationAction(ISD::CTLZ, VT, Expand); 361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 362 setOperationAction(ISD::CTTZ, VT, Expand); 363 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 364 } 365 366 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 367 // with merges, splats, etc. 368 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 369 370 setOperationAction(ISD::AND , MVT::v4i32, Legal); 371 setOperationAction(ISD::OR , MVT::v4i32, Legal); 372 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 373 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 374 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 375 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 376 377 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); 378 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); 379 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); 380 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); 381 382 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 383 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 384 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 385 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 386 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 387 388 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 389 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 390 391 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 392 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 393 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 394 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 395 } 396 397 if (Subtarget->has64BitSupport()) { 398 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); 399 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); 400 } 401 402 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 403 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 404 405 setBooleanContents(ZeroOrOneBooleanContent); 406 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 407 408 if (isPPC64) { 409 setStackPointerRegisterToSaveRestore(PPC::X1); 410 setExceptionPointerRegister(PPC::X3); 411 setExceptionSelectorRegister(PPC::X4); 412 } else { 413 setStackPointerRegisterToSaveRestore(PPC::R1); 414 setExceptionPointerRegister(PPC::R3); 415 setExceptionSelectorRegister(PPC::R4); 416 } 417 418 // We have target-specific dag combine patterns for the following nodes: 419 setTargetDAGCombine(ISD::SINT_TO_FP); 420 setTargetDAGCombine(ISD::STORE); 421 setTargetDAGCombine(ISD::BR_CC); 422 setTargetDAGCombine(ISD::BSWAP); 423 424 // Darwin long double math library functions have $LDBL128 appended. 425 if (Subtarget->isDarwin()) { 426 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 427 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 428 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 429 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 430 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 431 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 432 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 433 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 434 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 435 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 436 } 437 438 setMinFunctionAlignment(2); 439 if (PPCSubTarget.isDarwin()) 440 setPrefFunctionAlignment(4); 441 442 if (isPPC64 && Subtarget->isJITCodeModel()) 443 // Temporary workaround for the inability of PPC64 JIT to handle jump 444 // tables. 445 setSupportJumpTables(false); 446 447 setInsertFencesForAtomic(true); 448 449 setSchedulingPreference(Sched::Hybrid); 450 451 computeRegisterProperties(); 452 453 // The Freescale cores does better with aggressive inlining of memcpy and 454 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores). 455 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc || 456 Subtarget->getDarwinDirective() == PPC::DIR_E5500) { 457 maxStoresPerMemset = 32; 458 maxStoresPerMemsetOptSize = 16; 459 maxStoresPerMemcpy = 32; 460 maxStoresPerMemcpyOptSize = 8; 461 maxStoresPerMemmove = 32; 462 maxStoresPerMemmoveOptSize = 8; 463 464 setPrefFunctionAlignment(4); 465 benefitFromCodePlacementOpt = true; 466 } 467} 468 469/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 470/// function arguments in the caller parameter area. 471unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const { 472 const TargetMachine &TM = getTargetMachine(); 473 // Darwin passes everything on 4 byte boundary. 474 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 475 return 4; 476 477 // 16byte and wider vectors are passed on 16byte boundary. 478 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) 479 if (VTy->getBitWidth() >= 128) 480 return 16; 481 482 // The rest is 8 on PPC64 and 4 on PPC32 boundary. 483 if (PPCSubTarget.isPPC64()) 484 return 8; 485 486 return 4; 487} 488 489const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 490 switch (Opcode) { 491 default: return 0; 492 case PPCISD::FSEL: return "PPCISD::FSEL"; 493 case PPCISD::FCFID: return "PPCISD::FCFID"; 494 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 495 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 496 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 497 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 498 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 499 case PPCISD::VPERM: return "PPCISD::VPERM"; 500 case PPCISD::Hi: return "PPCISD::Hi"; 501 case PPCISD::Lo: return "PPCISD::Lo"; 502 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 503 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 504 case PPCISD::LOAD: return "PPCISD::LOAD"; 505 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 506 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 507 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 508 case PPCISD::SRL: return "PPCISD::SRL"; 509 case PPCISD::SRA: return "PPCISD::SRA"; 510 case PPCISD::SHL: return "PPCISD::SHL"; 511 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 512 case PPCISD::STD_32: return "PPCISD::STD_32"; 513 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 514 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4"; 515 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 516 case PPCISD::NOP: return "PPCISD::NOP"; 517 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 518 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 519 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 520 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 521 case PPCISD::MFCR: return "PPCISD::MFCR"; 522 case PPCISD::VCMP: return "PPCISD::VCMP"; 523 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 524 case PPCISD::LBRX: return "PPCISD::LBRX"; 525 case PPCISD::STBRX: return "PPCISD::STBRX"; 526 case PPCISD::LARX: return "PPCISD::LARX"; 527 case PPCISD::STCX: return "PPCISD::STCX"; 528 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 529 case PPCISD::MFFS: return "PPCISD::MFFS"; 530 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 531 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 532 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 533 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 534 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 535 case PPCISD::CR6SET: return "PPCISD::CR6SET"; 536 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET"; 537 } 538} 539 540EVT PPCTargetLowering::getSetCCResultType(EVT VT) const { 541 return MVT::i32; 542} 543 544//===----------------------------------------------------------------------===// 545// Node matching predicates, for use by the tblgen matching code. 546//===----------------------------------------------------------------------===// 547 548/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 549static bool isFloatingPointZero(SDValue Op) { 550 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 551 return CFP->getValueAPF().isZero(); 552 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 553 // Maybe this has already been legalized into the constant pool? 554 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 555 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 556 return CFP->getValueAPF().isZero(); 557 } 558 return false; 559} 560 561/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 562/// true if Op is undef or if it matches the specified value. 563static bool isConstantOrUndef(int Op, int Val) { 564 return Op < 0 || Op == Val; 565} 566 567/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 568/// VPKUHUM instruction. 569bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 570 if (!isUnary) { 571 for (unsigned i = 0; i != 16; ++i) 572 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 573 return false; 574 } else { 575 for (unsigned i = 0; i != 8; ++i) 576 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 577 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 578 return false; 579 } 580 return true; 581} 582 583/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 584/// VPKUWUM instruction. 585bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 586 if (!isUnary) { 587 for (unsigned i = 0; i != 16; i += 2) 588 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 589 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 590 return false; 591 } else { 592 for (unsigned i = 0; i != 8; i += 2) 593 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 594 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 595 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 596 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 597 return false; 598 } 599 return true; 600} 601 602/// isVMerge - Common function, used to match vmrg* shuffles. 603/// 604static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 605 unsigned LHSStart, unsigned RHSStart) { 606 assert(N->getValueType(0) == MVT::v16i8 && 607 "PPC only supports shuffles by bytes!"); 608 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 609 "Unsupported merge size!"); 610 611 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 612 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 613 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 614 LHSStart+j+i*UnitSize) || 615 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 616 RHSStart+j+i*UnitSize)) 617 return false; 618 } 619 return true; 620} 621 622/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 623/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 624bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 625 bool isUnary) { 626 if (!isUnary) 627 return isVMerge(N, UnitSize, 8, 24); 628 return isVMerge(N, UnitSize, 8, 8); 629} 630 631/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 632/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 633bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 634 bool isUnary) { 635 if (!isUnary) 636 return isVMerge(N, UnitSize, 0, 16); 637 return isVMerge(N, UnitSize, 0, 0); 638} 639 640 641/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 642/// amount, otherwise return -1. 643int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 644 assert(N->getValueType(0) == MVT::v16i8 && 645 "PPC only supports shuffles by bytes!"); 646 647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 648 649 // Find the first non-undef value in the shuffle mask. 650 unsigned i; 651 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 652 /*search*/; 653 654 if (i == 16) return -1; // all undef. 655 656 // Otherwise, check to see if the rest of the elements are consecutively 657 // numbered from this value. 658 unsigned ShiftAmt = SVOp->getMaskElt(i); 659 if (ShiftAmt < i) return -1; 660 ShiftAmt -= i; 661 662 if (!isUnary) { 663 // Check the rest of the elements to see if they are consecutive. 664 for (++i; i != 16; ++i) 665 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 666 return -1; 667 } else { 668 // Check the rest of the elements to see if they are consecutive. 669 for (++i; i != 16; ++i) 670 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 671 return -1; 672 } 673 return ShiftAmt; 674} 675 676/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 677/// specifies a splat of a single element that is suitable for input to 678/// VSPLTB/VSPLTH/VSPLTW. 679bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 680 assert(N->getValueType(0) == MVT::v16i8 && 681 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 682 683 // This is a splat operation if each element of the permute is the same, and 684 // if the value doesn't reference the second vector. 685 unsigned ElementBase = N->getMaskElt(0); 686 687 // FIXME: Handle UNDEF elements too! 688 if (ElementBase >= 16) 689 return false; 690 691 // Check that the indices are consecutive, in the case of a multi-byte element 692 // splatted with a v16i8 mask. 693 for (unsigned i = 1; i != EltSize; ++i) 694 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 695 return false; 696 697 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 698 if (N->getMaskElt(i) < 0) continue; 699 for (unsigned j = 0; j != EltSize; ++j) 700 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 701 return false; 702 } 703 return true; 704} 705 706/// isAllNegativeZeroVector - Returns true if all elements of build_vector 707/// are -0.0. 708bool PPC::isAllNegativeZeroVector(SDNode *N) { 709 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 710 711 APInt APVal, APUndef; 712 unsigned BitSize; 713 bool HasAnyUndefs; 714 715 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 716 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 717 return CFP->getValueAPF().isNegZero(); 718 719 return false; 720} 721 722/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 723/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 724unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 726 assert(isSplatShuffleMask(SVOp, EltSize)); 727 return SVOp->getMaskElt(0) / EltSize; 728} 729 730/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 731/// by using a vspltis[bhw] instruction of the specified element size, return 732/// the constant being splatted. The ByteSize field indicates the number of 733/// bytes of each element [124] -> [bhw]. 734SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 735 SDValue OpVal(0, 0); 736 737 // If ByteSize of the splat is bigger than the element size of the 738 // build_vector, then we have a case where we are checking for a splat where 739 // multiple elements of the buildvector are folded together into a single 740 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 741 unsigned EltSize = 16/N->getNumOperands(); 742 if (EltSize < ByteSize) { 743 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 744 SDValue UniquedVals[4]; 745 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 746 747 // See if all of the elements in the buildvector agree across. 748 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 749 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 750 // If the element isn't a constant, bail fully out. 751 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 752 753 754 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 755 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 756 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 757 return SDValue(); // no match. 758 } 759 760 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 761 // either constant or undef values that are identical for each chunk. See 762 // if these chunks can form into a larger vspltis*. 763 764 // Check to see if all of the leading entries are either 0 or -1. If 765 // neither, then this won't fit into the immediate field. 766 bool LeadingZero = true; 767 bool LeadingOnes = true; 768 for (unsigned i = 0; i != Multiple-1; ++i) { 769 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 770 771 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 772 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 773 } 774 // Finally, check the least significant entry. 775 if (LeadingZero) { 776 if (UniquedVals[Multiple-1].getNode() == 0) 777 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 778 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 779 if (Val < 16) 780 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 781 } 782 if (LeadingOnes) { 783 if (UniquedVals[Multiple-1].getNode() == 0) 784 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 785 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 786 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 787 return DAG.getTargetConstant(Val, MVT::i32); 788 } 789 790 return SDValue(); 791 } 792 793 // Check to see if this buildvec has a single non-undef value in its elements. 794 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 795 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 796 if (OpVal.getNode() == 0) 797 OpVal = N->getOperand(i); 798 else if (OpVal != N->getOperand(i)) 799 return SDValue(); 800 } 801 802 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 803 804 unsigned ValSizeInBytes = EltSize; 805 uint64_t Value = 0; 806 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 807 Value = CN->getZExtValue(); 808 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 809 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 810 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 811 } 812 813 // If the splat value is larger than the element value, then we can never do 814 // this splat. The only case that we could fit the replicated bits into our 815 // immediate field for would be zero, and we prefer to use vxor for it. 816 if (ValSizeInBytes < ByteSize) return SDValue(); 817 818 // If the element value is larger than the splat value, cut it in half and 819 // check to see if the two halves are equal. Continue doing this until we 820 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 821 while (ValSizeInBytes > ByteSize) { 822 ValSizeInBytes >>= 1; 823 824 // If the top half equals the bottom half, we're still ok. 825 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 826 (Value & ((1 << (8*ValSizeInBytes))-1))) 827 return SDValue(); 828 } 829 830 // Properly sign extend the value. 831 int MaskVal = SignExtend32(Value, ByteSize * 8); 832 833 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 834 if (MaskVal == 0) return SDValue(); 835 836 // Finally, if this value fits in a 5 bit sext field, return it 837 if (SignExtend32<5>(MaskVal) == MaskVal) 838 return DAG.getTargetConstant(MaskVal, MVT::i32); 839 return SDValue(); 840} 841 842//===----------------------------------------------------------------------===// 843// Addressing Mode Selection 844//===----------------------------------------------------------------------===// 845 846/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 847/// or 64-bit immediate, and if the value can be accurately represented as a 848/// sign extension from a 16-bit value. If so, this returns true and the 849/// immediate. 850static bool isIntS16Immediate(SDNode *N, short &Imm) { 851 if (N->getOpcode() != ISD::Constant) 852 return false; 853 854 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 855 if (N->getValueType(0) == MVT::i32) 856 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 857 else 858 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 859} 860static bool isIntS16Immediate(SDValue Op, short &Imm) { 861 return isIntS16Immediate(Op.getNode(), Imm); 862} 863 864 865/// SelectAddressRegReg - Given the specified addressed, check to see if it 866/// can be represented as an indexed [r+r] operation. Returns false if it 867/// can be more efficiently represented with [r+imm]. 868bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 869 SDValue &Index, 870 SelectionDAG &DAG) const { 871 short imm = 0; 872 if (N.getOpcode() == ISD::ADD) { 873 if (isIntS16Immediate(N.getOperand(1), imm)) 874 return false; // r+i 875 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 876 return false; // r+i 877 878 Base = N.getOperand(0); 879 Index = N.getOperand(1); 880 return true; 881 } else if (N.getOpcode() == ISD::OR) { 882 if (isIntS16Immediate(N.getOperand(1), imm)) 883 return false; // r+i can fold it if we can. 884 885 // If this is an or of disjoint bitfields, we can codegen this as an add 886 // (for better address arithmetic) if the LHS and RHS of the OR are provably 887 // disjoint. 888 APInt LHSKnownZero, LHSKnownOne; 889 APInt RHSKnownZero, RHSKnownOne; 890 DAG.ComputeMaskedBits(N.getOperand(0), 891 LHSKnownZero, LHSKnownOne); 892 893 if (LHSKnownZero.getBoolValue()) { 894 DAG.ComputeMaskedBits(N.getOperand(1), 895 RHSKnownZero, RHSKnownOne); 896 // If all of the bits are known zero on the LHS or RHS, the add won't 897 // carry. 898 if (~(LHSKnownZero | RHSKnownZero) == 0) { 899 Base = N.getOperand(0); 900 Index = N.getOperand(1); 901 return true; 902 } 903 } 904 } 905 906 return false; 907} 908 909/// Returns true if the address N can be represented by a base register plus 910/// a signed 16-bit displacement [r+imm], and if it is not better 911/// represented as reg+reg. 912bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 913 SDValue &Base, 914 SelectionDAG &DAG) const { 915 // FIXME dl should come from parent load or store, not from address 916 DebugLoc dl = N.getDebugLoc(); 917 // If this can be more profitably realized as r+r, fail. 918 if (SelectAddressRegReg(N, Disp, Base, DAG)) 919 return false; 920 921 if (N.getOpcode() == ISD::ADD) { 922 short imm = 0; 923 if (isIntS16Immediate(N.getOperand(1), imm)) { 924 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 925 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 926 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 927 } else { 928 Base = N.getOperand(0); 929 } 930 return true; // [r+i] 931 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 932 // Match LOAD (ADD (X, Lo(G))). 933 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 934 && "Cannot handle constant offsets yet!"); 935 Disp = N.getOperand(1).getOperand(0); // The global address. 936 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 937 Disp.getOpcode() == ISD::TargetGlobalTLSAddress || 938 Disp.getOpcode() == ISD::TargetConstantPool || 939 Disp.getOpcode() == ISD::TargetJumpTable); 940 Base = N.getOperand(0); 941 return true; // [&g+r] 942 } 943 } else if (N.getOpcode() == ISD::OR) { 944 short imm = 0; 945 if (isIntS16Immediate(N.getOperand(1), imm)) { 946 // If this is an or of disjoint bitfields, we can codegen this as an add 947 // (for better address arithmetic) if the LHS and RHS of the OR are 948 // provably disjoint. 949 APInt LHSKnownZero, LHSKnownOne; 950 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 951 952 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 953 // If all of the bits are known zero on the LHS or RHS, the add won't 954 // carry. 955 Base = N.getOperand(0); 956 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 957 return true; 958 } 959 } 960 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 961 // Loading from a constant address. 962 963 // If this address fits entirely in a 16-bit sext immediate field, codegen 964 // this as "d, 0" 965 short Imm; 966 if (isIntS16Immediate(CN, Imm)) { 967 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 968 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 969 CN->getValueType(0)); 970 return true; 971 } 972 973 // Handle 32-bit sext immediates with LIS + addr mode. 974 if (CN->getValueType(0) == MVT::i32 || 975 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 976 int Addr = (int)CN->getZExtValue(); 977 978 // Otherwise, break this down into an LIS + disp. 979 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 980 981 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 982 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 983 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 984 return true; 985 } 986 } 987 988 Disp = DAG.getTargetConstant(0, getPointerTy()); 989 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 990 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 991 else 992 Base = N; 993 return true; // [r+0] 994} 995 996/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 997/// represented as an indexed [r+r] operation. 998bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 999 SDValue &Index, 1000 SelectionDAG &DAG) const { 1001 // Check to see if we can easily represent this as an [r+r] address. This 1002 // will fail if it thinks that the address is more profitably represented as 1003 // reg+imm, e.g. where imm = 0. 1004 if (SelectAddressRegReg(N, Base, Index, DAG)) 1005 return true; 1006 1007 // If the operand is an addition, always emit this as [r+r], since this is 1008 // better (for code size, and execution, as the memop does the add for free) 1009 // than emitting an explicit add. 1010 if (N.getOpcode() == ISD::ADD) { 1011 Base = N.getOperand(0); 1012 Index = N.getOperand(1); 1013 return true; 1014 } 1015 1016 // Otherwise, do it the hard way, using R0 as the base register. 1017 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1018 N.getValueType()); 1019 Index = N; 1020 return true; 1021} 1022 1023/// SelectAddressRegImmShift - Returns true if the address N can be 1024/// represented by a base register plus a signed 14-bit displacement 1025/// [r+imm*4]. Suitable for use by STD and friends. 1026bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 1027 SDValue &Base, 1028 SelectionDAG &DAG) const { 1029 // FIXME dl should come from the parent load or store, not the address 1030 DebugLoc dl = N.getDebugLoc(); 1031 // If this can be more profitably realized as r+r, fail. 1032 if (SelectAddressRegReg(N, Disp, Base, DAG)) 1033 return false; 1034 1035 if (N.getOpcode() == ISD::ADD) { 1036 short imm = 0; 1037 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1038 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1039 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 1040 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1041 } else { 1042 Base = N.getOperand(0); 1043 } 1044 return true; // [r+i] 1045 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 1046 // Match LOAD (ADD (X, Lo(G))). 1047 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 1048 && "Cannot handle constant offsets yet!"); 1049 Disp = N.getOperand(1).getOperand(0); // The global address. 1050 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 1051 Disp.getOpcode() == ISD::TargetConstantPool || 1052 Disp.getOpcode() == ISD::TargetJumpTable); 1053 Base = N.getOperand(0); 1054 return true; // [&g+r] 1055 } 1056 } else if (N.getOpcode() == ISD::OR) { 1057 short imm = 0; 1058 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1059 // If this is an or of disjoint bitfields, we can codegen this as an add 1060 // (for better address arithmetic) if the LHS and RHS of the OR are 1061 // provably disjoint. 1062 APInt LHSKnownZero, LHSKnownOne; 1063 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1064 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1065 // If all of the bits are known zero on the LHS or RHS, the add won't 1066 // carry. 1067 Base = N.getOperand(0); 1068 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1069 return true; 1070 } 1071 } 1072 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1073 // Loading from a constant address. Verify low two bits are clear. 1074 if ((CN->getZExtValue() & 3) == 0) { 1075 // If this address fits entirely in a 14-bit sext immediate field, codegen 1076 // this as "d, 0" 1077 short Imm; 1078 if (isIntS16Immediate(CN, Imm)) { 1079 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1080 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1081 CN->getValueType(0)); 1082 return true; 1083 } 1084 1085 // Fold the low-part of 32-bit absolute addresses into addr mode. 1086 if (CN->getValueType(0) == MVT::i32 || 1087 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1088 int Addr = (int)CN->getZExtValue(); 1089 1090 // Otherwise, break this down into an LIS + disp. 1091 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1092 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1093 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1094 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1095 return true; 1096 } 1097 } 1098 } 1099 1100 Disp = DAG.getTargetConstant(0, getPointerTy()); 1101 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1102 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1103 else 1104 Base = N; 1105 return true; // [r+0] 1106} 1107 1108 1109/// getPreIndexedAddressParts - returns true by value, base pointer and 1110/// offset pointer and addressing mode by reference if the node's address 1111/// can be legally represented as pre-indexed load / store address. 1112bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1113 SDValue &Offset, 1114 ISD::MemIndexedMode &AM, 1115 SelectionDAG &DAG) const { 1116 if (DisablePPCPreinc) return false; 1117 1118 SDValue Ptr; 1119 EVT VT; 1120 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1121 Ptr = LD->getBasePtr(); 1122 VT = LD->getMemoryVT(); 1123 1124 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1125 Ptr = ST->getBasePtr(); 1126 VT = ST->getMemoryVT(); 1127 } else 1128 return false; 1129 1130 // PowerPC doesn't have preinc load/store instructions for vectors. 1131 if (VT.isVector()) 1132 return false; 1133 1134 if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) { 1135 AM = ISD::PRE_INC; 1136 return true; 1137 } 1138 1139 // LDU/STU use reg+imm*4, others use reg+imm. 1140 if (VT != MVT::i64) { 1141 // reg + imm 1142 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1143 return false; 1144 } else { 1145 // reg + imm * 4. 1146 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1147 return false; 1148 } 1149 1150 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1151 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1152 // sext i32 to i64 when addr mode is r+i. 1153 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1154 LD->getExtensionType() == ISD::SEXTLOAD && 1155 isa<ConstantSDNode>(Offset)) 1156 return false; 1157 } 1158 1159 AM = ISD::PRE_INC; 1160 return true; 1161} 1162 1163//===----------------------------------------------------------------------===// 1164// LowerOperation implementation 1165//===----------------------------------------------------------------------===// 1166 1167/// GetLabelAccessInfo - Return true if we should reference labels using a 1168/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1169static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1170 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1171 HiOpFlags = PPCII::MO_HA16; 1172 LoOpFlags = PPCII::MO_LO16; 1173 1174 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1175 // non-darwin platform. We don't support PIC on other platforms yet. 1176 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1177 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1178 if (isPIC) { 1179 HiOpFlags |= PPCII::MO_PIC_FLAG; 1180 LoOpFlags |= PPCII::MO_PIC_FLAG; 1181 } 1182 1183 // If this is a reference to a global value that requires a non-lazy-ptr, make 1184 // sure that instruction lowering adds it. 1185 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1186 HiOpFlags |= PPCII::MO_NLP_FLAG; 1187 LoOpFlags |= PPCII::MO_NLP_FLAG; 1188 1189 if (GV->hasHiddenVisibility()) { 1190 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1191 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1192 } 1193 } 1194 1195 return isPIC; 1196} 1197 1198static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1199 SelectionDAG &DAG) { 1200 EVT PtrVT = HiPart.getValueType(); 1201 SDValue Zero = DAG.getConstant(0, PtrVT); 1202 DebugLoc DL = HiPart.getDebugLoc(); 1203 1204 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1205 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1206 1207 // With PIC, the first instruction is actually "GR+hi(&G)". 1208 if (isPIC) 1209 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1210 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1211 1212 // Generate non-pic code that has direct accesses to the constant pool. 1213 // The address of the global is just (hi(&g)+lo(&g)). 1214 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1215} 1216 1217SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1218 SelectionDAG &DAG) const { 1219 EVT PtrVT = Op.getValueType(); 1220 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1221 const Constant *C = CP->getConstVal(); 1222 1223 // 64-bit SVR4 ABI code is always position-independent. 1224 // The actual address of the GlobalValue is stored in the TOC. 1225 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1226 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0); 1227 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA, 1228 DAG.getRegister(PPC::X2, MVT::i64)); 1229 } 1230 1231 unsigned MOHiFlag, MOLoFlag; 1232 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1233 SDValue CPIHi = 1234 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1235 SDValue CPILo = 1236 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1237 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1238} 1239 1240SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1241 EVT PtrVT = Op.getValueType(); 1242 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1243 1244 // 64-bit SVR4 ABI code is always position-independent. 1245 // The actual address of the GlobalValue is stored in the TOC. 1246 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1247 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1248 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA, 1249 DAG.getRegister(PPC::X2, MVT::i64)); 1250 } 1251 1252 unsigned MOHiFlag, MOLoFlag; 1253 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1254 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1255 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1256 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1257} 1258 1259SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1260 SelectionDAG &DAG) const { 1261 EVT PtrVT = Op.getValueType(); 1262 1263 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1264 1265 unsigned MOHiFlag, MOLoFlag; 1266 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1267 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag); 1268 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag); 1269 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1270} 1271 1272SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1273 SelectionDAG &DAG) const { 1274 1275 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1276 DebugLoc dl = GA->getDebugLoc(); 1277 const GlobalValue *GV = GA->getGlobal(); 1278 EVT PtrVT = getPointerTy(); 1279 bool is64bit = PPCSubTarget.isPPC64(); 1280 1281 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1282 1283 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1284 PPCII::MO_TPREL16_HA); 1285 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1286 PPCII::MO_TPREL16_LO); 1287 1288 if (model != TLSModel::LocalExec) 1289 llvm_unreachable("only local-exec TLS mode supported"); 1290 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2, 1291 is64bit ? MVT::i64 : MVT::i32); 1292 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg); 1293 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi); 1294} 1295 1296SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1297 SelectionDAG &DAG) const { 1298 EVT PtrVT = Op.getValueType(); 1299 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1300 DebugLoc DL = GSDN->getDebugLoc(); 1301 const GlobalValue *GV = GSDN->getGlobal(); 1302 1303 // 64-bit SVR4 ABI code is always position-independent. 1304 // The actual address of the GlobalValue is stored in the TOC. 1305 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1306 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1307 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1308 DAG.getRegister(PPC::X2, MVT::i64)); 1309 } 1310 1311 unsigned MOHiFlag, MOLoFlag; 1312 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1313 1314 SDValue GAHi = 1315 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1316 SDValue GALo = 1317 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1318 1319 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1320 1321 // If the global reference is actually to a non-lazy-pointer, we have to do an 1322 // extra load to get the address of the global. 1323 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1324 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1325 false, false, false, 0); 1326 return Ptr; 1327} 1328 1329SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1330 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1331 DebugLoc dl = Op.getDebugLoc(); 1332 1333 // If we're comparing for equality to zero, expose the fact that this is 1334 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1335 // fold the new nodes. 1336 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1337 if (C->isNullValue() && CC == ISD::SETEQ) { 1338 EVT VT = Op.getOperand(0).getValueType(); 1339 SDValue Zext = Op.getOperand(0); 1340 if (VT.bitsLT(MVT::i32)) { 1341 VT = MVT::i32; 1342 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1343 } 1344 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1345 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1346 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1347 DAG.getConstant(Log2b, MVT::i32)); 1348 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1349 } 1350 // Leave comparisons against 0 and -1 alone for now, since they're usually 1351 // optimized. FIXME: revisit this when we can custom lower all setcc 1352 // optimizations. 1353 if (C->isAllOnesValue() || C->isNullValue()) 1354 return SDValue(); 1355 } 1356 1357 // If we have an integer seteq/setne, turn it into a compare against zero 1358 // by xor'ing the rhs with the lhs, which is faster than setting a 1359 // condition register, reading it back out, and masking the correct bit. The 1360 // normal approach here uses sub to do this instead of xor. Using xor exposes 1361 // the result to other bit-twiddling opportunities. 1362 EVT LHSVT = Op.getOperand(0).getValueType(); 1363 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1364 EVT VT = Op.getValueType(); 1365 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1366 Op.getOperand(1)); 1367 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1368 } 1369 return SDValue(); 1370} 1371 1372SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1373 const PPCSubtarget &Subtarget) const { 1374 SDNode *Node = Op.getNode(); 1375 EVT VT = Node->getValueType(0); 1376 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1377 SDValue InChain = Node->getOperand(0); 1378 SDValue VAListPtr = Node->getOperand(1); 1379 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1380 DebugLoc dl = Node->getDebugLoc(); 1381 1382 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); 1383 1384 // gpr_index 1385 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1386 VAListPtr, MachinePointerInfo(SV), MVT::i8, 1387 false, false, 0); 1388 InChain = GprIndex.getValue(1); 1389 1390 if (VT == MVT::i64) { 1391 // Check if GprIndex is even 1392 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, 1393 DAG.getConstant(1, MVT::i32)); 1394 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, 1395 DAG.getConstant(0, MVT::i32), ISD::SETNE); 1396 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, 1397 DAG.getConstant(1, MVT::i32)); 1398 // Align GprIndex to be even if it isn't 1399 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, 1400 GprIndex); 1401 } 1402 1403 // fpr index is 1 byte after gpr 1404 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1405 DAG.getConstant(1, MVT::i32)); 1406 1407 // fpr 1408 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1409 FprPtr, MachinePointerInfo(SV), MVT::i8, 1410 false, false, 0); 1411 InChain = FprIndex.getValue(1); 1412 1413 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1414 DAG.getConstant(8, MVT::i32)); 1415 1416 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1417 DAG.getConstant(4, MVT::i32)); 1418 1419 // areas 1420 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, 1421 MachinePointerInfo(), false, false, 1422 false, 0); 1423 InChain = OverflowArea.getValue(1); 1424 1425 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, 1426 MachinePointerInfo(), false, false, 1427 false, 0); 1428 InChain = RegSaveArea.getValue(1); 1429 1430 // select overflow_area if index > 8 1431 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, 1432 DAG.getConstant(8, MVT::i32), ISD::SETLT); 1433 1434 // adjustment constant gpr_index * 4/8 1435 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 1436 VT.isInteger() ? GprIndex : FprIndex, 1437 DAG.getConstant(VT.isInteger() ? 4 : 8, 1438 MVT::i32)); 1439 1440 // OurReg = RegSaveArea + RegConstant 1441 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, 1442 RegConstant); 1443 1444 // Floating types are 32 bytes into RegSaveArea 1445 if (VT.isFloatingPoint()) 1446 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, 1447 DAG.getConstant(32, MVT::i32)); 1448 1449 // increase {f,g}pr_index by 1 (or 2 if VT is i64) 1450 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, 1451 VT.isInteger() ? GprIndex : FprIndex, 1452 DAG.getConstant(VT == MVT::i64 ? 2 : 1, 1453 MVT::i32)); 1454 1455 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, 1456 VT.isInteger() ? VAListPtr : FprPtr, 1457 MachinePointerInfo(SV), 1458 MVT::i8, false, false, 0); 1459 1460 // determine if we should load from reg_save_area or overflow_area 1461 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); 1462 1463 // increase overflow_area by 4/8 if gpr/fpr > 8 1464 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, 1465 DAG.getConstant(VT.isInteger() ? 4 : 8, 1466 MVT::i32)); 1467 1468 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, 1469 OverflowAreaPlusN); 1470 1471 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, 1472 OverflowAreaPtr, 1473 MachinePointerInfo(), 1474 MVT::i32, false, false, 0); 1475 1476 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), 1477 false, false, false, 0); 1478} 1479 1480SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 1481 SelectionDAG &DAG) const { 1482 return Op.getOperand(0); 1483} 1484 1485SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 1486 SelectionDAG &DAG) const { 1487 SDValue Chain = Op.getOperand(0); 1488 SDValue Trmp = Op.getOperand(1); // trampoline 1489 SDValue FPtr = Op.getOperand(2); // nested function 1490 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1491 DebugLoc dl = Op.getDebugLoc(); 1492 1493 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1494 bool isPPC64 = (PtrVT == MVT::i64); 1495 Type *IntPtrTy = 1496 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1497 *DAG.getContext()); 1498 1499 TargetLowering::ArgListTy Args; 1500 TargetLowering::ArgListEntry Entry; 1501 1502 Entry.Ty = IntPtrTy; 1503 Entry.Node = Trmp; Args.push_back(Entry); 1504 1505 // TrampSize == (isPPC64 ? 48 : 40); 1506 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1507 isPPC64 ? MVT::i64 : MVT::i32); 1508 Args.push_back(Entry); 1509 1510 Entry.Node = FPtr; Args.push_back(Entry); 1511 Entry.Node = Nest; Args.push_back(Entry); 1512 1513 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1514 TargetLowering::CallLoweringInfo CLI(Chain, 1515 Type::getVoidTy(*DAG.getContext()), 1516 false, false, false, false, 0, 1517 CallingConv::C, 1518 /*isTailCall=*/false, 1519 /*doesNotRet=*/false, 1520 /*isReturnValueUsed=*/true, 1521 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1522 Args, DAG, dl); 1523 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1524 1525 return CallResult.second; 1526} 1527 1528SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1529 const PPCSubtarget &Subtarget) const { 1530 MachineFunction &MF = DAG.getMachineFunction(); 1531 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1532 1533 DebugLoc dl = Op.getDebugLoc(); 1534 1535 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1536 // vastart just stores the address of the VarArgsFrameIndex slot into the 1537 // memory location argument. 1538 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1539 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1540 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1541 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1542 MachinePointerInfo(SV), 1543 false, false, 0); 1544 } 1545 1546 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1547 // We suppose the given va_list is already allocated. 1548 // 1549 // typedef struct { 1550 // char gpr; /* index into the array of 8 GPRs 1551 // * stored in the register save area 1552 // * gpr=0 corresponds to r3, 1553 // * gpr=1 to r4, etc. 1554 // */ 1555 // char fpr; /* index into the array of 8 FPRs 1556 // * stored in the register save area 1557 // * fpr=0 corresponds to f1, 1558 // * fpr=1 to f2, etc. 1559 // */ 1560 // char *overflow_arg_area; 1561 // /* location on stack that holds 1562 // * the next overflow argument 1563 // */ 1564 // char *reg_save_area; 1565 // /* where r3:r10 and f1:f8 (if saved) 1566 // * are stored 1567 // */ 1568 // } va_list[1]; 1569 1570 1571 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1572 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1573 1574 1575 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1576 1577 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1578 PtrVT); 1579 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1580 PtrVT); 1581 1582 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1583 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1584 1585 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1586 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1587 1588 uint64_t FPROffset = 1; 1589 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1590 1591 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1592 1593 // Store first byte : number of int regs 1594 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1595 Op.getOperand(1), 1596 MachinePointerInfo(SV), 1597 MVT::i8, false, false, 0); 1598 uint64_t nextOffset = FPROffset; 1599 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1600 ConstFPROffset); 1601 1602 // Store second byte : number of float regs 1603 SDValue secondStore = 1604 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1605 MachinePointerInfo(SV, nextOffset), MVT::i8, 1606 false, false, 0); 1607 nextOffset += StackOffset; 1608 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1609 1610 // Store second word : arguments given on stack 1611 SDValue thirdStore = 1612 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1613 MachinePointerInfo(SV, nextOffset), 1614 false, false, 0); 1615 nextOffset += FrameOffset; 1616 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1617 1618 // Store third word : arguments given in registers 1619 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1620 MachinePointerInfo(SV, nextOffset), 1621 false, false, 0); 1622 1623} 1624 1625#include "PPCGenCallingConv.inc" 1626 1627static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1628 CCValAssign::LocInfo &LocInfo, 1629 ISD::ArgFlagsTy &ArgFlags, 1630 CCState &State) { 1631 return true; 1632} 1633 1634static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1635 MVT &LocVT, 1636 CCValAssign::LocInfo &LocInfo, 1637 ISD::ArgFlagsTy &ArgFlags, 1638 CCState &State) { 1639 static const uint16_t ArgRegs[] = { 1640 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1641 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1642 }; 1643 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1644 1645 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1646 1647 // Skip one register if the first unallocated register has an even register 1648 // number and there are still argument registers available which have not been 1649 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1650 // need to skip a register if RegNum is odd. 1651 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1652 State.AllocateReg(ArgRegs[RegNum]); 1653 } 1654 1655 // Always return false here, as this function only makes sure that the first 1656 // unallocated register has an odd register number and does not actually 1657 // allocate a register for the current argument. 1658 return false; 1659} 1660 1661static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1662 MVT &LocVT, 1663 CCValAssign::LocInfo &LocInfo, 1664 ISD::ArgFlagsTy &ArgFlags, 1665 CCState &State) { 1666 static const uint16_t ArgRegs[] = { 1667 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1668 PPC::F8 1669 }; 1670 1671 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1672 1673 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1674 1675 // If there is only one Floating-point register left we need to put both f64 1676 // values of a split ppc_fp128 value on the stack. 1677 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1678 State.AllocateReg(ArgRegs[RegNum]); 1679 } 1680 1681 // Always return false here, as this function only makes sure that the two f64 1682 // values a ppc_fp128 value is split into are both passed in registers or both 1683 // passed on the stack and does not actually allocate a register for the 1684 // current argument. 1685 return false; 1686} 1687 1688/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1689/// on Darwin. 1690static const uint16_t *GetFPR() { 1691 static const uint16_t FPR[] = { 1692 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1693 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1694 }; 1695 1696 return FPR; 1697} 1698 1699/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1700/// the stack. 1701static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1702 unsigned PtrByteSize) { 1703 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1704 if (Flags.isByVal()) 1705 ArgSize = Flags.getByValSize(); 1706 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1707 1708 return ArgSize; 1709} 1710 1711SDValue 1712PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1713 CallingConv::ID CallConv, bool isVarArg, 1714 const SmallVectorImpl<ISD::InputArg> 1715 &Ins, 1716 DebugLoc dl, SelectionDAG &DAG, 1717 SmallVectorImpl<SDValue> &InVals) 1718 const { 1719 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1720 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, 1721 dl, DAG, InVals); 1722 } else { 1723 return LowerFormalArguments_Darwin_Or_64SVR4(Chain, CallConv, isVarArg, Ins, 1724 dl, DAG, InVals); 1725 } 1726} 1727 1728SDValue 1729PPCTargetLowering::LowerFormalArguments_32SVR4( 1730 SDValue Chain, 1731 CallingConv::ID CallConv, bool isVarArg, 1732 const SmallVectorImpl<ISD::InputArg> 1733 &Ins, 1734 DebugLoc dl, SelectionDAG &DAG, 1735 SmallVectorImpl<SDValue> &InVals) const { 1736 1737 // 32-bit SVR4 ABI Stack Frame Layout: 1738 // +-----------------------------------+ 1739 // +--> | Back chain | 1740 // | +-----------------------------------+ 1741 // | | Floating-point register save area | 1742 // | +-----------------------------------+ 1743 // | | General register save area | 1744 // | +-----------------------------------+ 1745 // | | CR save word | 1746 // | +-----------------------------------+ 1747 // | | VRSAVE save word | 1748 // | +-----------------------------------+ 1749 // | | Alignment padding | 1750 // | +-----------------------------------+ 1751 // | | Vector register save area | 1752 // | +-----------------------------------+ 1753 // | | Local variable space | 1754 // | +-----------------------------------+ 1755 // | | Parameter list area | 1756 // | +-----------------------------------+ 1757 // | | LR save word | 1758 // | +-----------------------------------+ 1759 // SP--> +--- | Back chain | 1760 // +-----------------------------------+ 1761 // 1762 // Specifications: 1763 // System V Application Binary Interface PowerPC Processor Supplement 1764 // AltiVec Technology Programming Interface Manual 1765 1766 MachineFunction &MF = DAG.getMachineFunction(); 1767 MachineFrameInfo *MFI = MF.getFrameInfo(); 1768 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1769 1770 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1771 // Potential tail calls could cause overwriting of argument stack slots. 1772 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 1773 (CallConv == CallingConv::Fast)); 1774 unsigned PtrByteSize = 4; 1775 1776 // Assign locations to all of the incoming arguments. 1777 SmallVector<CCValAssign, 16> ArgLocs; 1778 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1779 getTargetMachine(), ArgLocs, *DAG.getContext()); 1780 1781 // Reserve space for the linkage area on the stack. 1782 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1783 1784 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1785 1786 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1787 CCValAssign &VA = ArgLocs[i]; 1788 1789 // Arguments stored in registers. 1790 if (VA.isRegLoc()) { 1791 const TargetRegisterClass *RC; 1792 EVT ValVT = VA.getValVT(); 1793 1794 switch (ValVT.getSimpleVT().SimpleTy) { 1795 default: 1796 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1797 case MVT::i32: 1798 RC = &PPC::GPRCRegClass; 1799 break; 1800 case MVT::f32: 1801 RC = &PPC::F4RCRegClass; 1802 break; 1803 case MVT::f64: 1804 RC = &PPC::F8RCRegClass; 1805 break; 1806 case MVT::v16i8: 1807 case MVT::v8i16: 1808 case MVT::v4i32: 1809 case MVT::v4f32: 1810 RC = &PPC::VRRCRegClass; 1811 break; 1812 } 1813 1814 // Transform the arguments stored in physical registers into virtual ones. 1815 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1816 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1817 1818 InVals.push_back(ArgValue); 1819 } else { 1820 // Argument stored in memory. 1821 assert(VA.isMemLoc()); 1822 1823 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1824 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1825 isImmutable); 1826 1827 // Create load nodes to retrieve arguments from the stack. 1828 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1829 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1830 MachinePointerInfo(), 1831 false, false, false, 0)); 1832 } 1833 } 1834 1835 // Assign locations to all of the incoming aggregate by value arguments. 1836 // Aggregates passed by value are stored in the local variable space of the 1837 // caller's stack frame, right above the parameter list area. 1838 SmallVector<CCValAssign, 16> ByValArgLocs; 1839 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1840 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 1841 1842 // Reserve stack space for the allocations in CCInfo. 1843 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1844 1845 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1846 1847 // Area that is at least reserved in the caller of this function. 1848 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1849 1850 // Set the size that is at least reserved in caller of this function. Tail 1851 // call optimized function's reserved stack space needs to be aligned so that 1852 // taking the difference between two stack areas will result in an aligned 1853 // stack. 1854 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1855 1856 MinReservedArea = 1857 std::max(MinReservedArea, 1858 PPCFrameLowering::getMinCallFrameSize(false, false)); 1859 1860 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 1861 getStackAlignment(); 1862 unsigned AlignMask = TargetAlign-1; 1863 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1864 1865 FI->setMinReservedArea(MinReservedArea); 1866 1867 SmallVector<SDValue, 8> MemOps; 1868 1869 // If the function takes variable number of arguments, make a frame index for 1870 // the start of the first vararg value... for expansion of llvm.va_start. 1871 if (isVarArg) { 1872 static const uint16_t GPArgRegs[] = { 1873 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1874 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1875 }; 1876 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1877 1878 static const uint16_t FPArgRegs[] = { 1879 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1880 PPC::F8 1881 }; 1882 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1883 1884 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 1885 NumGPArgRegs)); 1886 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 1887 NumFPArgRegs)); 1888 1889 // Make room for NumGPArgRegs and NumFPArgRegs. 1890 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1891 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1892 1893 FuncInfo->setVarArgsStackOffset( 1894 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1895 CCInfo.getNextStackOffset(), true)); 1896 1897 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 1898 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1899 1900 // The fixed integer arguments of a variadic function are stored to the 1901 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 1902 // the result of va_next. 1903 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1904 // Get an existing live-in vreg, or add a new one. 1905 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 1906 if (!VReg) 1907 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1908 1909 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1910 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1911 MachinePointerInfo(), false, false, 0); 1912 MemOps.push_back(Store); 1913 // Increment the address by four for the next argument to store 1914 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1915 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1916 } 1917 1918 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1919 // is set. 1920 // The double arguments are stored to the VarArgsFrameIndex 1921 // on the stack. 1922 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1923 // Get an existing live-in vreg, or add a new one. 1924 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 1925 if (!VReg) 1926 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1927 1928 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1929 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1930 MachinePointerInfo(), false, false, 0); 1931 MemOps.push_back(Store); 1932 // Increment the address by eight for the next argument to store 1933 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1934 PtrVT); 1935 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1936 } 1937 } 1938 1939 if (!MemOps.empty()) 1940 Chain = DAG.getNode(ISD::TokenFactor, dl, 1941 MVT::Other, &MemOps[0], MemOps.size()); 1942 1943 return Chain; 1944} 1945 1946SDValue 1947PPCTargetLowering::LowerFormalArguments_Darwin_Or_64SVR4( 1948 SDValue Chain, 1949 CallingConv::ID CallConv, bool isVarArg, 1950 const SmallVectorImpl<ISD::InputArg> 1951 &Ins, 1952 DebugLoc dl, SelectionDAG &DAG, 1953 SmallVectorImpl<SDValue> &InVals) const { 1954 // TODO: add description of PPC stack frame format, or at least some docs. 1955 // 1956 MachineFunction &MF = DAG.getMachineFunction(); 1957 MachineFrameInfo *MFI = MF.getFrameInfo(); 1958 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1959 1960 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1961 bool isPPC64 = PtrVT == MVT::i64; 1962 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 1963 // Potential tail calls could cause overwriting of argument stack slots. 1964 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 1965 (CallConv == CallingConv::Fast)); 1966 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1967 1968 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 1969 // Area that is at least reserved in caller of this function. 1970 unsigned MinReservedArea = ArgOffset; 1971 1972 static const uint16_t GPR_32[] = { // 32-bit registers. 1973 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1974 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1975 }; 1976 static const uint16_t GPR_64[] = { // 64-bit registers. 1977 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1978 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1979 }; 1980 1981 static const uint16_t *FPR = GetFPR(); 1982 1983 static const uint16_t VR[] = { 1984 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1985 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1986 }; 1987 1988 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1989 const unsigned Num_FPR_Regs = 13; 1990 const unsigned Num_VR_Regs = array_lengthof( VR); 1991 1992 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1993 1994 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 1995 1996 // In 32-bit non-varargs functions, the stack space for vectors is after the 1997 // stack space for non-vectors. We do not use this space unless we have 1998 // too many vectors to fit in registers, something that only occurs in 1999 // constructed examples:), but we have to walk the arglist to figure 2000 // that out...for the pathological case, compute VecArgOffset as the 2001 // start of the vector parameter area. Computing VecArgOffset is the 2002 // entire point of the following loop. 2003 unsigned VecArgOffset = ArgOffset; 2004 if (!isVarArg && !isPPC64) { 2005 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 2006 ++ArgNo) { 2007 EVT ObjectVT = Ins[ArgNo].VT; 2008 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2009 2010 if (Flags.isByVal()) { 2011 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 2012 unsigned ObjSize = Flags.getByValSize(); 2013 unsigned ArgSize = 2014 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2015 VecArgOffset += ArgSize; 2016 continue; 2017 } 2018 2019 switch(ObjectVT.getSimpleVT().SimpleTy) { 2020 default: llvm_unreachable("Unhandled argument type!"); 2021 case MVT::i32: 2022 case MVT::f32: 2023 VecArgOffset += 4; 2024 break; 2025 case MVT::i64: // PPC64 2026 case MVT::f64: 2027 // FIXME: We are guaranteed to be !isPPC64 at this point. 2028 // Does MVT::i64 apply? 2029 VecArgOffset += 8; 2030 break; 2031 case MVT::v4f32: 2032 case MVT::v4i32: 2033 case MVT::v8i16: 2034 case MVT::v16i8: 2035 // Nothing to do, we're only looking at Nonvector args here. 2036 break; 2037 } 2038 } 2039 } 2040 // We've found where the vector parameter area in memory is. Skip the 2041 // first 12 parameters; these don't use that memory. 2042 VecArgOffset = ((VecArgOffset+15)/16)*16; 2043 VecArgOffset += 12*16; 2044 2045 // Add DAG nodes to load the arguments or copy them out of registers. On 2046 // entry to a function on PPC, the arguments start after the linkage area, 2047 // although the first ones are often in registers. 2048 2049 SmallVector<SDValue, 8> MemOps; 2050 unsigned nAltivecParamsAtEnd = 0; 2051 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2052 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) { 2053 SDValue ArgVal; 2054 bool needsLoad = false; 2055 EVT ObjectVT = Ins[ArgNo].VT; 2056 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2057 unsigned ArgSize = ObjSize; 2058 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2059 2060 unsigned CurArgOffset = ArgOffset; 2061 2062 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2063 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2064 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2065 if (isVarArg || isPPC64) { 2066 MinReservedArea = ((MinReservedArea+15)/16)*16; 2067 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2068 Flags, 2069 PtrByteSize); 2070 } else nAltivecParamsAtEnd++; 2071 } else 2072 // Calculate min reserved area. 2073 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2074 Flags, 2075 PtrByteSize); 2076 2077 // FIXME the codegen can be much improved in some cases. 2078 // We do not have to keep everything in memory. 2079 if (Flags.isByVal()) { 2080 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2081 ObjSize = Flags.getByValSize(); 2082 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2083 // FOR DARWIN: Objects of size 1 and 2 are right justified, everything 2084 // else is left justified. This means the memory address is adjusted 2085 // forwards. 2086 // FOR 64-BIT SVR4: All aggregates smaller than 8 bytes must be passed 2087 // right-justified. 2088 if (ObjSize==1 || ObjSize==2) { 2089 CurArgOffset = CurArgOffset + (4 - ObjSize); 2090 } 2091 // The value of the object is its address. 2092 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2093 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2094 InVals.push_back(FIN); 2095 if (ObjSize==1 || ObjSize==2 || 2096 (ObjSize==4 && isSVR4ABI)) { 2097 if (GPR_idx != Num_GPR_Regs) { 2098 unsigned VReg; 2099 if (isPPC64) 2100 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2101 else 2102 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2103 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2104 EVT ObjType = (ObjSize == 1 ? MVT::i8 : 2105 (ObjSize == 2 ? MVT::i16 : MVT::i32)); 2106 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2107 MachinePointerInfo(FuncArg, 2108 CurArgOffset), 2109 ObjType, false, false, 0); 2110 MemOps.push_back(Store); 2111 ++GPR_idx; 2112 } 2113 2114 ArgOffset += PtrByteSize; 2115 2116 continue; 2117 } 2118 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2119 // Store whatever pieces of the object are in registers 2120 // to memory. ArgOffset will be the address of the beginning 2121 // of the object. 2122 if (GPR_idx != Num_GPR_Regs) { 2123 unsigned VReg; 2124 if (isPPC64) 2125 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2126 else 2127 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2128 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2129 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2130 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2131 SDValue Shifted = Val; 2132 2133 // For 64-bit SVR4, small structs come in right-adjusted. 2134 // Shift them left so the following logic works as expected. 2135 if (ObjSize < 8 && isSVR4ABI) { 2136 SDValue ShiftAmt = DAG.getConstant(64 - 8 * ObjSize, PtrVT); 2137 Shifted = DAG.getNode(ISD::SHL, dl, PtrVT, Val, ShiftAmt); 2138 } 2139 2140 SDValue Store = DAG.getStore(Val.getValue(1), dl, Shifted, FIN, 2141 MachinePointerInfo(FuncArg, ArgOffset), 2142 false, false, 0); 2143 MemOps.push_back(Store); 2144 ++GPR_idx; 2145 ArgOffset += PtrByteSize; 2146 } else { 2147 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 2148 break; 2149 } 2150 } 2151 continue; 2152 } 2153 2154 switch (ObjectVT.getSimpleVT().SimpleTy) { 2155 default: llvm_unreachable("Unhandled argument type!"); 2156 case MVT::i32: 2157 if (!isPPC64) { 2158 if (GPR_idx != Num_GPR_Regs) { 2159 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2160 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2161 ++GPR_idx; 2162 } else { 2163 needsLoad = true; 2164 ArgSize = PtrByteSize; 2165 } 2166 // All int arguments reserve stack space in the Darwin ABI. 2167 ArgOffset += PtrByteSize; 2168 break; 2169 } 2170 // FALLTHROUGH 2171 case MVT::i64: // PPC64 2172 if (GPR_idx != Num_GPR_Regs) { 2173 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2174 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2175 2176 if (ObjectVT == MVT::i32) { 2177 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2178 // value to MVT::i64 and then truncate to the correct register size. 2179 if (Flags.isSExt()) 2180 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 2181 DAG.getValueType(ObjectVT)); 2182 else if (Flags.isZExt()) 2183 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 2184 DAG.getValueType(ObjectVT)); 2185 2186 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 2187 } 2188 2189 ++GPR_idx; 2190 } else { 2191 needsLoad = true; 2192 ArgSize = PtrByteSize; 2193 } 2194 // All int arguments reserve stack space in the Darwin ABI. 2195 ArgOffset += 8; 2196 break; 2197 2198 case MVT::f32: 2199 case MVT::f64: 2200 // Every 4 bytes of argument space consumes one of the GPRs available for 2201 // argument passing. 2202 if (GPR_idx != Num_GPR_Regs) { 2203 ++GPR_idx; 2204 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2205 ++GPR_idx; 2206 } 2207 if (FPR_idx != Num_FPR_Regs) { 2208 unsigned VReg; 2209 2210 if (ObjectVT == MVT::f32) 2211 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2212 else 2213 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2214 2215 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2216 ++FPR_idx; 2217 } else { 2218 needsLoad = true; 2219 } 2220 2221 // All FP arguments reserve stack space in the Darwin ABI. 2222 ArgOffset += isPPC64 ? 8 : ObjSize; 2223 break; 2224 case MVT::v4f32: 2225 case MVT::v4i32: 2226 case MVT::v8i16: 2227 case MVT::v16i8: 2228 // Note that vector arguments in registers don't reserve stack space, 2229 // except in varargs functions. 2230 if (VR_idx != Num_VR_Regs) { 2231 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2232 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2233 if (isVarArg) { 2234 while ((ArgOffset % 16) != 0) { 2235 ArgOffset += PtrByteSize; 2236 if (GPR_idx != Num_GPR_Regs) 2237 GPR_idx++; 2238 } 2239 ArgOffset += 16; 2240 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2241 } 2242 ++VR_idx; 2243 } else { 2244 if (!isVarArg && !isPPC64) { 2245 // Vectors go after all the nonvectors. 2246 CurArgOffset = VecArgOffset; 2247 VecArgOffset += 16; 2248 } else { 2249 // Vectors are aligned. 2250 ArgOffset = ((ArgOffset+15)/16)*16; 2251 CurArgOffset = ArgOffset; 2252 ArgOffset += 16; 2253 } 2254 needsLoad = true; 2255 } 2256 break; 2257 } 2258 2259 // We need to load the argument to a virtual register if we determined above 2260 // that we ran out of physical registers of the appropriate type. 2261 if (needsLoad) { 2262 int FI = MFI->CreateFixedObject(ObjSize, 2263 CurArgOffset + (ArgSize - ObjSize), 2264 isImmutable); 2265 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2266 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2267 false, false, false, 0); 2268 } 2269 2270 InVals.push_back(ArgVal); 2271 } 2272 2273 // Set the size that is at least reserved in caller of this function. Tail 2274 // call optimized function's reserved stack space needs to be aligned so that 2275 // taking the difference between two stack areas will result in an aligned 2276 // stack. 2277 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2278 // Add the Altivec parameters at the end, if needed. 2279 if (nAltivecParamsAtEnd) { 2280 MinReservedArea = ((MinReservedArea+15)/16)*16; 2281 MinReservedArea += 16*nAltivecParamsAtEnd; 2282 } 2283 MinReservedArea = 2284 std::max(MinReservedArea, 2285 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2286 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2287 getStackAlignment(); 2288 unsigned AlignMask = TargetAlign-1; 2289 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2290 FI->setMinReservedArea(MinReservedArea); 2291 2292 // If the function takes variable number of arguments, make a frame index for 2293 // the start of the first vararg value... for expansion of llvm.va_start. 2294 if (isVarArg) { 2295 int Depth = ArgOffset; 2296 2297 FuncInfo->setVarArgsFrameIndex( 2298 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2299 Depth, true)); 2300 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2301 2302 // If this function is vararg, store any remaining integer argument regs 2303 // to their spots on the stack so that they may be loaded by deferencing the 2304 // result of va_next. 2305 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2306 unsigned VReg; 2307 2308 if (isPPC64) 2309 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2310 else 2311 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2312 2313 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2314 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2315 MachinePointerInfo(), false, false, 0); 2316 MemOps.push_back(Store); 2317 // Increment the address by four for the next argument to store 2318 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2319 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2320 } 2321 } 2322 2323 if (!MemOps.empty()) 2324 Chain = DAG.getNode(ISD::TokenFactor, dl, 2325 MVT::Other, &MemOps[0], MemOps.size()); 2326 2327 return Chain; 2328} 2329 2330/// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus 2331/// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI. 2332static unsigned 2333CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2334 bool isPPC64, 2335 bool isVarArg, 2336 unsigned CC, 2337 const SmallVectorImpl<ISD::OutputArg> 2338 &Outs, 2339 const SmallVectorImpl<SDValue> &OutVals, 2340 unsigned &nAltivecParamsAtEnd) { 2341 // Count how many bytes are to be pushed on the stack, including the linkage 2342 // area, and parameter passing area. We start with 24/48 bytes, which is 2343 // prereserved space for [SP][CR][LR][3 x unused]. 2344 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2345 unsigned NumOps = Outs.size(); 2346 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2347 2348 // Add up all the space actually used. 2349 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2350 // they all go in registers, but we must reserve stack space for them for 2351 // possible use by the caller. In varargs or 64-bit calls, parameters are 2352 // assigned stack space in order, with padding so Altivec parameters are 2353 // 16-byte aligned. 2354 nAltivecParamsAtEnd = 0; 2355 for (unsigned i = 0; i != NumOps; ++i) { 2356 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2357 EVT ArgVT = Outs[i].VT; 2358 // Varargs Altivec parameters are padded to a 16 byte boundary. 2359 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2360 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2361 if (!isVarArg && !isPPC64) { 2362 // Non-varargs Altivec parameters go after all the non-Altivec 2363 // parameters; handle those later so we know how much padding we need. 2364 nAltivecParamsAtEnd++; 2365 continue; 2366 } 2367 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2368 NumBytes = ((NumBytes+15)/16)*16; 2369 } 2370 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2371 } 2372 2373 // Allow for Altivec parameters at the end, if needed. 2374 if (nAltivecParamsAtEnd) { 2375 NumBytes = ((NumBytes+15)/16)*16; 2376 NumBytes += 16*nAltivecParamsAtEnd; 2377 } 2378 2379 // The prolog code of the callee may store up to 8 GPR argument registers to 2380 // the stack, allowing va_start to index over them in memory if its varargs. 2381 // Because we cannot tell if this is needed on the caller side, we have to 2382 // conservatively assume that it is needed. As such, make sure we have at 2383 // least enough stack space for the caller to store the 8 GPRs. 2384 NumBytes = std::max(NumBytes, 2385 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2386 2387 // Tail call needs the stack to be aligned. 2388 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){ 2389 unsigned TargetAlign = DAG.getMachineFunction().getTarget(). 2390 getFrameLowering()->getStackAlignment(); 2391 unsigned AlignMask = TargetAlign-1; 2392 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2393 } 2394 2395 return NumBytes; 2396} 2397 2398/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2399/// adjusted to accommodate the arguments for the tailcall. 2400static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2401 unsigned ParamSize) { 2402 2403 if (!isTailCall) return 0; 2404 2405 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2406 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2407 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2408 // Remember only if the new adjustement is bigger. 2409 if (SPDiff < FI->getTailCallSPDelta()) 2410 FI->setTailCallSPDelta(SPDiff); 2411 2412 return SPDiff; 2413} 2414 2415/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2416/// for tail call optimization. Targets which want to do tail call 2417/// optimization should implement this function. 2418bool 2419PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2420 CallingConv::ID CalleeCC, 2421 bool isVarArg, 2422 const SmallVectorImpl<ISD::InputArg> &Ins, 2423 SelectionDAG& DAG) const { 2424 if (!getTargetMachine().Options.GuaranteedTailCallOpt) 2425 return false; 2426 2427 // Variable argument functions are not supported. 2428 if (isVarArg) 2429 return false; 2430 2431 MachineFunction &MF = DAG.getMachineFunction(); 2432 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2433 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2434 // Functions containing by val parameters are not supported. 2435 for (unsigned i = 0; i != Ins.size(); i++) { 2436 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2437 if (Flags.isByVal()) return false; 2438 } 2439 2440 // Non PIC/GOT tail calls are supported. 2441 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2442 return true; 2443 2444 // At the moment we can only do local tail calls (in same module, hidden 2445 // or protected) if we are generating PIC. 2446 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2447 return G->getGlobal()->hasHiddenVisibility() 2448 || G->getGlobal()->hasProtectedVisibility(); 2449 } 2450 2451 return false; 2452} 2453 2454/// isCallCompatibleAddress - Return the immediate to use if the specified 2455/// 32-bit value is representable in the immediate field of a BxA instruction. 2456static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2457 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2458 if (!C) return 0; 2459 2460 int Addr = C->getZExtValue(); 2461 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2462 SignExtend32<26>(Addr) != Addr) 2463 return 0; // Top 6 bits have to be sext of immediate. 2464 2465 return DAG.getConstant((int)C->getZExtValue() >> 2, 2466 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2467} 2468 2469namespace { 2470 2471struct TailCallArgumentInfo { 2472 SDValue Arg; 2473 SDValue FrameIdxOp; 2474 int FrameIdx; 2475 2476 TailCallArgumentInfo() : FrameIdx(0) {} 2477}; 2478 2479} 2480 2481/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2482static void 2483StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2484 SDValue Chain, 2485 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2486 SmallVector<SDValue, 8> &MemOpChains, 2487 DebugLoc dl) { 2488 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2489 SDValue Arg = TailCallArgs[i].Arg; 2490 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2491 int FI = TailCallArgs[i].FrameIdx; 2492 // Store relative to framepointer. 2493 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2494 MachinePointerInfo::getFixedStack(FI), 2495 false, false, 0)); 2496 } 2497} 2498 2499/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2500/// the appropriate stack slot for the tail call optimized function call. 2501static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2502 MachineFunction &MF, 2503 SDValue Chain, 2504 SDValue OldRetAddr, 2505 SDValue OldFP, 2506 int SPDiff, 2507 bool isPPC64, 2508 bool isDarwinABI, 2509 DebugLoc dl) { 2510 if (SPDiff) { 2511 // Calculate the new stack slot for the return address. 2512 int SlotSize = isPPC64 ? 8 : 4; 2513 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 2514 isDarwinABI); 2515 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2516 NewRetAddrLoc, true); 2517 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2518 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2519 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2520 MachinePointerInfo::getFixedStack(NewRetAddr), 2521 false, false, 0); 2522 2523 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2524 // slot as the FP is never overwritten. 2525 if (isDarwinABI) { 2526 int NewFPLoc = 2527 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2528 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2529 true); 2530 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2531 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2532 MachinePointerInfo::getFixedStack(NewFPIdx), 2533 false, false, 0); 2534 } 2535 } 2536 return Chain; 2537} 2538 2539/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2540/// the position of the argument. 2541static void 2542CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2543 SDValue Arg, int SPDiff, unsigned ArgOffset, 2544 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2545 int Offset = ArgOffset + SPDiff; 2546 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2547 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2548 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2549 SDValue FIN = DAG.getFrameIndex(FI, VT); 2550 TailCallArgumentInfo Info; 2551 Info.Arg = Arg; 2552 Info.FrameIdxOp = FIN; 2553 Info.FrameIdx = FI; 2554 TailCallArguments.push_back(Info); 2555} 2556 2557/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2558/// stack slot. Returns the chain as result and the loaded frame pointers in 2559/// LROpOut/FPOpout. Used when tail calling. 2560SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2561 int SPDiff, 2562 SDValue Chain, 2563 SDValue &LROpOut, 2564 SDValue &FPOpOut, 2565 bool isDarwinABI, 2566 DebugLoc dl) const { 2567 if (SPDiff) { 2568 // Load the LR and FP stack slot for later adjusting. 2569 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2570 LROpOut = getReturnAddrFrameIndex(DAG); 2571 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2572 false, false, false, 0); 2573 Chain = SDValue(LROpOut.getNode(), 1); 2574 2575 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2576 // slot as the FP is never overwritten. 2577 if (isDarwinABI) { 2578 FPOpOut = getFramePointerFrameIndex(DAG); 2579 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 2580 false, false, false, 0); 2581 Chain = SDValue(FPOpOut.getNode(), 1); 2582 } 2583 } 2584 return Chain; 2585} 2586 2587/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2588/// by "Src" to address "Dst" of size "Size". Alignment information is 2589/// specified by the specific parameter attribute. The copy will be passed as 2590/// a byval function parameter. 2591/// Sometimes what we are copying is the end of a larger object, the part that 2592/// does not fit in registers. 2593static SDValue 2594CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2595 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2596 DebugLoc dl) { 2597 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2598 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2599 false, false, MachinePointerInfo(0), 2600 MachinePointerInfo(0)); 2601} 2602 2603/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2604/// tail calls. 2605static void 2606LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2607 SDValue Arg, SDValue PtrOff, int SPDiff, 2608 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2609 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2610 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 2611 DebugLoc dl) { 2612 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2613 if (!isTailCall) { 2614 if (isVector) { 2615 SDValue StackPtr; 2616 if (isPPC64) 2617 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2618 else 2619 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2620 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2621 DAG.getConstant(ArgOffset, PtrVT)); 2622 } 2623 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2624 MachinePointerInfo(), false, false, 0)); 2625 // Calculate and remember argument location. 2626 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2627 TailCallArguments); 2628} 2629 2630static 2631void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2632 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2633 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2634 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2635 MachineFunction &MF = DAG.getMachineFunction(); 2636 2637 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2638 // might overwrite each other in case of tail call optimization. 2639 SmallVector<SDValue, 8> MemOpChains2; 2640 // Do not flag preceding copytoreg stuff together with the following stuff. 2641 InFlag = SDValue(); 2642 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2643 MemOpChains2, dl); 2644 if (!MemOpChains2.empty()) 2645 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2646 &MemOpChains2[0], MemOpChains2.size()); 2647 2648 // Store the return address to the appropriate stack slot. 2649 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2650 isPPC64, isDarwinABI, dl); 2651 2652 // Emit callseq_end just before tailcall node. 2653 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2654 DAG.getIntPtrConstant(0, true), InFlag); 2655 InFlag = Chain.getValue(1); 2656} 2657 2658static 2659unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2660 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2661 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2662 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2663 const PPCSubtarget &PPCSubTarget) { 2664 2665 bool isPPC64 = PPCSubTarget.isPPC64(); 2666 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 2667 2668 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2669 NodeTys.push_back(MVT::Other); // Returns a chain 2670 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 2671 2672 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2673 2674 bool needIndirectCall = true; 2675 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 2676 // If this is an absolute destination address, use the munged value. 2677 Callee = SDValue(Dest, 0); 2678 needIndirectCall = false; 2679 } 2680 2681 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2682 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 2683 // Use indirect calls for ALL functions calls in JIT mode, since the 2684 // far-call stubs may be outside relocation limits for a BL instruction. 2685 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 2686 unsigned OpFlags = 0; 2687 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 2688 (PPCSubTarget.getTargetTriple().isMacOSX() && 2689 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 2690 (G->getGlobal()->isDeclaration() || 2691 G->getGlobal()->isWeakForLinker())) { 2692 // PC-relative references to external symbols should go through $stub, 2693 // unless we're building with the leopard linker or later, which 2694 // automatically synthesizes these stubs. 2695 OpFlags = PPCII::MO_DARWIN_STUB; 2696 } 2697 2698 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 2699 // every direct call is) turn it into a TargetGlobalAddress / 2700 // TargetExternalSymbol node so that legalize doesn't hack it. 2701 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2702 Callee.getValueType(), 2703 0, OpFlags); 2704 needIndirectCall = false; 2705 } 2706 } 2707 2708 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2709 unsigned char OpFlags = 0; 2710 2711 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 2712 (PPCSubTarget.getTargetTriple().isMacOSX() && 2713 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 2714 // PC-relative references to external symbols should go through $stub, 2715 // unless we're building with the leopard linker or later, which 2716 // automatically synthesizes these stubs. 2717 OpFlags = PPCII::MO_DARWIN_STUB; 2718 } 2719 2720 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 2721 OpFlags); 2722 needIndirectCall = false; 2723 } 2724 2725 if (needIndirectCall) { 2726 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2727 // to do the call, we can't use PPCISD::CALL. 2728 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2729 2730 if (isSVR4ABI && isPPC64) { 2731 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2732 // entry point, but to the function descriptor (the function entry point 2733 // address is part of the function descriptor though). 2734 // The function descriptor is a three doubleword structure with the 2735 // following fields: function entry point, TOC base address and 2736 // environment pointer. 2737 // Thus for a call through a function pointer, the following actions need 2738 // to be performed: 2739 // 1. Save the TOC of the caller in the TOC save area of its stack 2740 // frame (this is done in LowerCall_Darwin_Or_64SVR4()). 2741 // 2. Load the address of the function entry point from the function 2742 // descriptor. 2743 // 3. Load the TOC of the callee from the function descriptor into r2. 2744 // 4. Load the environment pointer from the function descriptor into 2745 // r11. 2746 // 5. Branch to the function entry point address. 2747 // 6. On return of the callee, the TOC of the caller needs to be 2748 // restored (this is done in FinishCall()). 2749 // 2750 // All those operations are flagged together to ensure that no other 2751 // operations can be scheduled in between. E.g. without flagging the 2752 // operations together, a TOC access in the caller could be scheduled 2753 // between the load of the callee TOC and the branch to the callee, which 2754 // results in the TOC access going through the TOC of the callee instead 2755 // of going through the TOC of the caller, which leads to incorrect code. 2756 2757 // Load the address of the function entry point from the function 2758 // descriptor. 2759 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 2760 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2761 InFlag.getNode() ? 3 : 2); 2762 Chain = LoadFuncPtr.getValue(1); 2763 InFlag = LoadFuncPtr.getValue(2); 2764 2765 // Load environment pointer into r11. 2766 // Offset of the environment pointer within the function descriptor. 2767 SDValue PtrOff = DAG.getIntPtrConstant(16); 2768 2769 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2770 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2771 InFlag); 2772 Chain = LoadEnvPtr.getValue(1); 2773 InFlag = LoadEnvPtr.getValue(2); 2774 2775 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2776 InFlag); 2777 Chain = EnvVal.getValue(0); 2778 InFlag = EnvVal.getValue(1); 2779 2780 // Load TOC of the callee into r2. We are using a target-specific load 2781 // with r2 hard coded, because the result of a target-independent load 2782 // would never go directly into r2, since r2 is a reserved register (which 2783 // prevents the register allocator from allocating it), resulting in an 2784 // additional register being allocated and an unnecessary move instruction 2785 // being generated. 2786 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 2787 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2788 Callee, InFlag); 2789 Chain = LoadTOCPtr.getValue(0); 2790 InFlag = LoadTOCPtr.getValue(1); 2791 2792 MTCTROps[0] = Chain; 2793 MTCTROps[1] = LoadFuncPtr; 2794 MTCTROps[2] = InFlag; 2795 } 2796 2797 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2798 2 + (InFlag.getNode() != 0)); 2799 InFlag = Chain.getValue(1); 2800 2801 NodeTys.clear(); 2802 NodeTys.push_back(MVT::Other); 2803 NodeTys.push_back(MVT::Glue); 2804 Ops.push_back(Chain); 2805 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2806 Callee.setNode(0); 2807 // Add CTR register as callee so a bctr can be emitted later. 2808 if (isTailCall) 2809 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 2810 } 2811 2812 // If this is a direct call, pass the chain and the callee. 2813 if (Callee.getNode()) { 2814 Ops.push_back(Chain); 2815 Ops.push_back(Callee); 2816 } 2817 // If this is a tail call add stack pointer delta. 2818 if (isTailCall) 2819 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2820 2821 // Add argument registers to the end of the list so that they are known live 2822 // into the call. 2823 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2824 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2825 RegsToPass[i].second.getValueType())); 2826 2827 return CallOpc; 2828} 2829 2830static 2831bool isLocalCall(const SDValue &Callee) 2832{ 2833 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2834 return !G->getGlobal()->isDeclaration() && 2835 !G->getGlobal()->isWeakForLinker(); 2836 return false; 2837} 2838 2839SDValue 2840PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2841 CallingConv::ID CallConv, bool isVarArg, 2842 const SmallVectorImpl<ISD::InputArg> &Ins, 2843 DebugLoc dl, SelectionDAG &DAG, 2844 SmallVectorImpl<SDValue> &InVals) const { 2845 2846 SmallVector<CCValAssign, 16> RVLocs; 2847 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2848 getTargetMachine(), RVLocs, *DAG.getContext()); 2849 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2850 2851 // Copy all of the result registers out of their specified physreg. 2852 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2853 CCValAssign &VA = RVLocs[i]; 2854 EVT VT = VA.getValVT(); 2855 assert(VA.isRegLoc() && "Can only return in registers!"); 2856 Chain = DAG.getCopyFromReg(Chain, dl, 2857 VA.getLocReg(), VT, InFlag).getValue(1); 2858 InVals.push_back(Chain.getValue(0)); 2859 InFlag = Chain.getValue(2); 2860 } 2861 2862 return Chain; 2863} 2864 2865SDValue 2866PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2867 bool isTailCall, bool isVarArg, 2868 SelectionDAG &DAG, 2869 SmallVector<std::pair<unsigned, SDValue>, 8> 2870 &RegsToPass, 2871 SDValue InFlag, SDValue Chain, 2872 SDValue &Callee, 2873 int SPDiff, unsigned NumBytes, 2874 const SmallVectorImpl<ISD::InputArg> &Ins, 2875 SmallVectorImpl<SDValue> &InVals) const { 2876 std::vector<EVT> NodeTys; 2877 SmallVector<SDValue, 8> Ops; 2878 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2879 isTailCall, RegsToPass, Ops, NodeTys, 2880 PPCSubTarget); 2881 2882 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls 2883 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 2884 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); 2885 2886 // When performing tail call optimization the callee pops its arguments off 2887 // the stack. Account for this here so these bytes can be pushed back on in 2888 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2889 int BytesCalleePops = 2890 (CallConv == CallingConv::Fast && 2891 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0; 2892 2893 // Add a register mask operand representing the call-preserved registers. 2894 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2895 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2896 assert(Mask && "Missing call preserved mask for calling convention"); 2897 Ops.push_back(DAG.getRegisterMask(Mask)); 2898 2899 if (InFlag.getNode()) 2900 Ops.push_back(InFlag); 2901 2902 // Emit tail call. 2903 if (isTailCall) { 2904 // If this is the first return lowered for this function, add the regs 2905 // to the liveout set for the function. 2906 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2907 SmallVector<CCValAssign, 16> RVLocs; 2908 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2909 getTargetMachine(), RVLocs, *DAG.getContext()); 2910 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2911 for (unsigned i = 0; i != RVLocs.size(); ++i) 2912 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2913 } 2914 2915 assert(((Callee.getOpcode() == ISD::Register && 2916 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2917 Callee.getOpcode() == ISD::TargetExternalSymbol || 2918 Callee.getOpcode() == ISD::TargetGlobalAddress || 2919 isa<ConstantSDNode>(Callee)) && 2920 "Expecting an global address, external symbol, absolute value or register"); 2921 2922 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2923 } 2924 2925 // Add a NOP immediately after the branch instruction when using the 64-bit 2926 // SVR4 ABI. At link time, if caller and callee are in a different module and 2927 // thus have a different TOC, the call will be replaced with a call to a stub 2928 // function which saves the current TOC, loads the TOC of the callee and 2929 // branches to the callee. The NOP will be replaced with a load instruction 2930 // which restores the TOC of the caller from the TOC save slot of the current 2931 // stack frame. If caller and callee belong to the same module (and have the 2932 // same TOC), the NOP will remain unchanged. 2933 2934 bool needsTOCRestore = false; 2935 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2936 if (CallOpc == PPCISD::BCTRL_SVR4) { 2937 // This is a call through a function pointer. 2938 // Restore the caller TOC from the save area into R2. 2939 // See PrepareCall() for more information about calls through function 2940 // pointers in the 64-bit SVR4 ABI. 2941 // We are using a target-specific load with r2 hard coded, because the 2942 // result of a target-independent load would never go directly into r2, 2943 // since r2 is a reserved register (which prevents the register allocator 2944 // from allocating it), resulting in an additional register being 2945 // allocated and an unnecessary move instruction being generated. 2946 needsTOCRestore = true; 2947 } else if ((CallOpc == PPCISD::CALL_SVR4) && !isLocalCall(Callee)) { 2948 // Otherwise insert NOP for non-local calls. 2949 CallOpc = PPCISD::CALL_NOP_SVR4; 2950 } 2951 } 2952 2953 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2954 InFlag = Chain.getValue(1); 2955 2956 if (needsTOCRestore) { 2957 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 2958 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2959 InFlag = Chain.getValue(1); 2960 } 2961 2962 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2963 DAG.getIntPtrConstant(BytesCalleePops, true), 2964 InFlag); 2965 if (!Ins.empty()) 2966 InFlag = Chain.getValue(1); 2967 2968 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2969 Ins, dl, DAG, InVals); 2970} 2971 2972SDValue 2973PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2974 SmallVectorImpl<SDValue> &InVals) const { 2975 SelectionDAG &DAG = CLI.DAG; 2976 DebugLoc &dl = CLI.DL; 2977 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2978 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2979 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2980 SDValue Chain = CLI.Chain; 2981 SDValue Callee = CLI.Callee; 2982 bool &isTailCall = CLI.IsTailCall; 2983 CallingConv::ID CallConv = CLI.CallConv; 2984 bool isVarArg = CLI.IsVarArg; 2985 2986 if (isTailCall) 2987 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2988 Ins, DAG); 2989 2990 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 2991 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg, 2992 isTailCall, Outs, OutVals, Ins, 2993 dl, DAG, InVals); 2994 2995 return LowerCall_Darwin_Or_64SVR4(Chain, Callee, CallConv, isVarArg, 2996 isTailCall, Outs, OutVals, Ins, 2997 dl, DAG, InVals); 2998} 2999 3000SDValue 3001PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, 3002 CallingConv::ID CallConv, bool isVarArg, 3003 bool isTailCall, 3004 const SmallVectorImpl<ISD::OutputArg> &Outs, 3005 const SmallVectorImpl<SDValue> &OutVals, 3006 const SmallVectorImpl<ISD::InputArg> &Ins, 3007 DebugLoc dl, SelectionDAG &DAG, 3008 SmallVectorImpl<SDValue> &InVals) const { 3009 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description 3010 // of the 32-bit SVR4 ABI stack frame layout. 3011 3012 assert((CallConv == CallingConv::C || 3013 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 3014 3015 unsigned PtrByteSize = 4; 3016 3017 MachineFunction &MF = DAG.getMachineFunction(); 3018 3019 // Mark this function as potentially containing a function that contains a 3020 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3021 // and restoring the callers stack pointer in this functions epilog. This is 3022 // done because by tail calling the called function might overwrite the value 3023 // in this function's (MF) stack pointer stack slot 0(SP). 3024 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3025 CallConv == CallingConv::Fast) 3026 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3027 3028 // Count how many bytes are to be pushed on the stack, including the linkage 3029 // area, parameter list area and the part of the local variable space which 3030 // contains copies of aggregates which are passed by value. 3031 3032 // Assign locations to all of the outgoing arguments. 3033 SmallVector<CCValAssign, 16> ArgLocs; 3034 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3035 getTargetMachine(), ArgLocs, *DAG.getContext()); 3036 3037 // Reserve space for the linkage area on the stack. 3038 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 3039 3040 if (isVarArg) { 3041 // Handle fixed and variable vector arguments differently. 3042 // Fixed vector arguments go into registers as long as registers are 3043 // available. Variable vector arguments always go into memory. 3044 unsigned NumArgs = Outs.size(); 3045 3046 for (unsigned i = 0; i != NumArgs; ++i) { 3047 MVT ArgVT = Outs[i].VT; 3048 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 3049 bool Result; 3050 3051 if (Outs[i].IsFixed) { 3052 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 3053 CCInfo); 3054 } else { 3055 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 3056 ArgFlags, CCInfo); 3057 } 3058 3059 if (Result) { 3060#ifndef NDEBUG 3061 errs() << "Call operand #" << i << " has unhandled type " 3062 << EVT(ArgVT).getEVTString() << "\n"; 3063#endif 3064 llvm_unreachable(0); 3065 } 3066 } 3067 } else { 3068 // All arguments are treated the same. 3069 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 3070 } 3071 3072 // Assign locations to all of the outgoing aggregate by value arguments. 3073 SmallVector<CCValAssign, 16> ByValArgLocs; 3074 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3075 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 3076 3077 // Reserve stack space for the allocations in CCInfo. 3078 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 3079 3080 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 3081 3082 // Size of the linkage area, parameter list area and the part of the local 3083 // space variable where copies of aggregates which are passed by value are 3084 // stored. 3085 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 3086 3087 // Calculate by how many bytes the stack has to be adjusted in case of tail 3088 // call optimization. 3089 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3090 3091 // Adjust the stack pointer for the new arguments... 3092 // These operations are automatically eliminated by the prolog/epilog pass 3093 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3094 SDValue CallSeqStart = Chain; 3095 3096 // Load the return address and frame pointer so it can be moved somewhere else 3097 // later. 3098 SDValue LROp, FPOp; 3099 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 3100 dl); 3101 3102 // Set up a copy of the stack pointer for use loading and storing any 3103 // arguments that may not fit in the registers available for argument 3104 // passing. 3105 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3106 3107 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3108 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3109 SmallVector<SDValue, 8> MemOpChains; 3110 3111 bool seenFloatArg = false; 3112 // Walk the register/memloc assignments, inserting copies/loads. 3113 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 3114 i != e; 3115 ++i) { 3116 CCValAssign &VA = ArgLocs[i]; 3117 SDValue Arg = OutVals[i]; 3118 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3119 3120 if (Flags.isByVal()) { 3121 // Argument is an aggregate which is passed by value, thus we need to 3122 // create a copy of it in the local variable space of the current stack 3123 // frame (which is the stack frame of the caller) and pass the address of 3124 // this copy to the callee. 3125 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 3126 CCValAssign &ByValVA = ByValArgLocs[j++]; 3127 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 3128 3129 // Memory reserved in the local variable space of the callers stack frame. 3130 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 3131 3132 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3133 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3134 3135 // Create a copy of the argument in the local area of the current 3136 // stack frame. 3137 SDValue MemcpyCall = 3138 CreateCopyOfByValArgument(Arg, PtrOff, 3139 CallSeqStart.getNode()->getOperand(0), 3140 Flags, DAG, dl); 3141 3142 // This must go outside the CALLSEQ_START..END. 3143 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3144 CallSeqStart.getNode()->getOperand(1)); 3145 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3146 NewCallSeqStart.getNode()); 3147 Chain = CallSeqStart = NewCallSeqStart; 3148 3149 // Pass the address of the aggregate copy on the stack either in a 3150 // physical register or in the parameter list area of the current stack 3151 // frame to the callee. 3152 Arg = PtrOff; 3153 } 3154 3155 if (VA.isRegLoc()) { 3156 seenFloatArg |= VA.getLocVT().isFloatingPoint(); 3157 // Put argument in a physical register. 3158 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3159 } else { 3160 // Put argument in the parameter list area of the current stack frame. 3161 assert(VA.isMemLoc()); 3162 unsigned LocMemOffset = VA.getLocMemOffset(); 3163 3164 if (!isTailCall) { 3165 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3166 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3167 3168 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3169 MachinePointerInfo(), 3170 false, false, 0)); 3171 } else { 3172 // Calculate and remember argument location. 3173 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 3174 TailCallArguments); 3175 } 3176 } 3177 } 3178 3179 if (!MemOpChains.empty()) 3180 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3181 &MemOpChains[0], MemOpChains.size()); 3182 3183 // Build a sequence of copy-to-reg nodes chained together with token chain 3184 // and flag operands which copy the outgoing args into the appropriate regs. 3185 SDValue InFlag; 3186 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3187 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3188 RegsToPass[i].second, InFlag); 3189 InFlag = Chain.getValue(1); 3190 } 3191 3192 // Set CR bit 6 to true if this is a vararg call with floating args passed in 3193 // registers. 3194 if (isVarArg) { 3195 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3196 SDValue Ops[] = { Chain, InFlag }; 3197 3198 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, 3199 dl, VTs, Ops, InFlag.getNode() ? 2 : 1); 3200 3201 InFlag = Chain.getValue(1); 3202 } 3203 3204 if (isTailCall) 3205 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 3206 false, TailCallArguments); 3207 3208 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3209 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3210 Ins, InVals); 3211} 3212 3213SDValue 3214PPCTargetLowering::LowerCall_Darwin_Or_64SVR4(SDValue Chain, SDValue Callee, 3215 CallingConv::ID CallConv, bool isVarArg, 3216 bool isTailCall, 3217 const SmallVectorImpl<ISD::OutputArg> &Outs, 3218 const SmallVectorImpl<SDValue> &OutVals, 3219 const SmallVectorImpl<ISD::InputArg> &Ins, 3220 DebugLoc dl, SelectionDAG &DAG, 3221 SmallVectorImpl<SDValue> &InVals) const { 3222 3223 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 3224 3225 unsigned NumOps = Outs.size(); 3226 3227 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3228 bool isPPC64 = PtrVT == MVT::i64; 3229 unsigned PtrByteSize = isPPC64 ? 8 : 4; 3230 3231 MachineFunction &MF = DAG.getMachineFunction(); 3232 3233 // Mark this function as potentially containing a function that contains a 3234 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3235 // and restoring the callers stack pointer in this functions epilog. This is 3236 // done because by tail calling the called function might overwrite the value 3237 // in this function's (MF) stack pointer stack slot 0(SP). 3238 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3239 CallConv == CallingConv::Fast) 3240 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3241 3242 unsigned nAltivecParamsAtEnd = 0; 3243 3244 // Count how many bytes are to be pushed on the stack, including the linkage 3245 // area, and parameter passing area. We start with 24/48 bytes, which is 3246 // prereserved space for [SP][CR][LR][3 x unused]. 3247 unsigned NumBytes = 3248 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 3249 Outs, OutVals, 3250 nAltivecParamsAtEnd); 3251 3252 // Calculate by how many bytes the stack has to be adjusted in case of tail 3253 // call optimization. 3254 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3255 3256 // To protect arguments on the stack from being clobbered in a tail call, 3257 // force all the loads to happen before doing any other lowering. 3258 if (isTailCall) 3259 Chain = DAG.getStackArgumentTokenFactor(Chain); 3260 3261 // Adjust the stack pointer for the new arguments... 3262 // These operations are automatically eliminated by the prolog/epilog pass 3263 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3264 SDValue CallSeqStart = Chain; 3265 3266 // Load the return address and frame pointer so it can be move somewhere else 3267 // later. 3268 SDValue LROp, FPOp; 3269 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 3270 dl); 3271 3272 // Set up a copy of the stack pointer for use loading and storing any 3273 // arguments that may not fit in the registers available for argument 3274 // passing. 3275 SDValue StackPtr; 3276 if (isPPC64) 3277 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3278 else 3279 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3280 3281 // Figure out which arguments are going to go in registers, and which in 3282 // memory. Also, if this is a vararg function, floating point operations 3283 // must be stored to our stack, and loaded into integer regs as well, if 3284 // any integer regs are available for argument passing. 3285 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 3286 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3287 3288 static const uint16_t GPR_32[] = { // 32-bit registers. 3289 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 3290 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 3291 }; 3292 static const uint16_t GPR_64[] = { // 64-bit registers. 3293 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3294 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3295 }; 3296 static const uint16_t *FPR = GetFPR(); 3297 3298 static const uint16_t VR[] = { 3299 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3300 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3301 }; 3302 const unsigned NumGPRs = array_lengthof(GPR_32); 3303 const unsigned NumFPRs = 13; 3304 const unsigned NumVRs = array_lengthof(VR); 3305 3306 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 3307 3308 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3309 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3310 3311 SmallVector<SDValue, 8> MemOpChains; 3312 for (unsigned i = 0; i != NumOps; ++i) { 3313 SDValue Arg = OutVals[i]; 3314 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3315 3316 // PtrOff will be used to store the current argument to the stack if a 3317 // register cannot be found for it. 3318 SDValue PtrOff; 3319 3320 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3321 3322 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3323 3324 // On PPC64, promote integers to 64-bit values. 3325 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3326 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3327 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3328 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3329 } 3330 3331 // FIXME memcpy is used way more than necessary. Correctness first. 3332 // Note: "by value" is code for passing a structure by value, not 3333 // basic types. 3334 if (Flags.isByVal()) { 3335 // Note: Size includes alignment padding, so 3336 // struct x { short a; char b; } 3337 // will have Size = 4. With #pragma pack(1), it will have Size = 3. 3338 // These are the proper values we need for right-justifying the 3339 // aggregate in a parameter register for 64-bit SVR4. 3340 unsigned Size = Flags.getByValSize(); 3341 // FOR DARWIN ONLY: Very small objects are passed right-justified. 3342 // Everything else is passed left-justified. 3343 // FOR 64-BIT SVR4: All aggregates smaller than 8 bytes must 3344 // be passed right-justified. 3345 if (Size==1 || Size==2 || 3346 (Size==4 && isSVR4ABI)) { 3347 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); 3348 if (GPR_idx != NumGPRs) { 3349 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3350 MachinePointerInfo(), VT, 3351 false, false, 0); 3352 MemOpChains.push_back(Load.getValue(1)); 3353 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3354 3355 ArgOffset += PtrByteSize; 3356 } else { 3357 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3358 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3359 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3360 CallSeqStart.getNode()->getOperand(0), 3361 Flags, DAG, dl); 3362 // This must go outside the CALLSEQ_START..END. 3363 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3364 CallSeqStart.getNode()->getOperand(1)); 3365 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3366 NewCallSeqStart.getNode()); 3367 Chain = CallSeqStart = NewCallSeqStart; 3368 ArgOffset += PtrByteSize; 3369 } 3370 continue; 3371 } 3372 // Copy entire object into memory. There are cases where gcc-generated 3373 // code assumes it is there, even if it could be put entirely into 3374 // registers. (This is not what the doc says.) 3375 3376 // FIXME: The above statement is likely due to a misunderstanding of the 3377 // documents. At least for 64-bit SVR4, all arguments must be copied 3378 // into the parameter area BY THE CALLEE in the event that the callee 3379 // takes the address of any formal argument. That has not yet been 3380 // implemented. However, it is reasonable to use the stack area as a 3381 // staging area for the register load. 3382 3383 // Skip this for small aggregates under 64-bit SVR4, as we will use 3384 // the same slot for a right-justified copy, below. 3385 if (Size >= 8 || !isSVR4ABI) { 3386 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3387 CallSeqStart.getNode()->getOperand(0), 3388 Flags, DAG, dl); 3389 // This must go outside the CALLSEQ_START..END. 3390 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3391 CallSeqStart.getNode()->getOperand(1)); 3392 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3393 NewCallSeqStart.getNode()); 3394 Chain = CallSeqStart = NewCallSeqStart; 3395 } 3396 3397 // FOR 64-BIT SVR4: When a register is available, pass the 3398 // aggregate right-justified. 3399 if (isSVR4ABI && Size < 8 && GPR_idx != NumGPRs) { 3400 // The easiest way to get this right-justified in a register 3401 // is to copy the structure into the rightmost portion of a 3402 // local variable slot, then load the whole slot into the 3403 // register. 3404 // FIXME: The memcpy seems to produce pretty awful code for 3405 // small aggregates, particularly for packed ones. 3406 // FIXME: It would be preferable to use the slot in the 3407 // parameter save area instead of a new local variable. 3408 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType()); 3409 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3410 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3411 CallSeqStart.getNode()->getOperand(0), 3412 Flags, DAG, dl); 3413 3414 // Place the memcpy outside the CALLSEQ_START..END. 3415 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3416 CallSeqStart.getNode()->getOperand(1)); 3417 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3418 NewCallSeqStart.getNode()); 3419 Chain = CallSeqStart = NewCallSeqStart; 3420 3421 // Load the slot into the register. 3422 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff, 3423 MachinePointerInfo(), 3424 false, false, false, 0); 3425 MemOpChains.push_back(Load.getValue(1)); 3426 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3427 3428 // Done with this argument. 3429 ArgOffset += PtrByteSize; 3430 continue; 3431 } 3432 3433 // For small aggregates (Darwin only) and aggregates >= PtrByteSize, 3434 // copy the pieces of the object that fit into registers from the 3435 // parameter save area. 3436 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3437 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3438 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3439 if (GPR_idx != NumGPRs) { 3440 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3441 MachinePointerInfo(), 3442 false, false, false, 0); 3443 MemOpChains.push_back(Load.getValue(1)); 3444 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3445 ArgOffset += PtrByteSize; 3446 } else { 3447 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3448 break; 3449 } 3450 } 3451 continue; 3452 } 3453 3454 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3455 default: llvm_unreachable("Unexpected ValueType for argument!"); 3456 case MVT::i32: 3457 case MVT::i64: 3458 if (GPR_idx != NumGPRs) { 3459 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3460 } else { 3461 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3462 isPPC64, isTailCall, false, MemOpChains, 3463 TailCallArguments, dl); 3464 } 3465 ArgOffset += PtrByteSize; 3466 break; 3467 case MVT::f32: 3468 case MVT::f64: 3469 if (FPR_idx != NumFPRs) { 3470 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3471 3472 if (isVarArg) { 3473 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3474 MachinePointerInfo(), false, false, 0); 3475 MemOpChains.push_back(Store); 3476 3477 // Float varargs are always shadowed in available integer registers 3478 if (GPR_idx != NumGPRs) { 3479 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3480 MachinePointerInfo(), false, false, 3481 false, 0); 3482 MemOpChains.push_back(Load.getValue(1)); 3483 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3484 } 3485 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3486 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3487 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3488 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3489 MachinePointerInfo(), 3490 false, false, false, 0); 3491 MemOpChains.push_back(Load.getValue(1)); 3492 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3493 } 3494 } else { 3495 // If we have any FPRs remaining, we may also have GPRs remaining. 3496 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3497 // GPRs. 3498 if (GPR_idx != NumGPRs) 3499 ++GPR_idx; 3500 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3501 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3502 ++GPR_idx; 3503 } 3504 } else { 3505 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3506 isPPC64, isTailCall, false, MemOpChains, 3507 TailCallArguments, dl); 3508 } 3509 if (isPPC64) 3510 ArgOffset += 8; 3511 else 3512 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3513 break; 3514 case MVT::v4f32: 3515 case MVT::v4i32: 3516 case MVT::v8i16: 3517 case MVT::v16i8: 3518 if (isVarArg) { 3519 // These go aligned on the stack, or in the corresponding R registers 3520 // when within range. The Darwin PPC ABI doc claims they also go in 3521 // V registers; in fact gcc does this only for arguments that are 3522 // prototyped, not for those that match the ... We do it for all 3523 // arguments, seems to work. 3524 while (ArgOffset % 16 !=0) { 3525 ArgOffset += PtrByteSize; 3526 if (GPR_idx != NumGPRs) 3527 GPR_idx++; 3528 } 3529 // We could elide this store in the case where the object fits 3530 // entirely in R registers. Maybe later. 3531 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3532 DAG.getConstant(ArgOffset, PtrVT)); 3533 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3534 MachinePointerInfo(), false, false, 0); 3535 MemOpChains.push_back(Store); 3536 if (VR_idx != NumVRs) { 3537 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3538 MachinePointerInfo(), 3539 false, false, false, 0); 3540 MemOpChains.push_back(Load.getValue(1)); 3541 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3542 } 3543 ArgOffset += 16; 3544 for (unsigned i=0; i<16; i+=PtrByteSize) { 3545 if (GPR_idx == NumGPRs) 3546 break; 3547 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3548 DAG.getConstant(i, PtrVT)); 3549 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3550 false, false, false, 0); 3551 MemOpChains.push_back(Load.getValue(1)); 3552 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3553 } 3554 break; 3555 } 3556 3557 // Non-varargs Altivec params generally go in registers, but have 3558 // stack space allocated at the end. 3559 if (VR_idx != NumVRs) { 3560 // Doesn't have GPR space allocated. 3561 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3562 } else if (nAltivecParamsAtEnd==0) { 3563 // We are emitting Altivec params in order. 3564 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3565 isPPC64, isTailCall, true, MemOpChains, 3566 TailCallArguments, dl); 3567 ArgOffset += 16; 3568 } 3569 break; 3570 } 3571 } 3572 // If all Altivec parameters fit in registers, as they usually do, 3573 // they get stack space following the non-Altivec parameters. We 3574 // don't track this here because nobody below needs it. 3575 // If there are more Altivec parameters than fit in registers emit 3576 // the stores here. 3577 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3578 unsigned j = 0; 3579 // Offset is aligned; skip 1st 12 params which go in V registers. 3580 ArgOffset = ((ArgOffset+15)/16)*16; 3581 ArgOffset += 12*16; 3582 for (unsigned i = 0; i != NumOps; ++i) { 3583 SDValue Arg = OutVals[i]; 3584 EVT ArgType = Outs[i].VT; 3585 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3586 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3587 if (++j > NumVRs) { 3588 SDValue PtrOff; 3589 // We are emitting Altivec params in order. 3590 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3591 isPPC64, isTailCall, true, MemOpChains, 3592 TailCallArguments, dl); 3593 ArgOffset += 16; 3594 } 3595 } 3596 } 3597 } 3598 3599 if (!MemOpChains.empty()) 3600 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3601 &MemOpChains[0], MemOpChains.size()); 3602 3603 // Check if this is an indirect call (MTCTR/BCTRL). 3604 // See PrepareCall() for more information about calls through function 3605 // pointers in the 64-bit SVR4 ABI. 3606 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3607 !dyn_cast<GlobalAddressSDNode>(Callee) && 3608 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3609 !isBLACompatibleAddress(Callee, DAG)) { 3610 // Load r2 into a virtual register and store it to the TOC save area. 3611 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3612 // TOC save area offset. 3613 SDValue PtrOff = DAG.getIntPtrConstant(40); 3614 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3615 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 3616 false, false, 0); 3617 } 3618 3619 // On Darwin, R12 must contain the address of an indirect callee. This does 3620 // not mean the MTCTR instruction must use R12; it's easier to model this as 3621 // an extra parameter, so do that. 3622 if (!isTailCall && 3623 !dyn_cast<GlobalAddressSDNode>(Callee) && 3624 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3625 !isBLACompatibleAddress(Callee, DAG)) 3626 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 3627 PPC::R12), Callee)); 3628 3629 // Build a sequence of copy-to-reg nodes chained together with token chain 3630 // and flag operands which copy the outgoing args into the appropriate regs. 3631 SDValue InFlag; 3632 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3633 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3634 RegsToPass[i].second, InFlag); 3635 InFlag = Chain.getValue(1); 3636 } 3637 3638 if (isTailCall) 3639 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3640 FPOp, true, TailCallArguments); 3641 3642 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3643 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3644 Ins, InVals); 3645} 3646 3647bool 3648PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3649 MachineFunction &MF, bool isVarArg, 3650 const SmallVectorImpl<ISD::OutputArg> &Outs, 3651 LLVMContext &Context) const { 3652 SmallVector<CCValAssign, 16> RVLocs; 3653 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 3654 RVLocs, Context); 3655 return CCInfo.CheckReturn(Outs, RetCC_PPC); 3656} 3657 3658SDValue 3659PPCTargetLowering::LowerReturn(SDValue Chain, 3660 CallingConv::ID CallConv, bool isVarArg, 3661 const SmallVectorImpl<ISD::OutputArg> &Outs, 3662 const SmallVectorImpl<SDValue> &OutVals, 3663 DebugLoc dl, SelectionDAG &DAG) const { 3664 3665 SmallVector<CCValAssign, 16> RVLocs; 3666 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3667 getTargetMachine(), RVLocs, *DAG.getContext()); 3668 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3669 3670 // If this is the first return lowered for this function, add the regs to the 3671 // liveout set for the function. 3672 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3673 for (unsigned i = 0; i != RVLocs.size(); ++i) 3674 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3675 } 3676 3677 SDValue Flag; 3678 3679 // Copy the result values into the output registers. 3680 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3681 CCValAssign &VA = RVLocs[i]; 3682 assert(VA.isRegLoc() && "Can only return in registers!"); 3683 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3684 OutVals[i], Flag); 3685 Flag = Chain.getValue(1); 3686 } 3687 3688 if (Flag.getNode()) 3689 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3690 else 3691 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3692} 3693 3694SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3695 const PPCSubtarget &Subtarget) const { 3696 // When we pop the dynamic allocation we need to restore the SP link. 3697 DebugLoc dl = Op.getDebugLoc(); 3698 3699 // Get the corect type for pointers. 3700 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3701 3702 // Construct the stack pointer operand. 3703 bool isPPC64 = Subtarget.isPPC64(); 3704 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3705 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3706 3707 // Get the operands for the STACKRESTORE. 3708 SDValue Chain = Op.getOperand(0); 3709 SDValue SaveSP = Op.getOperand(1); 3710 3711 // Load the old link SP. 3712 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 3713 MachinePointerInfo(), 3714 false, false, false, 0); 3715 3716 // Restore the stack pointer. 3717 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3718 3719 // Store the old link SP. 3720 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 3721 false, false, 0); 3722} 3723 3724 3725 3726SDValue 3727PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3728 MachineFunction &MF = DAG.getMachineFunction(); 3729 bool isPPC64 = PPCSubTarget.isPPC64(); 3730 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3731 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3732 3733 // Get current frame pointer save index. The users of this index will be 3734 // primarily DYNALLOC instructions. 3735 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3736 int RASI = FI->getReturnAddrSaveIndex(); 3737 3738 // If the frame pointer save index hasn't been defined yet. 3739 if (!RASI) { 3740 // Find out what the fix offset of the frame pointer save area. 3741 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 3742 // Allocate the frame index for frame pointer save area. 3743 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 3744 // Save the result. 3745 FI->setReturnAddrSaveIndex(RASI); 3746 } 3747 return DAG.getFrameIndex(RASI, PtrVT); 3748} 3749 3750SDValue 3751PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3752 MachineFunction &MF = DAG.getMachineFunction(); 3753 bool isPPC64 = PPCSubTarget.isPPC64(); 3754 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3755 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3756 3757 // Get current frame pointer save index. The users of this index will be 3758 // primarily DYNALLOC instructions. 3759 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3760 int FPSI = FI->getFramePointerSaveIndex(); 3761 3762 // If the frame pointer save index hasn't been defined yet. 3763 if (!FPSI) { 3764 // Find out what the fix offset of the frame pointer save area. 3765 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 3766 isDarwinABI); 3767 3768 // Allocate the frame index for frame pointer save area. 3769 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 3770 // Save the result. 3771 FI->setFramePointerSaveIndex(FPSI); 3772 } 3773 return DAG.getFrameIndex(FPSI, PtrVT); 3774} 3775 3776SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3777 SelectionDAG &DAG, 3778 const PPCSubtarget &Subtarget) const { 3779 // Get the inputs. 3780 SDValue Chain = Op.getOperand(0); 3781 SDValue Size = Op.getOperand(1); 3782 DebugLoc dl = Op.getDebugLoc(); 3783 3784 // Get the corect type for pointers. 3785 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3786 // Negate the size. 3787 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3788 DAG.getConstant(0, PtrVT), Size); 3789 // Construct a node for the frame pointer save index. 3790 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3791 // Build a DYNALLOC node. 3792 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3793 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3794 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3795} 3796 3797/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3798/// possible. 3799SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 3800 // Not FP? Not a fsel. 3801 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3802 !Op.getOperand(2).getValueType().isFloatingPoint()) 3803 return Op; 3804 3805 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3806 3807 // Cannot handle SETEQ/SETNE. 3808 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3809 3810 EVT ResVT = Op.getValueType(); 3811 EVT CmpVT = Op.getOperand(0).getValueType(); 3812 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3813 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3814 DebugLoc dl = Op.getDebugLoc(); 3815 3816 // If the RHS of the comparison is a 0.0, we don't need to do the 3817 // subtraction at all. 3818 if (isFloatingPointZero(RHS)) 3819 switch (CC) { 3820 default: break; // SETUO etc aren't handled by fsel. 3821 case ISD::SETULT: 3822 case ISD::SETLT: 3823 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3824 case ISD::SETOGE: 3825 case ISD::SETGE: 3826 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3827 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3828 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3829 case ISD::SETUGT: 3830 case ISD::SETGT: 3831 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3832 case ISD::SETOLE: 3833 case ISD::SETLE: 3834 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3835 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3836 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3837 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3838 } 3839 3840 SDValue Cmp; 3841 switch (CC) { 3842 default: break; // SETUO etc aren't handled by fsel. 3843 case ISD::SETULT: 3844 case ISD::SETLT: 3845 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3846 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3847 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3848 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3849 case ISD::SETOGE: 3850 case ISD::SETGE: 3851 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3852 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3853 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3854 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3855 case ISD::SETUGT: 3856 case ISD::SETGT: 3857 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3858 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3859 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3860 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3861 case ISD::SETOLE: 3862 case ISD::SETLE: 3863 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3864 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3865 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3866 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3867 } 3868 return Op; 3869} 3870 3871// FIXME: Split this code up when LegalizeDAGTypes lands. 3872SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3873 DebugLoc dl) const { 3874 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3875 SDValue Src = Op.getOperand(0); 3876 if (Src.getValueType() == MVT::f32) 3877 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3878 3879 SDValue Tmp; 3880 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3881 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3882 case MVT::i32: 3883 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3884 PPCISD::FCTIDZ, 3885 dl, MVT::f64, Src); 3886 break; 3887 case MVT::i64: 3888 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3889 break; 3890 } 3891 3892 // Convert the FP value to an int value through memory. 3893 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3894 3895 // Emit a store to the stack slot. 3896 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 3897 MachinePointerInfo(), false, false, 0); 3898 3899 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3900 // add in a bias. 3901 if (Op.getValueType() == MVT::i32) 3902 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3903 DAG.getConstant(4, FIPtr.getValueType())); 3904 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 3905 false, false, false, 0); 3906} 3907 3908SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 3909 SelectionDAG &DAG) const { 3910 DebugLoc dl = Op.getDebugLoc(); 3911 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3912 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3913 return SDValue(); 3914 3915 if (Op.getOperand(0).getValueType() == MVT::i64) { 3916 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0)); 3917 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3918 if (Op.getValueType() == MVT::f32) 3919 FP = DAG.getNode(ISD::FP_ROUND, dl, 3920 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3921 return FP; 3922 } 3923 3924 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3925 "Unhandled SINT_TO_FP type in custom expander!"); 3926 // Since we only generate this in 64-bit mode, we can take advantage of 3927 // 64-bit registers. In particular, sign extend the input value into the 3928 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3929 // then lfd it and fcfid it. 3930 MachineFunction &MF = DAG.getMachineFunction(); 3931 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3932 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3933 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3934 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3935 3936 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3937 Op.getOperand(0)); 3938 3939 // STD the extended value into the stack slot. 3940 MachineMemOperand *MMO = 3941 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 3942 MachineMemOperand::MOStore, 8, 8); 3943 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3944 SDValue Store = 3945 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3946 Ops, 4, MVT::i64, MMO); 3947 // Load the value as a double. 3948 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 3949 false, false, false, 0); 3950 3951 // FCFID it and return it. 3952 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3953 if (Op.getValueType() == MVT::f32) 3954 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3955 return FP; 3956} 3957 3958SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3959 SelectionDAG &DAG) const { 3960 DebugLoc dl = Op.getDebugLoc(); 3961 /* 3962 The rounding mode is in bits 30:31 of FPSR, and has the following 3963 settings: 3964 00 Round to nearest 3965 01 Round to 0 3966 10 Round to +inf 3967 11 Round to -inf 3968 3969 FLT_ROUNDS, on the other hand, expects the following: 3970 -1 Undefined 3971 0 Round to 0 3972 1 Round to nearest 3973 2 Round to +inf 3974 3 Round to -inf 3975 3976 To perform the conversion, we do: 3977 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3978 */ 3979 3980 MachineFunction &MF = DAG.getMachineFunction(); 3981 EVT VT = Op.getValueType(); 3982 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3983 std::vector<EVT> NodeTys; 3984 SDValue MFFSreg, InFlag; 3985 3986 // Save FP Control Word to register 3987 NodeTys.push_back(MVT::f64); // return register 3988 NodeTys.push_back(MVT::Glue); // unused in this context 3989 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3990 3991 // Save FP register to stack slot 3992 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3993 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3994 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3995 StackSlot, MachinePointerInfo(), false, false,0); 3996 3997 // Load FP Control Word from low 32 bits of stack slot. 3998 SDValue Four = DAG.getConstant(4, PtrVT); 3999 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 4000 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 4001 false, false, false, 0); 4002 4003 // Transform as necessary 4004 SDValue CWD1 = 4005 DAG.getNode(ISD::AND, dl, MVT::i32, 4006 CWD, DAG.getConstant(3, MVT::i32)); 4007 SDValue CWD2 = 4008 DAG.getNode(ISD::SRL, dl, MVT::i32, 4009 DAG.getNode(ISD::AND, dl, MVT::i32, 4010 DAG.getNode(ISD::XOR, dl, MVT::i32, 4011 CWD, DAG.getConstant(3, MVT::i32)), 4012 DAG.getConstant(3, MVT::i32)), 4013 DAG.getConstant(1, MVT::i32)); 4014 4015 SDValue RetVal = 4016 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 4017 4018 return DAG.getNode((VT.getSizeInBits() < 16 ? 4019 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 4020} 4021 4022SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4023 EVT VT = Op.getValueType(); 4024 unsigned BitWidth = VT.getSizeInBits(); 4025 DebugLoc dl = Op.getDebugLoc(); 4026 assert(Op.getNumOperands() == 3 && 4027 VT == Op.getOperand(1).getValueType() && 4028 "Unexpected SHL!"); 4029 4030 // Expand into a bunch of logical ops. Note that these ops 4031 // depend on the PPC behavior for oversized shift amounts. 4032 SDValue Lo = Op.getOperand(0); 4033 SDValue Hi = Op.getOperand(1); 4034 SDValue Amt = Op.getOperand(2); 4035 EVT AmtVT = Amt.getValueType(); 4036 4037 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4038 DAG.getConstant(BitWidth, AmtVT), Amt); 4039 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 4040 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 4041 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 4042 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4043 DAG.getConstant(-BitWidth, AmtVT)); 4044 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 4045 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4046 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 4047 SDValue OutOps[] = { OutLo, OutHi }; 4048 return DAG.getMergeValues(OutOps, 2, dl); 4049} 4050 4051SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4052 EVT VT = Op.getValueType(); 4053 DebugLoc dl = Op.getDebugLoc(); 4054 unsigned BitWidth = VT.getSizeInBits(); 4055 assert(Op.getNumOperands() == 3 && 4056 VT == Op.getOperand(1).getValueType() && 4057 "Unexpected SRL!"); 4058 4059 // Expand into a bunch of logical ops. Note that these ops 4060 // depend on the PPC behavior for oversized shift amounts. 4061 SDValue Lo = Op.getOperand(0); 4062 SDValue Hi = Op.getOperand(1); 4063 SDValue Amt = Op.getOperand(2); 4064 EVT AmtVT = Amt.getValueType(); 4065 4066 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4067 DAG.getConstant(BitWidth, AmtVT), Amt); 4068 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4069 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4070 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4071 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4072 DAG.getConstant(-BitWidth, AmtVT)); 4073 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 4074 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4075 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 4076 SDValue OutOps[] = { OutLo, OutHi }; 4077 return DAG.getMergeValues(OutOps, 2, dl); 4078} 4079 4080SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 4081 DebugLoc dl = Op.getDebugLoc(); 4082 EVT VT = Op.getValueType(); 4083 unsigned BitWidth = VT.getSizeInBits(); 4084 assert(Op.getNumOperands() == 3 && 4085 VT == Op.getOperand(1).getValueType() && 4086 "Unexpected SRA!"); 4087 4088 // Expand into a bunch of logical ops, followed by a select_cc. 4089 SDValue Lo = Op.getOperand(0); 4090 SDValue Hi = Op.getOperand(1); 4091 SDValue Amt = Op.getOperand(2); 4092 EVT AmtVT = Amt.getValueType(); 4093 4094 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4095 DAG.getConstant(BitWidth, AmtVT), Amt); 4096 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4097 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4098 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4099 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4100 DAG.getConstant(-BitWidth, AmtVT)); 4101 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 4102 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 4103 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 4104 Tmp4, Tmp6, ISD::SETLE); 4105 SDValue OutOps[] = { OutLo, OutHi }; 4106 return DAG.getMergeValues(OutOps, 2, dl); 4107} 4108 4109//===----------------------------------------------------------------------===// 4110// Vector related lowering. 4111// 4112 4113/// BuildSplatI - Build a canonical splati of Val with an element size of 4114/// SplatSize. Cast the result to VT. 4115static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 4116 SelectionDAG &DAG, DebugLoc dl) { 4117 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 4118 4119 static const EVT VTys[] = { // canonical VT to use for each size. 4120 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 4121 }; 4122 4123 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 4124 4125 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 4126 if (Val == -1) 4127 SplatSize = 1; 4128 4129 EVT CanonicalVT = VTys[SplatSize-1]; 4130 4131 // Build a canonical splat for this value. 4132 SDValue Elt = DAG.getConstant(Val, MVT::i32); 4133 SmallVector<SDValue, 8> Ops; 4134 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 4135 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 4136 &Ops[0], Ops.size()); 4137 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 4138} 4139 4140/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 4141/// specified intrinsic ID. 4142static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 4143 SelectionDAG &DAG, DebugLoc dl, 4144 EVT DestVT = MVT::Other) { 4145 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 4146 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4147 DAG.getConstant(IID, MVT::i32), LHS, RHS); 4148} 4149 4150/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 4151/// specified intrinsic ID. 4152static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 4153 SDValue Op2, SelectionDAG &DAG, 4154 DebugLoc dl, EVT DestVT = MVT::Other) { 4155 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 4156 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4157 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 4158} 4159 4160 4161/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 4162/// amount. The result has the specified value type. 4163static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 4164 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 4165 // Force LHS/RHS to be the right type. 4166 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 4167 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 4168 4169 int Ops[16]; 4170 for (unsigned i = 0; i != 16; ++i) 4171 Ops[i] = i + Amt; 4172 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 4173 return DAG.getNode(ISD::BITCAST, dl, VT, T); 4174} 4175 4176// If this is a case we can't handle, return null and let the default 4177// expansion code take care of it. If we CAN select this case, and if it 4178// selects to a single instruction, return Op. Otherwise, if we can codegen 4179// this case more efficiently than a constant pool load, lower it to the 4180// sequence of ops that should be used. 4181SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 4182 SelectionDAG &DAG) const { 4183 DebugLoc dl = Op.getDebugLoc(); 4184 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 4185 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 4186 4187 // Check if this is a splat of a constant value. 4188 APInt APSplatBits, APSplatUndef; 4189 unsigned SplatBitSize; 4190 bool HasAnyUndefs; 4191 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 4192 HasAnyUndefs, 0, true) || SplatBitSize > 32) 4193 return SDValue(); 4194 4195 unsigned SplatBits = APSplatBits.getZExtValue(); 4196 unsigned SplatUndef = APSplatUndef.getZExtValue(); 4197 unsigned SplatSize = SplatBitSize / 8; 4198 4199 // First, handle single instruction cases. 4200 4201 // All zeros? 4202 if (SplatBits == 0) { 4203 // Canonicalize all zero vectors to be v4i32. 4204 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 4205 SDValue Z = DAG.getConstant(0, MVT::i32); 4206 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 4207 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 4208 } 4209 return Op; 4210 } 4211 4212 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 4213 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 4214 (32-SplatBitSize)); 4215 if (SextVal >= -16 && SextVal <= 15) 4216 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 4217 4218 4219 // Two instruction sequences. 4220 4221 // If this value is in the range [-32,30] and is even, use: 4222 // tmp = VSPLTI[bhw], result = add tmp, tmp 4223 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 4224 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 4225 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 4226 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4227 } 4228 4229 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 4230 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 4231 // for fneg/fabs. 4232 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 4233 // Make -1 and vspltisw -1: 4234 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 4235 4236 // Make the VSLW intrinsic, computing 0x8000_0000. 4237 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 4238 OnesV, DAG, dl); 4239 4240 // xor by OnesV to invert it. 4241 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 4242 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4243 } 4244 4245 // Check to see if this is a wide variety of vsplti*, binop self cases. 4246 static const signed char SplatCsts[] = { 4247 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 4248 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 4249 }; 4250 4251 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 4252 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 4253 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 4254 int i = SplatCsts[idx]; 4255 4256 // Figure out what shift amount will be used by altivec if shifted by i in 4257 // this splat size. 4258 unsigned TypeShiftAmt = i & (SplatBitSize-1); 4259 4260 // vsplti + shl self. 4261 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) { 4262 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4263 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4264 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 4265 Intrinsic::ppc_altivec_vslw 4266 }; 4267 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4268 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4269 } 4270 4271 // vsplti + srl self. 4272 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 4273 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4274 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4275 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 4276 Intrinsic::ppc_altivec_vsrw 4277 }; 4278 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4279 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4280 } 4281 4282 // vsplti + sra self. 4283 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 4284 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4285 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4286 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 4287 Intrinsic::ppc_altivec_vsraw 4288 }; 4289 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4290 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4291 } 4292 4293 // vsplti + rol self. 4294 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 4295 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 4296 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4297 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4298 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 4299 Intrinsic::ppc_altivec_vrlw 4300 }; 4301 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4302 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4303 } 4304 4305 // t = vsplti c, result = vsldoi t, t, 1 4306 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) { 4307 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4308 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 4309 } 4310 // t = vsplti c, result = vsldoi t, t, 2 4311 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) { 4312 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4313 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 4314 } 4315 // t = vsplti c, result = vsldoi t, t, 3 4316 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 4317 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4318 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 4319 } 4320 } 4321 4322 // Three instruction sequences. 4323 4324 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 4325 if (SextVal >= 0 && SextVal <= 31) { 4326 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 4327 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 4328 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 4329 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 4330 } 4331 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 4332 if (SextVal >= -31 && SextVal <= 0) { 4333 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 4334 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 4335 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 4336 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 4337 } 4338 4339 return SDValue(); 4340} 4341 4342/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4343/// the specified operations to build the shuffle. 4344static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4345 SDValue RHS, SelectionDAG &DAG, 4346 DebugLoc dl) { 4347 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4348 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4349 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4350 4351 enum { 4352 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4353 OP_VMRGHW, 4354 OP_VMRGLW, 4355 OP_VSPLTISW0, 4356 OP_VSPLTISW1, 4357 OP_VSPLTISW2, 4358 OP_VSPLTISW3, 4359 OP_VSLDOI4, 4360 OP_VSLDOI8, 4361 OP_VSLDOI12 4362 }; 4363 4364 if (OpNum == OP_COPY) { 4365 if (LHSID == (1*9+2)*9+3) return LHS; 4366 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4367 return RHS; 4368 } 4369 4370 SDValue OpLHS, OpRHS; 4371 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4372 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4373 4374 int ShufIdxs[16]; 4375 switch (OpNum) { 4376 default: llvm_unreachable("Unknown i32 permute!"); 4377 case OP_VMRGHW: 4378 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 4379 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 4380 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 4381 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 4382 break; 4383 case OP_VMRGLW: 4384 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 4385 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 4386 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 4387 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 4388 break; 4389 case OP_VSPLTISW0: 4390 for (unsigned i = 0; i != 16; ++i) 4391 ShufIdxs[i] = (i&3)+0; 4392 break; 4393 case OP_VSPLTISW1: 4394 for (unsigned i = 0; i != 16; ++i) 4395 ShufIdxs[i] = (i&3)+4; 4396 break; 4397 case OP_VSPLTISW2: 4398 for (unsigned i = 0; i != 16; ++i) 4399 ShufIdxs[i] = (i&3)+8; 4400 break; 4401 case OP_VSPLTISW3: 4402 for (unsigned i = 0; i != 16; ++i) 4403 ShufIdxs[i] = (i&3)+12; 4404 break; 4405 case OP_VSLDOI4: 4406 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 4407 case OP_VSLDOI8: 4408 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 4409 case OP_VSLDOI12: 4410 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 4411 } 4412 EVT VT = OpLHS.getValueType(); 4413 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 4414 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 4415 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4416 return DAG.getNode(ISD::BITCAST, dl, VT, T); 4417} 4418 4419/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4420/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4421/// return the code it can be lowered into. Worst case, it can always be 4422/// lowered into a vperm. 4423SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4424 SelectionDAG &DAG) const { 4425 DebugLoc dl = Op.getDebugLoc(); 4426 SDValue V1 = Op.getOperand(0); 4427 SDValue V2 = Op.getOperand(1); 4428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4429 EVT VT = Op.getValueType(); 4430 4431 // Cases that are handled by instructions that take permute immediates 4432 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4433 // selected by the instruction selector. 4434 if (V2.getOpcode() == ISD::UNDEF) { 4435 if (PPC::isSplatShuffleMask(SVOp, 1) || 4436 PPC::isSplatShuffleMask(SVOp, 2) || 4437 PPC::isSplatShuffleMask(SVOp, 4) || 4438 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4439 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4440 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4441 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4442 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4443 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4444 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4445 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4446 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4447 return Op; 4448 } 4449 } 4450 4451 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4452 // and produce a fixed permutation. If any of these match, do not lower to 4453 // VPERM. 4454 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4455 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4456 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4457 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4458 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4459 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4460 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4461 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4462 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4463 return Op; 4464 4465 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4466 // perfect shuffle table to emit an optimal matching sequence. 4467 ArrayRef<int> PermMask = SVOp->getMask(); 4468 4469 unsigned PFIndexes[4]; 4470 bool isFourElementShuffle = true; 4471 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4472 unsigned EltNo = 8; // Start out undef. 4473 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4474 if (PermMask[i*4+j] < 0) 4475 continue; // Undef, ignore it. 4476 4477 unsigned ByteSource = PermMask[i*4+j]; 4478 if ((ByteSource & 3) != j) { 4479 isFourElementShuffle = false; 4480 break; 4481 } 4482 4483 if (EltNo == 8) { 4484 EltNo = ByteSource/4; 4485 } else if (EltNo != ByteSource/4) { 4486 isFourElementShuffle = false; 4487 break; 4488 } 4489 } 4490 PFIndexes[i] = EltNo; 4491 } 4492 4493 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4494 // perfect shuffle vector to determine if it is cost effective to do this as 4495 // discrete instructions, or whether we should use a vperm. 4496 if (isFourElementShuffle) { 4497 // Compute the index in the perfect shuffle table. 4498 unsigned PFTableIndex = 4499 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4500 4501 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4502 unsigned Cost = (PFEntry >> 30); 4503 4504 // Determining when to avoid vperm is tricky. Many things affect the cost 4505 // of vperm, particularly how many times the perm mask needs to be computed. 4506 // For example, if the perm mask can be hoisted out of a loop or is already 4507 // used (perhaps because there are multiple permutes with the same shuffle 4508 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4509 // the loop requires an extra register. 4510 // 4511 // As a compromise, we only emit discrete instructions if the shuffle can be 4512 // generated in 3 or fewer operations. When we have loop information 4513 // available, if this block is within a loop, we should avoid using vperm 4514 // for 3-operation perms and use a constant pool load instead. 4515 if (Cost < 3) 4516 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4517 } 4518 4519 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4520 // vector that will get spilled to the constant pool. 4521 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4522 4523 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4524 // that it is in input element units, not in bytes. Convert now. 4525 EVT EltVT = V1.getValueType().getVectorElementType(); 4526 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4527 4528 SmallVector<SDValue, 16> ResultMask; 4529 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4530 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4531 4532 for (unsigned j = 0; j != BytesPerElement; ++j) 4533 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4534 MVT::i32)); 4535 } 4536 4537 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4538 &ResultMask[0], ResultMask.size()); 4539 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4540} 4541 4542/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4543/// altivec comparison. If it is, return true and fill in Opc/isDot with 4544/// information about the intrinsic. 4545static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4546 bool &isDot) { 4547 unsigned IntrinsicID = 4548 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4549 CompareOpc = -1; 4550 isDot = false; 4551 switch (IntrinsicID) { 4552 default: return false; 4553 // Comparison predicates. 4554 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4555 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4556 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4557 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4558 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4559 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4560 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4561 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4562 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4563 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4564 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4565 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4566 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4567 4568 // Normal Comparisons. 4569 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4570 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4571 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4572 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4573 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4574 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4575 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4576 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4577 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4578 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4579 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4580 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4581 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4582 } 4583 return true; 4584} 4585 4586/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4587/// lower, do it, otherwise return null. 4588SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4589 SelectionDAG &DAG) const { 4590 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4591 // opcode number of the comparison. 4592 DebugLoc dl = Op.getDebugLoc(); 4593 int CompareOpc; 4594 bool isDot; 4595 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4596 return SDValue(); // Don't custom lower most intrinsics. 4597 4598 // If this is a non-dot comparison, make the VCMP node and we are done. 4599 if (!isDot) { 4600 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4601 Op.getOperand(1), Op.getOperand(2), 4602 DAG.getConstant(CompareOpc, MVT::i32)); 4603 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 4604 } 4605 4606 // Create the PPCISD altivec 'dot' comparison node. 4607 SDValue Ops[] = { 4608 Op.getOperand(2), // LHS 4609 Op.getOperand(3), // RHS 4610 DAG.getConstant(CompareOpc, MVT::i32) 4611 }; 4612 std::vector<EVT> VTs; 4613 VTs.push_back(Op.getOperand(2).getValueType()); 4614 VTs.push_back(MVT::Glue); 4615 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4616 4617 // Now that we have the comparison, emit a copy from the CR to a GPR. 4618 // This is flagged to the above dot comparison. 4619 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4620 DAG.getRegister(PPC::CR6, MVT::i32), 4621 CompNode.getValue(1)); 4622 4623 // Unpack the result based on how the target uses it. 4624 unsigned BitNo; // Bit # of CR6. 4625 bool InvertBit; // Invert result? 4626 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4627 default: // Can't happen, don't crash on invalid number though. 4628 case 0: // Return the value of the EQ bit of CR6. 4629 BitNo = 0; InvertBit = false; 4630 break; 4631 case 1: // Return the inverted value of the EQ bit of CR6. 4632 BitNo = 0; InvertBit = true; 4633 break; 4634 case 2: // Return the value of the LT bit of CR6. 4635 BitNo = 2; InvertBit = false; 4636 break; 4637 case 3: // Return the inverted value of the LT bit of CR6. 4638 BitNo = 2; InvertBit = true; 4639 break; 4640 } 4641 4642 // Shift the bit into the low position. 4643 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4644 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4645 // Isolate the bit. 4646 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4647 DAG.getConstant(1, MVT::i32)); 4648 4649 // If we are supposed to, toggle the bit. 4650 if (InvertBit) 4651 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4652 DAG.getConstant(1, MVT::i32)); 4653 return Flags; 4654} 4655 4656SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4657 SelectionDAG &DAG) const { 4658 DebugLoc dl = Op.getDebugLoc(); 4659 // Create a stack slot that is 16-byte aligned. 4660 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4661 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4662 EVT PtrVT = getPointerTy(); 4663 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4664 4665 // Store the input value into Value#0 of the stack slot. 4666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4667 Op.getOperand(0), FIdx, MachinePointerInfo(), 4668 false, false, 0); 4669 // Load it out. 4670 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 4671 false, false, false, 0); 4672} 4673 4674SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 4675 DebugLoc dl = Op.getDebugLoc(); 4676 if (Op.getValueType() == MVT::v4i32) { 4677 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4678 4679 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4680 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4681 4682 SDValue RHSSwap = // = vrlw RHS, 16 4683 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4684 4685 // Shrinkify inputs to v8i16. 4686 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 4687 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 4688 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 4689 4690 // Low parts multiplied together, generating 32-bit results (we ignore the 4691 // top parts). 4692 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4693 LHS, RHS, DAG, dl, MVT::v4i32); 4694 4695 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4696 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4697 // Shift the high parts up 16 bits. 4698 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4699 Neg16, DAG, dl); 4700 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4701 } else if (Op.getValueType() == MVT::v8i16) { 4702 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4703 4704 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4705 4706 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4707 LHS, RHS, Zero, DAG, dl); 4708 } else if (Op.getValueType() == MVT::v16i8) { 4709 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4710 4711 // Multiply the even 8-bit parts, producing 16-bit sums. 4712 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4713 LHS, RHS, DAG, dl, MVT::v8i16); 4714 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 4715 4716 // Multiply the odd 8-bit parts, producing 16-bit sums. 4717 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4718 LHS, RHS, DAG, dl, MVT::v8i16); 4719 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 4720 4721 // Merge the results together. 4722 int Ops[16]; 4723 for (unsigned i = 0; i != 8; ++i) { 4724 Ops[i*2 ] = 2*i+1; 4725 Ops[i*2+1] = 2*i+1+16; 4726 } 4727 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4728 } else { 4729 llvm_unreachable("Unknown mul to lower!"); 4730 } 4731} 4732 4733/// LowerOperation - Provide custom lowering hooks for some operations. 4734/// 4735SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4736 switch (Op.getOpcode()) { 4737 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4738 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4739 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4740 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4741 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4742 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4743 case ISD::SETCC: return LowerSETCC(Op, DAG); 4744 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 4745 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 4746 case ISD::VASTART: 4747 return LowerVASTART(Op, DAG, PPCSubTarget); 4748 4749 case ISD::VAARG: 4750 return LowerVAARG(Op, DAG, PPCSubTarget); 4751 4752 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4753 case ISD::DYNAMIC_STACKALLOC: 4754 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4755 4756 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4757 case ISD::FP_TO_UINT: 4758 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4759 Op.getDebugLoc()); 4760 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4761 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4762 4763 // Lower 64-bit shifts. 4764 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4765 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4766 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4767 4768 // Vector-related lowering. 4769 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4770 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4771 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4772 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4773 case ISD::MUL: return LowerMUL(Op, DAG); 4774 4775 // Frame & Return address. 4776 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4777 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4778 } 4779} 4780 4781void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4782 SmallVectorImpl<SDValue>&Results, 4783 SelectionDAG &DAG) const { 4784 const TargetMachine &TM = getTargetMachine(); 4785 DebugLoc dl = N->getDebugLoc(); 4786 switch (N->getOpcode()) { 4787 default: 4788 llvm_unreachable("Do not know how to custom type legalize this operation!"); 4789 case ISD::VAARG: { 4790 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 4791 || TM.getSubtarget<PPCSubtarget>().isPPC64()) 4792 return; 4793 4794 EVT VT = N->getValueType(0); 4795 4796 if (VT == MVT::i64) { 4797 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); 4798 4799 Results.push_back(NewNode); 4800 Results.push_back(NewNode.getValue(1)); 4801 } 4802 return; 4803 } 4804 case ISD::FP_ROUND_INREG: { 4805 assert(N->getValueType(0) == MVT::ppcf128); 4806 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4807 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4808 MVT::f64, N->getOperand(0), 4809 DAG.getIntPtrConstant(0)); 4810 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4811 MVT::f64, N->getOperand(0), 4812 DAG.getIntPtrConstant(1)); 4813 4814 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4815 // of the long double, and puts FPSCR back the way it was. We do not 4816 // actually model FPSCR. 4817 std::vector<EVT> NodeTys; 4818 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4819 4820 NodeTys.push_back(MVT::f64); // Return register 4821 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns 4822 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4823 MFFSreg = Result.getValue(0); 4824 InFlag = Result.getValue(1); 4825 4826 NodeTys.clear(); 4827 NodeTys.push_back(MVT::Glue); // Returns a flag 4828 Ops[0] = DAG.getConstant(31, MVT::i32); 4829 Ops[1] = InFlag; 4830 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4831 InFlag = Result.getValue(0); 4832 4833 NodeTys.clear(); 4834 NodeTys.push_back(MVT::Glue); // Returns a flag 4835 Ops[0] = DAG.getConstant(30, MVT::i32); 4836 Ops[1] = InFlag; 4837 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4838 InFlag = Result.getValue(0); 4839 4840 NodeTys.clear(); 4841 NodeTys.push_back(MVT::f64); // result of add 4842 NodeTys.push_back(MVT::Glue); // Returns a flag 4843 Ops[0] = Lo; 4844 Ops[1] = Hi; 4845 Ops[2] = InFlag; 4846 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4847 FPreg = Result.getValue(0); 4848 InFlag = Result.getValue(1); 4849 4850 NodeTys.clear(); 4851 NodeTys.push_back(MVT::f64); 4852 Ops[0] = DAG.getConstant(1, MVT::i32); 4853 Ops[1] = MFFSreg; 4854 Ops[2] = FPreg; 4855 Ops[3] = InFlag; 4856 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4857 FPreg = Result.getValue(0); 4858 4859 // We know the low half is about to be thrown away, so just use something 4860 // convenient. 4861 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4862 FPreg, FPreg)); 4863 return; 4864 } 4865 case ISD::FP_TO_SINT: 4866 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4867 return; 4868 } 4869} 4870 4871 4872//===----------------------------------------------------------------------===// 4873// Other Lowering Code 4874//===----------------------------------------------------------------------===// 4875 4876MachineBasicBlock * 4877PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4878 bool is64bit, unsigned BinOpcode) const { 4879 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4880 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4881 4882 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4883 MachineFunction *F = BB->getParent(); 4884 MachineFunction::iterator It = BB; 4885 ++It; 4886 4887 unsigned dest = MI->getOperand(0).getReg(); 4888 unsigned ptrA = MI->getOperand(1).getReg(); 4889 unsigned ptrB = MI->getOperand(2).getReg(); 4890 unsigned incr = MI->getOperand(3).getReg(); 4891 DebugLoc dl = MI->getDebugLoc(); 4892 4893 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4894 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4895 F->insert(It, loopMBB); 4896 F->insert(It, exitMBB); 4897 exitMBB->splice(exitMBB->begin(), BB, 4898 llvm::next(MachineBasicBlock::iterator(MI)), 4899 BB->end()); 4900 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4901 4902 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4903 unsigned TmpReg = (!BinOpcode) ? incr : 4904 RegInfo.createVirtualRegister( 4905 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4906 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4907 4908 // thisMBB: 4909 // ... 4910 // fallthrough --> loopMBB 4911 BB->addSuccessor(loopMBB); 4912 4913 // loopMBB: 4914 // l[wd]arx dest, ptr 4915 // add r0, dest, incr 4916 // st[wd]cx. r0, ptr 4917 // bne- loopMBB 4918 // fallthrough --> exitMBB 4919 BB = loopMBB; 4920 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4921 .addReg(ptrA).addReg(ptrB); 4922 if (BinOpcode) 4923 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4924 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4925 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4926 BuildMI(BB, dl, TII->get(PPC::BCC)) 4927 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4928 BB->addSuccessor(loopMBB); 4929 BB->addSuccessor(exitMBB); 4930 4931 // exitMBB: 4932 // ... 4933 BB = exitMBB; 4934 return BB; 4935} 4936 4937MachineBasicBlock * 4938PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4939 MachineBasicBlock *BB, 4940 bool is8bit, // operation 4941 unsigned BinOpcode) const { 4942 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4943 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4944 // In 64 bit mode we have to use 64 bits for addresses, even though the 4945 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4946 // registers without caring whether they're 32 or 64, but here we're 4947 // doing actual arithmetic on the addresses. 4948 bool is64bit = PPCSubTarget.isPPC64(); 4949 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 4950 4951 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4952 MachineFunction *F = BB->getParent(); 4953 MachineFunction::iterator It = BB; 4954 ++It; 4955 4956 unsigned dest = MI->getOperand(0).getReg(); 4957 unsigned ptrA = MI->getOperand(1).getReg(); 4958 unsigned ptrB = MI->getOperand(2).getReg(); 4959 unsigned incr = MI->getOperand(3).getReg(); 4960 DebugLoc dl = MI->getDebugLoc(); 4961 4962 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4963 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4964 F->insert(It, loopMBB); 4965 F->insert(It, exitMBB); 4966 exitMBB->splice(exitMBB->begin(), BB, 4967 llvm::next(MachineBasicBlock::iterator(MI)), 4968 BB->end()); 4969 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4970 4971 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4972 const TargetRegisterClass *RC = 4973 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4974 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4975 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4976 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4977 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4978 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4979 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4980 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4981 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4982 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4983 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4984 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4985 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4986 unsigned Ptr1Reg; 4987 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4988 4989 // thisMBB: 4990 // ... 4991 // fallthrough --> loopMBB 4992 BB->addSuccessor(loopMBB); 4993 4994 // The 4-byte load must be aligned, while a char or short may be 4995 // anywhere in the word. Hence all this nasty bookkeeping code. 4996 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4997 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4998 // xori shift, shift1, 24 [16] 4999 // rlwinm ptr, ptr1, 0, 0, 29 5000 // slw incr2, incr, shift 5001 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5002 // slw mask, mask2, shift 5003 // loopMBB: 5004 // lwarx tmpDest, ptr 5005 // add tmp, tmpDest, incr2 5006 // andc tmp2, tmpDest, mask 5007 // and tmp3, tmp, mask 5008 // or tmp4, tmp3, tmp2 5009 // stwcx. tmp4, ptr 5010 // bne- loopMBB 5011 // fallthrough --> exitMBB 5012 // srw dest, tmpDest, shift 5013 if (ptrA != ZeroReg) { 5014 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5015 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5016 .addReg(ptrA).addReg(ptrB); 5017 } else { 5018 Ptr1Reg = ptrB; 5019 } 5020 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5021 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5022 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5023 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5024 if (is64bit) 5025 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5026 .addReg(Ptr1Reg).addImm(0).addImm(61); 5027 else 5028 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5029 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5030 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 5031 .addReg(incr).addReg(ShiftReg); 5032 if (is8bit) 5033 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5034 else { 5035 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5036 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 5037 } 5038 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5039 .addReg(Mask2Reg).addReg(ShiftReg); 5040 5041 BB = loopMBB; 5042 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5043 .addReg(ZeroReg).addReg(PtrReg); 5044 if (BinOpcode) 5045 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 5046 .addReg(Incr2Reg).addReg(TmpDestReg); 5047 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 5048 .addReg(TmpDestReg).addReg(MaskReg); 5049 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 5050 .addReg(TmpReg).addReg(MaskReg); 5051 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 5052 .addReg(Tmp3Reg).addReg(Tmp2Reg); 5053 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5054 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 5055 BuildMI(BB, dl, TII->get(PPC::BCC)) 5056 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5057 BB->addSuccessor(loopMBB); 5058 BB->addSuccessor(exitMBB); 5059 5060 // exitMBB: 5061 // ... 5062 BB = exitMBB; 5063 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 5064 .addReg(ShiftReg); 5065 return BB; 5066} 5067 5068MachineBasicBlock * 5069PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5070 MachineBasicBlock *BB) const { 5071 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5072 5073 // To "insert" these instructions we actually have to insert their 5074 // control-flow patterns. 5075 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5076 MachineFunction::iterator It = BB; 5077 ++It; 5078 5079 MachineFunction *F = BB->getParent(); 5080 5081 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 || 5082 MI->getOpcode() == PPC::SELECT_CC_I8)) { 5083 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ? 5084 PPC::ISEL8 : PPC::ISEL; 5085 unsigned SelectPred = MI->getOperand(4).getImm(); 5086 DebugLoc dl = MI->getDebugLoc(); 5087 5088 // The SelectPred is ((BI << 5) | BO) for a BCC 5089 unsigned BO = SelectPred & 0xF; 5090 assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel"); 5091 5092 unsigned TrueOpNo, FalseOpNo; 5093 if (BO == 12) { 5094 TrueOpNo = 2; 5095 FalseOpNo = 3; 5096 } else { 5097 TrueOpNo = 3; 5098 FalseOpNo = 2; 5099 SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred); 5100 } 5101 5102 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg()) 5103 .addReg(MI->getOperand(TrueOpNo).getReg()) 5104 .addReg(MI->getOperand(FalseOpNo).getReg()) 5105 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()); 5106 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 || 5107 MI->getOpcode() == PPC::SELECT_CC_I8 || 5108 MI->getOpcode() == PPC::SELECT_CC_F4 || 5109 MI->getOpcode() == PPC::SELECT_CC_F8 || 5110 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 5111 5112 5113 // The incoming instruction knows the destination vreg to set, the 5114 // condition code register to branch on, the true/false values to 5115 // select between, and a branch opcode to use. 5116 5117 // thisMBB: 5118 // ... 5119 // TrueVal = ... 5120 // cmpTY ccX, r1, r2 5121 // bCC copy1MBB 5122 // fallthrough --> copy0MBB 5123 MachineBasicBlock *thisMBB = BB; 5124 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 5125 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 5126 unsigned SelectPred = MI->getOperand(4).getImm(); 5127 DebugLoc dl = MI->getDebugLoc(); 5128 F->insert(It, copy0MBB); 5129 F->insert(It, sinkMBB); 5130 5131 // Transfer the remainder of BB and its successor edges to sinkMBB. 5132 sinkMBB->splice(sinkMBB->begin(), BB, 5133 llvm::next(MachineBasicBlock::iterator(MI)), 5134 BB->end()); 5135 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 5136 5137 // Next, add the true and fallthrough blocks as its successors. 5138 BB->addSuccessor(copy0MBB); 5139 BB->addSuccessor(sinkMBB); 5140 5141 BuildMI(BB, dl, TII->get(PPC::BCC)) 5142 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 5143 5144 // copy0MBB: 5145 // %FalseValue = ... 5146 // # fallthrough to sinkMBB 5147 BB = copy0MBB; 5148 5149 // Update machine-CFG edges 5150 BB->addSuccessor(sinkMBB); 5151 5152 // sinkMBB: 5153 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 5154 // ... 5155 BB = sinkMBB; 5156 BuildMI(*BB, BB->begin(), dl, 5157 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 5158 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 5159 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 5160 } 5161 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 5162 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 5163 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 5164 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 5165 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 5166 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 5167 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 5168 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 5169 5170 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 5171 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 5172 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 5173 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 5174 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 5175 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 5176 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 5177 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 5178 5179 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 5180 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 5181 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 5182 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 5183 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 5184 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 5185 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 5186 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 5187 5188 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 5189 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 5190 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 5191 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 5192 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 5193 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 5194 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 5195 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 5196 5197 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 5198 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 5199 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 5200 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 5201 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 5202 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 5203 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 5204 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 5205 5206 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 5207 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 5208 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 5209 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 5210 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 5211 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 5212 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 5213 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 5214 5215 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 5216 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 5217 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 5218 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 5219 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 5220 BB = EmitAtomicBinary(MI, BB, false, 0); 5221 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 5222 BB = EmitAtomicBinary(MI, BB, true, 0); 5223 5224 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 5225 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 5226 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 5227 5228 unsigned dest = MI->getOperand(0).getReg(); 5229 unsigned ptrA = MI->getOperand(1).getReg(); 5230 unsigned ptrB = MI->getOperand(2).getReg(); 5231 unsigned oldval = MI->getOperand(3).getReg(); 5232 unsigned newval = MI->getOperand(4).getReg(); 5233 DebugLoc dl = MI->getDebugLoc(); 5234 5235 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 5236 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 5237 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 5238 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5239 F->insert(It, loop1MBB); 5240 F->insert(It, loop2MBB); 5241 F->insert(It, midMBB); 5242 F->insert(It, exitMBB); 5243 exitMBB->splice(exitMBB->begin(), BB, 5244 llvm::next(MachineBasicBlock::iterator(MI)), 5245 BB->end()); 5246 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5247 5248 // thisMBB: 5249 // ... 5250 // fallthrough --> loopMBB 5251 BB->addSuccessor(loop1MBB); 5252 5253 // loop1MBB: 5254 // l[wd]arx dest, ptr 5255 // cmp[wd] dest, oldval 5256 // bne- midMBB 5257 // loop2MBB: 5258 // st[wd]cx. newval, ptr 5259 // bne- loopMBB 5260 // b exitBB 5261 // midMBB: 5262 // st[wd]cx. dest, ptr 5263 // exitBB: 5264 BB = loop1MBB; 5265 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 5266 .addReg(ptrA).addReg(ptrB); 5267 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 5268 .addReg(oldval).addReg(dest); 5269 BuildMI(BB, dl, TII->get(PPC::BCC)) 5270 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5271 BB->addSuccessor(loop2MBB); 5272 BB->addSuccessor(midMBB); 5273 5274 BB = loop2MBB; 5275 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5276 .addReg(newval).addReg(ptrA).addReg(ptrB); 5277 BuildMI(BB, dl, TII->get(PPC::BCC)) 5278 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5279 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5280 BB->addSuccessor(loop1MBB); 5281 BB->addSuccessor(exitMBB); 5282 5283 BB = midMBB; 5284 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5285 .addReg(dest).addReg(ptrA).addReg(ptrB); 5286 BB->addSuccessor(exitMBB); 5287 5288 // exitMBB: 5289 // ... 5290 BB = exitMBB; 5291 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 5292 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 5293 // We must use 64-bit registers for addresses when targeting 64-bit, 5294 // since we're actually doing arithmetic on them. Other registers 5295 // can be 32-bit. 5296 bool is64bit = PPCSubTarget.isPPC64(); 5297 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 5298 5299 unsigned dest = MI->getOperand(0).getReg(); 5300 unsigned ptrA = MI->getOperand(1).getReg(); 5301 unsigned ptrB = MI->getOperand(2).getReg(); 5302 unsigned oldval = MI->getOperand(3).getReg(); 5303 unsigned newval = MI->getOperand(4).getReg(); 5304 DebugLoc dl = MI->getDebugLoc(); 5305 5306 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 5307 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 5308 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 5309 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5310 F->insert(It, loop1MBB); 5311 F->insert(It, loop2MBB); 5312 F->insert(It, midMBB); 5313 F->insert(It, exitMBB); 5314 exitMBB->splice(exitMBB->begin(), BB, 5315 llvm::next(MachineBasicBlock::iterator(MI)), 5316 BB->end()); 5317 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5318 5319 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5320 const TargetRegisterClass *RC = 5321 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5322 (const TargetRegisterClass *) &PPC::GPRCRegClass; 5323 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 5324 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 5325 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 5326 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 5327 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 5328 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 5329 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 5330 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 5331 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 5332 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 5333 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 5334 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 5335 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 5336 unsigned Ptr1Reg; 5337 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 5338 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 5339 // thisMBB: 5340 // ... 5341 // fallthrough --> loopMBB 5342 BB->addSuccessor(loop1MBB); 5343 5344 // The 4-byte load must be aligned, while a char or short may be 5345 // anywhere in the word. Hence all this nasty bookkeeping code. 5346 // add ptr1, ptrA, ptrB [copy if ptrA==0] 5347 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 5348 // xori shift, shift1, 24 [16] 5349 // rlwinm ptr, ptr1, 0, 0, 29 5350 // slw newval2, newval, shift 5351 // slw oldval2, oldval,shift 5352 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5353 // slw mask, mask2, shift 5354 // and newval3, newval2, mask 5355 // and oldval3, oldval2, mask 5356 // loop1MBB: 5357 // lwarx tmpDest, ptr 5358 // and tmp, tmpDest, mask 5359 // cmpw tmp, oldval3 5360 // bne- midMBB 5361 // loop2MBB: 5362 // andc tmp2, tmpDest, mask 5363 // or tmp4, tmp2, newval3 5364 // stwcx. tmp4, ptr 5365 // bne- loop1MBB 5366 // b exitBB 5367 // midMBB: 5368 // stwcx. tmpDest, ptr 5369 // exitBB: 5370 // srw dest, tmpDest, shift 5371 if (ptrA != ZeroReg) { 5372 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5373 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5374 .addReg(ptrA).addReg(ptrB); 5375 } else { 5376 Ptr1Reg = ptrB; 5377 } 5378 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5379 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5380 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5381 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5382 if (is64bit) 5383 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5384 .addReg(Ptr1Reg).addImm(0).addImm(61); 5385 else 5386 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5387 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5388 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 5389 .addReg(newval).addReg(ShiftReg); 5390 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 5391 .addReg(oldval).addReg(ShiftReg); 5392 if (is8bit) 5393 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5394 else { 5395 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5396 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 5397 .addReg(Mask3Reg).addImm(65535); 5398 } 5399 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5400 .addReg(Mask2Reg).addReg(ShiftReg); 5401 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 5402 .addReg(NewVal2Reg).addReg(MaskReg); 5403 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 5404 .addReg(OldVal2Reg).addReg(MaskReg); 5405 5406 BB = loop1MBB; 5407 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5408 .addReg(ZeroReg).addReg(PtrReg); 5409 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 5410 .addReg(TmpDestReg).addReg(MaskReg); 5411 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 5412 .addReg(TmpReg).addReg(OldVal3Reg); 5413 BuildMI(BB, dl, TII->get(PPC::BCC)) 5414 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5415 BB->addSuccessor(loop2MBB); 5416 BB->addSuccessor(midMBB); 5417 5418 BB = loop2MBB; 5419 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 5420 .addReg(TmpDestReg).addReg(MaskReg); 5421 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 5422 .addReg(Tmp2Reg).addReg(NewVal3Reg); 5423 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 5424 .addReg(ZeroReg).addReg(PtrReg); 5425 BuildMI(BB, dl, TII->get(PPC::BCC)) 5426 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5427 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5428 BB->addSuccessor(loop1MBB); 5429 BB->addSuccessor(exitMBB); 5430 5431 BB = midMBB; 5432 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 5433 .addReg(ZeroReg).addReg(PtrReg); 5434 BB->addSuccessor(exitMBB); 5435 5436 // exitMBB: 5437 // ... 5438 BB = exitMBB; 5439 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 5440 .addReg(ShiftReg); 5441 } else { 5442 llvm_unreachable("Unexpected instr type to insert"); 5443 } 5444 5445 MI->eraseFromParent(); // The pseudo instruction is gone now. 5446 return BB; 5447} 5448 5449//===----------------------------------------------------------------------===// 5450// Target Optimization Hooks 5451//===----------------------------------------------------------------------===// 5452 5453SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 5454 DAGCombinerInfo &DCI) const { 5455 const TargetMachine &TM = getTargetMachine(); 5456 SelectionDAG &DAG = DCI.DAG; 5457 DebugLoc dl = N->getDebugLoc(); 5458 switch (N->getOpcode()) { 5459 default: break; 5460 case PPCISD::SHL: 5461 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5462 if (C->isNullValue()) // 0 << V -> 0. 5463 return N->getOperand(0); 5464 } 5465 break; 5466 case PPCISD::SRL: 5467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5468 if (C->isNullValue()) // 0 >>u V -> 0. 5469 return N->getOperand(0); 5470 } 5471 break; 5472 case PPCISD::SRA: 5473 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5474 if (C->isNullValue() || // 0 >>s V -> 0. 5475 C->isAllOnesValue()) // -1 >>s V -> -1. 5476 return N->getOperand(0); 5477 } 5478 break; 5479 5480 case ISD::SINT_TO_FP: 5481 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5482 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5483 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5484 // We allow the src/dst to be either f32/f64, but the intermediate 5485 // type must be i64. 5486 if (N->getOperand(0).getValueType() == MVT::i64 && 5487 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5488 SDValue Val = N->getOperand(0).getOperand(0); 5489 if (Val.getValueType() == MVT::f32) { 5490 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5491 DCI.AddToWorklist(Val.getNode()); 5492 } 5493 5494 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5495 DCI.AddToWorklist(Val.getNode()); 5496 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5497 DCI.AddToWorklist(Val.getNode()); 5498 if (N->getValueType(0) == MVT::f32) { 5499 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5500 DAG.getIntPtrConstant(0)); 5501 DCI.AddToWorklist(Val.getNode()); 5502 } 5503 return Val; 5504 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5505 // If the intermediate type is i32, we can avoid the load/store here 5506 // too. 5507 } 5508 } 5509 } 5510 break; 5511 case ISD::STORE: 5512 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5513 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5514 !cast<StoreSDNode>(N)->isTruncatingStore() && 5515 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5516 N->getOperand(1).getValueType() == MVT::i32 && 5517 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5518 SDValue Val = N->getOperand(1).getOperand(0); 5519 if (Val.getValueType() == MVT::f32) { 5520 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5521 DCI.AddToWorklist(Val.getNode()); 5522 } 5523 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5524 DCI.AddToWorklist(Val.getNode()); 5525 5526 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5527 N->getOperand(2), N->getOperand(3)); 5528 DCI.AddToWorklist(Val.getNode()); 5529 return Val; 5530 } 5531 5532 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5533 if (cast<StoreSDNode>(N)->isUnindexed() && 5534 N->getOperand(1).getOpcode() == ISD::BSWAP && 5535 N->getOperand(1).getNode()->hasOneUse() && 5536 (N->getOperand(1).getValueType() == MVT::i32 || 5537 N->getOperand(1).getValueType() == MVT::i16)) { 5538 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5539 // Do an any-extend to 32-bits if this is a half-word input. 5540 if (BSwapOp.getValueType() == MVT::i16) 5541 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5542 5543 SDValue Ops[] = { 5544 N->getOperand(0), BSwapOp, N->getOperand(2), 5545 DAG.getValueType(N->getOperand(1).getValueType()) 5546 }; 5547 return 5548 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5549 Ops, array_lengthof(Ops), 5550 cast<StoreSDNode>(N)->getMemoryVT(), 5551 cast<StoreSDNode>(N)->getMemOperand()); 5552 } 5553 break; 5554 case ISD::BSWAP: 5555 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5556 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5557 N->getOperand(0).hasOneUse() && 5558 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5559 SDValue Load = N->getOperand(0); 5560 LoadSDNode *LD = cast<LoadSDNode>(Load); 5561 // Create the byte-swapping load. 5562 SDValue Ops[] = { 5563 LD->getChain(), // Chain 5564 LD->getBasePtr(), // Ptr 5565 DAG.getValueType(N->getValueType(0)) // VT 5566 }; 5567 SDValue BSLoad = 5568 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5569 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5570 LD->getMemoryVT(), LD->getMemOperand()); 5571 5572 // If this is an i16 load, insert the truncate. 5573 SDValue ResVal = BSLoad; 5574 if (N->getValueType(0) == MVT::i16) 5575 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5576 5577 // First, combine the bswap away. This makes the value produced by the 5578 // load dead. 5579 DCI.CombineTo(N, ResVal); 5580 5581 // Next, combine the load away, we give it a bogus result value but a real 5582 // chain result. The result value is dead because the bswap is dead. 5583 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5584 5585 // Return N so it doesn't get rechecked! 5586 return SDValue(N, 0); 5587 } 5588 5589 break; 5590 case PPCISD::VCMP: { 5591 // If a VCMPo node already exists with exactly the same operands as this 5592 // node, use its result instead of this node (VCMPo computes both a CR6 and 5593 // a normal output). 5594 // 5595 if (!N->getOperand(0).hasOneUse() && 5596 !N->getOperand(1).hasOneUse() && 5597 !N->getOperand(2).hasOneUse()) { 5598 5599 // Scan all of the users of the LHS, looking for VCMPo's that match. 5600 SDNode *VCMPoNode = 0; 5601 5602 SDNode *LHSN = N->getOperand(0).getNode(); 5603 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5604 UI != E; ++UI) 5605 if (UI->getOpcode() == PPCISD::VCMPo && 5606 UI->getOperand(1) == N->getOperand(1) && 5607 UI->getOperand(2) == N->getOperand(2) && 5608 UI->getOperand(0) == N->getOperand(0)) { 5609 VCMPoNode = *UI; 5610 break; 5611 } 5612 5613 // If there is no VCMPo node, or if the flag value has a single use, don't 5614 // transform this. 5615 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5616 break; 5617 5618 // Look at the (necessarily single) use of the flag value. If it has a 5619 // chain, this transformation is more complex. Note that multiple things 5620 // could use the value result, which we should ignore. 5621 SDNode *FlagUser = 0; 5622 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5623 FlagUser == 0; ++UI) { 5624 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5625 SDNode *User = *UI; 5626 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5627 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5628 FlagUser = User; 5629 break; 5630 } 5631 } 5632 } 5633 5634 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5635 // give up for right now. 5636 if (FlagUser->getOpcode() == PPCISD::MFCR) 5637 return SDValue(VCMPoNode, 0); 5638 } 5639 break; 5640 } 5641 case ISD::BR_CC: { 5642 // If this is a branch on an altivec predicate comparison, lower this so 5643 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5644 // lowering is done pre-legalize, because the legalizer lowers the predicate 5645 // compare down to code that is difficult to reassemble. 5646 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5647 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5648 int CompareOpc; 5649 bool isDot; 5650 5651 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5652 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5653 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5654 assert(isDot && "Can't compare against a vector result!"); 5655 5656 // If this is a comparison against something other than 0/1, then we know 5657 // that the condition is never/always true. 5658 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5659 if (Val != 0 && Val != 1) { 5660 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5661 return N->getOperand(0); 5662 // Always !=, turn it into an unconditional branch. 5663 return DAG.getNode(ISD::BR, dl, MVT::Other, 5664 N->getOperand(0), N->getOperand(4)); 5665 } 5666 5667 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5668 5669 // Create the PPCISD altivec 'dot' comparison node. 5670 std::vector<EVT> VTs; 5671 SDValue Ops[] = { 5672 LHS.getOperand(2), // LHS of compare 5673 LHS.getOperand(3), // RHS of compare 5674 DAG.getConstant(CompareOpc, MVT::i32) 5675 }; 5676 VTs.push_back(LHS.getOperand(2).getValueType()); 5677 VTs.push_back(MVT::Glue); 5678 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5679 5680 // Unpack the result based on how the target uses it. 5681 PPC::Predicate CompOpc; 5682 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5683 default: // Can't happen, don't crash on invalid number though. 5684 case 0: // Branch on the value of the EQ bit of CR6. 5685 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5686 break; 5687 case 1: // Branch on the inverted value of the EQ bit of CR6. 5688 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5689 break; 5690 case 2: // Branch on the value of the LT bit of CR6. 5691 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5692 break; 5693 case 3: // Branch on the inverted value of the LT bit of CR6. 5694 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5695 break; 5696 } 5697 5698 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5699 DAG.getConstant(CompOpc, MVT::i32), 5700 DAG.getRegister(PPC::CR6, MVT::i32), 5701 N->getOperand(4), CompNode.getValue(1)); 5702 } 5703 break; 5704 } 5705 } 5706 5707 return SDValue(); 5708} 5709 5710//===----------------------------------------------------------------------===// 5711// Inline Assembly Support 5712//===----------------------------------------------------------------------===// 5713 5714void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5715 APInt &KnownZero, 5716 APInt &KnownOne, 5717 const SelectionDAG &DAG, 5718 unsigned Depth) const { 5719 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 5720 switch (Op.getOpcode()) { 5721 default: break; 5722 case PPCISD::LBRX: { 5723 // lhbrx is known to have the top bits cleared out. 5724 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5725 KnownZero = 0xFFFF0000; 5726 break; 5727 } 5728 case ISD::INTRINSIC_WO_CHAIN: { 5729 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5730 default: break; 5731 case Intrinsic::ppc_altivec_vcmpbfp_p: 5732 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5733 case Intrinsic::ppc_altivec_vcmpequb_p: 5734 case Intrinsic::ppc_altivec_vcmpequh_p: 5735 case Intrinsic::ppc_altivec_vcmpequw_p: 5736 case Intrinsic::ppc_altivec_vcmpgefp_p: 5737 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5738 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5739 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5740 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5741 case Intrinsic::ppc_altivec_vcmpgtub_p: 5742 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5743 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5744 KnownZero = ~1U; // All bits but the low one are known to be zero. 5745 break; 5746 } 5747 } 5748 } 5749} 5750 5751 5752/// getConstraintType - Given a constraint, return the type of 5753/// constraint it is for this target. 5754PPCTargetLowering::ConstraintType 5755PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5756 if (Constraint.size() == 1) { 5757 switch (Constraint[0]) { 5758 default: break; 5759 case 'b': 5760 case 'r': 5761 case 'f': 5762 case 'v': 5763 case 'y': 5764 return C_RegisterClass; 5765 } 5766 } 5767 return TargetLowering::getConstraintType(Constraint); 5768} 5769 5770/// Examine constraint type and operand type and determine a weight value. 5771/// This object must already have been set up with the operand type 5772/// and the current alternative constraint selected. 5773TargetLowering::ConstraintWeight 5774PPCTargetLowering::getSingleConstraintMatchWeight( 5775 AsmOperandInfo &info, const char *constraint) const { 5776 ConstraintWeight weight = CW_Invalid; 5777 Value *CallOperandVal = info.CallOperandVal; 5778 // If we don't have a value, we can't do a match, 5779 // but allow it at the lowest weight. 5780 if (CallOperandVal == NULL) 5781 return CW_Default; 5782 Type *type = CallOperandVal->getType(); 5783 // Look at the constraint type. 5784 switch (*constraint) { 5785 default: 5786 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 5787 break; 5788 case 'b': 5789 if (type->isIntegerTy()) 5790 weight = CW_Register; 5791 break; 5792 case 'f': 5793 if (type->isFloatTy()) 5794 weight = CW_Register; 5795 break; 5796 case 'd': 5797 if (type->isDoubleTy()) 5798 weight = CW_Register; 5799 break; 5800 case 'v': 5801 if (type->isVectorTy()) 5802 weight = CW_Register; 5803 break; 5804 case 'y': 5805 weight = CW_Register; 5806 break; 5807 } 5808 return weight; 5809} 5810 5811std::pair<unsigned, const TargetRegisterClass*> 5812PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5813 EVT VT) const { 5814 if (Constraint.size() == 1) { 5815 // GCC RS6000 Constraint Letters 5816 switch (Constraint[0]) { 5817 case 'b': // R1-R31 5818 case 'r': // R0-R31 5819 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5820 return std::make_pair(0U, &PPC::G8RCRegClass); 5821 return std::make_pair(0U, &PPC::GPRCRegClass); 5822 case 'f': 5823 if (VT == MVT::f32) 5824 return std::make_pair(0U, &PPC::F4RCRegClass); 5825 if (VT == MVT::f64) 5826 return std::make_pair(0U, &PPC::F8RCRegClass); 5827 break; 5828 case 'v': 5829 return std::make_pair(0U, &PPC::VRRCRegClass); 5830 case 'y': // crrc 5831 return std::make_pair(0U, &PPC::CRRCRegClass); 5832 } 5833 } 5834 5835 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5836} 5837 5838 5839/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5840/// vector. If it is invalid, don't add anything to Ops. 5841void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 5842 std::string &Constraint, 5843 std::vector<SDValue>&Ops, 5844 SelectionDAG &DAG) const { 5845 SDValue Result(0,0); 5846 5847 // Only support length 1 constraints. 5848 if (Constraint.length() > 1) return; 5849 5850 char Letter = Constraint[0]; 5851 switch (Letter) { 5852 default: break; 5853 case 'I': 5854 case 'J': 5855 case 'K': 5856 case 'L': 5857 case 'M': 5858 case 'N': 5859 case 'O': 5860 case 'P': { 5861 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5862 if (!CST) return; // Must be an immediate to match. 5863 unsigned Value = CST->getZExtValue(); 5864 switch (Letter) { 5865 default: llvm_unreachable("Unknown constraint letter!"); 5866 case 'I': // "I" is a signed 16-bit constant. 5867 if ((short)Value == (int)Value) 5868 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5869 break; 5870 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5871 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5872 if ((short)Value == 0) 5873 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5874 break; 5875 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5876 if ((Value >> 16) == 0) 5877 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5878 break; 5879 case 'M': // "M" is a constant that is greater than 31. 5880 if (Value > 31) 5881 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5882 break; 5883 case 'N': // "N" is a positive constant that is an exact power of two. 5884 if ((int)Value > 0 && isPowerOf2_32(Value)) 5885 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5886 break; 5887 case 'O': // "O" is the constant zero. 5888 if (Value == 0) 5889 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5890 break; 5891 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5892 if ((short)-Value == (int)-Value) 5893 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5894 break; 5895 } 5896 break; 5897 } 5898 } 5899 5900 if (Result.getNode()) { 5901 Ops.push_back(Result); 5902 return; 5903 } 5904 5905 // Handle standard constraint letters. 5906 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 5907} 5908 5909// isLegalAddressingMode - Return true if the addressing mode represented 5910// by AM is legal for this target, for a load/store of the specified type. 5911bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5912 Type *Ty) const { 5913 // FIXME: PPC does not allow r+i addressing modes for vectors! 5914 5915 // PPC allows a sign-extended 16-bit immediate field. 5916 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5917 return false; 5918 5919 // No global is ever allowed as a base. 5920 if (AM.BaseGV) 5921 return false; 5922 5923 // PPC only support r+r, 5924 switch (AM.Scale) { 5925 case 0: // "r+i" or just "i", depending on HasBaseReg. 5926 break; 5927 case 1: 5928 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5929 return false; 5930 // Otherwise we have r+r or r+i. 5931 break; 5932 case 2: 5933 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5934 return false; 5935 // Allow 2*r as r+r. 5936 break; 5937 default: 5938 // No other scales are supported. 5939 return false; 5940 } 5941 5942 return true; 5943} 5944 5945/// isLegalAddressImmediate - Return true if the integer value can be used 5946/// as the offset of the target addressing mode for load / store of the 5947/// given type. 5948bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{ 5949 // PPC allows a sign-extended 16-bit immediate field. 5950 return (V > -(1 << 16) && V < (1 << 16)-1); 5951} 5952 5953bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const { 5954 return false; 5955} 5956 5957SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 5958 SelectionDAG &DAG) const { 5959 MachineFunction &MF = DAG.getMachineFunction(); 5960 MachineFrameInfo *MFI = MF.getFrameInfo(); 5961 MFI->setReturnAddressIsTaken(true); 5962 5963 DebugLoc dl = Op.getDebugLoc(); 5964 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5965 5966 // Make sure the function does not optimize away the store of the RA to 5967 // the stack. 5968 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5969 FuncInfo->setLRStoreRequired(); 5970 bool isPPC64 = PPCSubTarget.isPPC64(); 5971 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 5972 5973 if (Depth > 0) { 5974 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 5975 SDValue Offset = 5976 5977 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 5978 isPPC64? MVT::i64 : MVT::i32); 5979 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5980 DAG.getNode(ISD::ADD, dl, getPointerTy(), 5981 FrameAddr, Offset), 5982 MachinePointerInfo(), false, false, false, 0); 5983 } 5984 5985 // Just load the return address off the stack. 5986 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5987 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5988 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 5989} 5990 5991SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 5992 SelectionDAG &DAG) const { 5993 DebugLoc dl = Op.getDebugLoc(); 5994 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5995 5996 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5997 bool isPPC64 = PtrVT == MVT::i64; 5998 5999 MachineFunction &MF = DAG.getMachineFunction(); 6000 MachineFrameInfo *MFI = MF.getFrameInfo(); 6001 MFI->setFrameAddressIsTaken(true); 6002 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) || 6003 MFI->hasVarSizedObjects()) && 6004 MFI->getStackSize() && 6005 !MF.getFunction()->getFnAttributes().hasNakedAttr(); 6006 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 6007 (is31 ? PPC::R31 : PPC::R1); 6008 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 6009 PtrVT); 6010 while (Depth--) 6011 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 6012 FrameAddr, MachinePointerInfo(), false, false, 6013 false, 0); 6014 return FrameAddr; 6015} 6016 6017bool 6018PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 6019 // The PowerPC target isn't yet aware of offsets. 6020 return false; 6021} 6022 6023/// getOptimalMemOpType - Returns the target specific optimal type for load 6024/// and store operations as a result of memset, memcpy, and memmove 6025/// lowering. If DstAlign is zero that means it's safe to destination 6026/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 6027/// means there isn't a need to check it against alignment requirement, 6028/// probably because the source does not need to be loaded. If 6029/// 'IsZeroVal' is true, that means it's safe to return a 6030/// non-scalar-integer type, e.g. empty string source, constant, or loaded 6031/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 6032/// constant so it does not need to be loaded. 6033/// It returns EVT::Other if the type should be determined using generic 6034/// target-independent logic. 6035EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 6036 unsigned DstAlign, unsigned SrcAlign, 6037 bool IsZeroVal, 6038 bool MemcpyStrSrc, 6039 MachineFunction &MF) const { 6040 if (this->PPCSubTarget.isPPC64()) { 6041 return MVT::i64; 6042 } else { 6043 return MVT::i32; 6044 } 6045} 6046 6047/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 6048/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 6049/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 6050/// is expanded to mul + add. 6051bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const { 6052 if (!VT.isSimple()) 6053 return false; 6054 6055 switch (VT.getSimpleVT().SimpleTy) { 6056 case MVT::f32: 6057 case MVT::f64: 6058 case MVT::v4f32: 6059 return true; 6060 default: 6061 break; 6062 } 6063 6064 return false; 6065} 6066 6067Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { 6068 if (DisableILPPref) 6069 return TargetLowering::getSchedulingPreference(N); 6070 6071 return Sched::ILP; 6072} 6073 6074