Searched refs:WRITE32_REG (Results 1 - 10 of 10) sorted by relevance
/fuchsia/zircon/system/dev/display/astro-display/ |
H A D | vpu.cpp | 118 WRITE32_REG(VPU, VPP_HOLD_LINES, 0x08080808); 126 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1, 128 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2, 130 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF00_01, 132 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF02_10, 134 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF11_12, 136 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF20_21, 138 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF22, 140 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_OFFSET0_1, 142 WRITE32_REG(VP [all...] |
H A D | astro-clock.cpp | 59 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL6, 0x55540000); // more magic 149 WRITE32_REG(VPU, ENCL_VIDEO_EN, 0); 183 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL0, regVal); 185 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL1, pll_cfg->pll_frac); 186 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL2, 0x00); 188 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL3, useFrac? 0x6a285c00 : 0x48681c00); 189 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL4, useFrac? 0x65771290 : 0x33771290); 190 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL5, 0x39272000); 191 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL6, useFrac? 0x56540000 : 0x56540000); 259 WRITE32_REG(VP [all...] |
H A D | osd.cpp | 109 WRITE32_REG(VPU, VIU_OSD_BLEND_CTRL, 120 WRITE32_REG(VPU, OSD1_BLEND_SRC_CTRL, 127 WRITE32_REG(VPU, OSD2_BLEND_SRC_CTRL, 135 WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_DATA0, 140 WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_ALPHA, 146 WRITE32_REG(VPU, 150 WRITE32_REG(VPU, 154 WRITE32_REG(VPU, VIU_OSD_BLEND_BLEND0_SIZE, 157 WRITE32_REG(VPU, VIU_OSD_BLEND_BLEND1_SIZE, 162 WRITE32_REG(VP [all...] |
H A D | aml-mipi-phy.cpp | 133 WRITE32_REG(DSI_PHY, MIPI_DSI_PHY_CTRL, PHY_CTRL_TXDDRCLK_EN | 141 WRITE32_REG(DSI_PHY, MIPI_DSI_CLK_TIM, 146 WRITE32_REG(DSI_PHY, MIPI_DSI_CLK_TIM1, dsi_phy_cfg_.clk_pre); 148 WRITE32_REG(DSI_PHY, MIPI_DSI_HS_TIM, 153 WRITE32_REG(DSI_PHY, MIPI_DSI_LP_TIM, 157 WRITE32_REG(DSI_PHY, MIPI_DSI_ANA_UP_TIM, ANA_UP_TIME); 158 WRITE32_REG(DSI_PHY, MIPI_DSI_INIT_TIM, dsi_phy_cfg_.init); 159 WRITE32_REG(DSI_PHY, MIPI_DSI_WAKEUP_TIM, dsi_phy_cfg_.wakeup); 160 WRITE32_REG(DSI_PHY, MIPI_DSI_LPOK_TIM, LPOK_TIME); 161 WRITE32_REG(DSI_PH [all...] |
H A D | aml-dsi-host.cpp | 22 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_IF_CFG, PHY_IF_CFG_STOP_WAIT_TIME | 26 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_VCID, MIPI_DSI_VIRTUAL_CHAN_ID); 29 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_COLOR_CODING, DPI_COLOR_CODING(SUPPORTED_DPI_FORMAT)); 40 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_CFG_POL, 0); 44 WRITE32_REG(MIPI_DSI, DW_DSI_VID_MODE_CFG,VID_MODE_CFG_LP_EN_ALL | 48 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_LP_CMD_TIM, LP_CMD_TIM_OUTVACT(LPCMD_PKT_SIZE) | 52 WRITE32_REG(MIPI_DSI, DW_DSI_VID_PKT_SIZE, disp_setting.h_active); 54 WRITE32_REG(MIPI_DSI, DW_DSI_VID_NUM_CHUNKS, 0); 55 WRITE32_REG(MIPI_DSI, DW_DSI_VID_NULL_SIZE, 0); 58 WRITE32_REG(MIPI_DS [all...] |
H A D | common.h | 26 #define WRITE32_REG(x, a, v) WRITE32_##x##_REG(a, v) macro
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H A D | dw-mipi-dsi.cpp | 104 WRITE32_REG(MIPI_DSI, DW_DSI_GEN_HDR, data); 114 WRITE32_REG(MIPI_DSI, DW_DSI_GEN_PLD_DATA, data);
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/fuchsia/zircon/system/dev/display/vim-display/ |
H A D | hdmitx.cpp | 81 WRITE32_REG(HHI,HHI_HDMI_PHY_CNTL0, 0); 82 WRITE32_REG(HHI,HHI_HDMI_PHY_CNTL3, 0); 84 WRITE32_REG(HHI,HHI_HDMI_PLL_CNTL, 0); 387 WRITE32_REG(VPU, VPU_ENCP_VIDEO_HAVON_BEGIN, p->timings.hsync + p->timings.hback); 388 WRITE32_REG(VPU, VPU_ENCP_VIDEO_HAVON_END, p->timings.hsync + p->timings.hback + 391 WRITE32_REG(VPU, VPU_ENCP_VIDEO_VAVON_BLINE, p->timings.vsync + p->timings.vback); 392 WRITE32_REG(VPU, VPU_ENCP_VIDEO_VAVON_ELINE, p->timings.vsync + p->timings.vback + 395 WRITE32_REG(VPU, VPU_ENCP_VIDEO_HSO_BEGIN, 0); 396 WRITE32_REG(VPU, VPU_ENCP_VIDEO_HSO_END, p->timings.hsync); 398 WRITE32_REG(VP [all...] |
H A D | hdmitx_clk.cpp | 62 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL, regVal); 65 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL1, 0x800cb000); 68 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL2, 0x860f30c4); 69 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL3, 0x0c8e0000); 70 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL4, 0x001fa729); 71 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL5, 0x01a31500);
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H A D | hdmitx.h | 50 #define WRITE32_REG(x, a, v) WRITE32_##x##_REG(a, v) macro
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