1// Copyright 2018 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#include "aml-dsi-host.h" 6#include <ddk/debug.h> 7 8namespace astro_display { 9 10#define READ32_MIPI_DSI_REG(a) mipi_dsi_regs_->Read<uint32_t>(a) 11#define WRITE32_MIPI_DSI_REG(a, v) mipi_dsi_regs_->Write<uint32_t>(a, v) 12 13#define READ32_HHI_REG(a) hhi_regs_->Read<uint32_t>(a) 14#define WRITE32_HHI_REG(a, v) hhi_regs_->Write<uint32_t>(a, v) 15 16zx_status_t AmlDsiHost::HostModeInit(uint32_t opp, const DisplaySetting& disp_setting) { 17 uint32_t lane_num = disp_setting.lane_num; 18 19 // DesignWare DSI Host Setup based on MIPI DSI Host Controller User Guide (Sec 3.1.1) 20 21 // 1. Global configuration: Lane number and PHY stop wait time 22 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_IF_CFG, PHY_IF_CFG_STOP_WAIT_TIME | 23 PHY_IF_CFG_N_LANES(lane_num)); 24 25 // 2.1 Configure virtual channel 26 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_VCID, MIPI_DSI_VIRTUAL_CHAN_ID); 27 28 // 2.2, Configure Color format 29 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_COLOR_CODING, DPI_COLOR_CODING(SUPPORTED_DPI_FORMAT)); 30 31 // Setup relevant TOP_CNTL register -- Undocumented -- 32 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, SUPPORTED_DPI_FORMAT, 33 TOP_CNTL_DPI_CLR_MODE_START, TOP_CNTL_DPI_CLR_MODE_BITS); 34 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, SUPPORTED_VENC_DATA_WIDTH, 35 TOP_CNTL_IN_CLR_MODE_START, TOP_CNTL_IN_CLR_MODE_BITS); 36 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, 0, 37 TOP_CNTL_CHROMA_SUBSAMPLE_START, TOP_CNTL_CHROMA_SUBSAMPLE_BITS); 38 39 // 2.3 Configure Signal polarity - Keep as default 40 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_CFG_POL, 0); 41 42 if (opp == VIDEO_MODE) { 43 // 3.1 Configure low power transitions and video mode type 44 WRITE32_REG(MIPI_DSI, DW_DSI_VID_MODE_CFG,VID_MODE_CFG_LP_EN_ALL | 45 (VID_MODE_CFG_VID_MODE_TYPE(SUPPORTED_VIDEO_MODE_TYPE))); 46 47 // Define the max pkt size during Low Power mode 48 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_LP_CMD_TIM, LP_CMD_TIM_OUTVACT(LPCMD_PKT_SIZE) | 49 LP_CMD_TIM_INVACT(LPCMD_PKT_SIZE)); 50 51 // 3.2 Configure video packet size settings 52 WRITE32_REG(MIPI_DSI, DW_DSI_VID_PKT_SIZE, disp_setting.h_active); 53 // Disable sending vid in chunk since they are ignored by DW host IP in burst mode 54 WRITE32_REG(MIPI_DSI, DW_DSI_VID_NUM_CHUNKS, 0); 55 WRITE32_REG(MIPI_DSI, DW_DSI_VID_NULL_SIZE, 0); 56 57 // 4 Configure the video relative parameters according to the output type 58 WRITE32_REG(MIPI_DSI, DW_DSI_VID_HLINE_TIME, disp_setting.h_period); 59 WRITE32_REG(MIPI_DSI, DW_DSI_VID_HSA_TIME, disp_setting.hsync_width); 60 WRITE32_REG(MIPI_DSI, DW_DSI_VID_HBP_TIME, disp_setting.hsync_bp); 61 WRITE32_REG(MIPI_DSI, DW_DSI_VID_VSA_LINES, disp_setting.vsync_width); 62 WRITE32_REG(MIPI_DSI, DW_DSI_VID_VBP_LINES, disp_setting.vsync_bp); 63 WRITE32_REG(MIPI_DSI, DW_DSI_VID_VACTIVE_LINES, disp_setting.v_active); 64 WRITE32_REG(MIPI_DSI, DW_DSI_VID_VFP_LINES, (disp_setting.v_period - 65 disp_setting.v_active - disp_setting.vsync_bp - 66 disp_setting.vsync_width)); 67 } 68 69 // Internal dividers to divide lanebyteclk for timeout purposes 70 WRITE32_REG(MIPI_DSI, DW_DSI_CLKMGR_CFG, 71 (CLKMGR_CFG_TO_CLK_DIV(1)) | 72 (CLKMGR_CFG_TX_ESC_CLK_DIV(phy_->GetLowPowerEscaseTime()))); 73 74 // Configure the operation mode (cmd or vid) 75 WRITE32_REG(MIPI_DSI, DW_DSI_MODE_CFG, opp); 76 77 // Setup Phy Timers as provided by vendor 78 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TMR_LPCLK_CFG, 79 PHY_TMR_LPCLK_CFG_CLKHS_TO_LP(PHY_TMR_LPCLK_CLKHS_TO_LP) | 80 PHY_TMR_LPCLK_CFG_CLKLP_TO_HS(PHY_TMR_LPCLK_CLKLP_TO_HS)); 81 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TMR_CFG, 82 PHY_TMR_CFG_HS_TO_LP(PHY_TMR_HS_TO_LP) | 83 PHY_TMR_CFG_LP_TO_HS(PHY_TMR_LP_TO_HS)); 84 85 return ZX_OK; 86} 87 88void AmlDsiHost::PhyEnable() { 89 WRITE32_REG(HHI, HHI_MIPI_CNTL0, MIPI_CNTL0_CMN_REF_GEN_CTRL(0x29) | 90 MIPI_CNTL0_VREF_SEL(VREF_SEL_VR) | 91 MIPI_CNTL0_LREF_SEL(LREF_SEL_L_ROUT) | 92 MIPI_CNTL0_LBG_EN | 93 MIPI_CNTL0_VR_TRIM_CNTL(0x7) | 94 MIPI_CNTL0_VR_GEN_FROM_LGB_EN); 95 WRITE32_REG(HHI, HHI_MIPI_CNTL1, MIPI_CNTL1_DSI_VBG_EN | MIPI_CNTL1_CTL); 96 WRITE32_REG(HHI, HHI_MIPI_CNTL2, MIPI_CNTL2_DEFAULT_VAL); // 4 lane 97} 98 99void AmlDsiHost::PhyDisable() { 100 WRITE32_REG(HHI, HHI_MIPI_CNTL0, 0); 101 WRITE32_REG(HHI, HHI_MIPI_CNTL1, 0); 102 WRITE32_REG(HHI, HHI_MIPI_CNTL2, 0); 103} 104 105void AmlDsiHost::HostOff(const DisplaySetting& disp_setting) { 106 ZX_DEBUG_ASSERT(initialized_); 107 // turn host off only if it's been fully turned on 108 if (!host_on_) { 109 return; 110 } 111 112 // Place dsi in command mode first 113 HostModeInit(COMMAND_MODE, disp_setting); 114 115 // Turn off LCD 116 lcd_->Disable(); 117 118 // disable PHY 119 PhyDisable(); 120 121 // finally shutdown host 122 phy_->Shutdown(); 123 124 host_on_ = false; 125} 126 127zx_status_t AmlDsiHost::HostOn(const DisplaySetting& disp_setting) { 128 ZX_DEBUG_ASSERT(initialized_); 129 130 if (host_on_) { 131 return ZX_OK; 132 } 133 134 // Enable MIPI PHY 135 PhyEnable(); 136 137 // Create MIPI PHY object 138 fbl::AllocChecker ac; 139 phy_ = fbl::make_unique_checked<astro_display::AmlMipiPhy>(&ac); 140 if (!ac.check()) { 141 DISP_ERROR("Could not create AmlMipiPhy object\n"); 142 return ZX_ERR_NO_MEMORY; 143 } 144 zx_status_t status = phy_->Init(parent_, disp_setting.lane_num); 145 if (status != ZX_OK) { 146 DISP_ERROR("MIPI PHY Init failed!\n"); 147 return status; 148 } 149 150 // Load Phy configuration 151 status = phy_->PhyCfgLoad(bitrate_); 152 if (status != ZX_OK) { 153 DISP_ERROR("Error during phy config calculations! %d\n", status); 154 return status; 155 } 156 157 // Enable dwc mipi_dsi_host's clock 158 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, 0x3, 4, 2); 159 // mipi_dsi_host's reset 160 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_SW_RESET, 0xf, 0, 4); 161 // Release mipi_dsi_host's reset 162 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_SW_RESET, 0x0, 0, 4); 163 // Enable dwc mipi_dsi_host's clock 164 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CLK_CNTL, 0x3, 0, 2); 165 166 WRITE32_REG(MIPI_DSI, MIPI_DSI_TOP_MEM_PD, 0); 167 zx_nanosleep(zx_deadline_after(ZX_MSEC(10))); 168 169 // Enable LP transmission in CMD Mode 170 WRITE32_REG(MIPI_DSI, DW_DSI_CMD_MODE_CFG,CMD_MODE_CFG_CMD_LP_ALL); 171 172 // Packet header settings - Enable CRC and ECC. BTA will be enabled based on CMD 173 WRITE32_REG(MIPI_DSI, DW_DSI_PCKHDL_CFG, PCKHDL_CFG_EN_CRC_ECC); 174 175 // Initialize host in command mode first 176 if ((status = HostModeInit(COMMAND_MODE, disp_setting)) != ZX_OK) { 177 DISP_ERROR("Error during dsi host init! %d\n", status); 178 return status; 179 } 180 181 // Initialize mipi dsi D-phy 182 if ((status = phy_->Startup()) != ZX_OK) { 183 DISP_ERROR("Error during MIPI D-PHY Initialization! %d\n", status); 184 return status; 185 } 186 187 // Enable LP Clock 188 SET_BIT32(MIPI_DSI, DW_DSI_LPCLK_CTRL, 1, LPCLK_CTRL_AUTOCLKLANE_CTRL, 1); 189 190 // Load LCD Init values while in command mode 191 lcd_ = fbl::make_unique_checked<astro_display::Lcd>(&ac, panel_type_); 192 if (!ac.check()) { 193 DISP_ERROR("Failed to create LCD object\n"); 194 return ZX_ERR_NO_MEMORY; 195 } 196 197 status = lcd_->Init(parent_); 198 if (status != ZX_OK) { 199 DISP_ERROR("Error during LCD Initialization! %d\n", status); 200 return status; 201 } 202 203 status = lcd_->Enable(); 204 if (status != ZX_OK) { 205 DISP_ERROR("Could not enable LCD! %d\n", status); 206 return status; 207 } 208 209 // switch to video mode 210 if ((status = HostModeInit(VIDEO_MODE, disp_setting)) != ZX_OK) { 211 DISP_ERROR("Error during dsi host init! %d\n", status); 212 return status; 213 } 214 215 // Host is On and Active at this point 216 host_on_ = true; 217 return ZX_OK; 218} 219 220zx_status_t AmlDsiHost::Init() { 221 if (initialized_) { 222 return ZX_OK; 223 } 224 225 zx_status_t status = device_get_protocol(parent_, ZX_PROTOCOL_PLATFORM_DEV, &pdev_); 226 if (status != ZX_OK) { 227 DISP_ERROR("AmlDsiHost: Could not get ZX_PROTOCOL_PLATFORM_DEV protocol\n"); 228 return status; 229 } 230 231 // Map MIPI DSI and HHI registers 232 status = pdev_map_mmio_buffer(&pdev_, MMIO_MPI_DSI, ZX_CACHE_POLICY_UNCACHED_DEVICE, 233 &mmio_mipi_dsi_); 234 if (status != ZX_OK) { 235 DISP_ERROR("Could not map MIPI DSI mmio\n"); 236 return status; 237 } 238 239 status = pdev_map_mmio_buffer(&pdev_, MMIO_HHI, ZX_CACHE_POLICY_UNCACHED_DEVICE, 240 &mmio_hhi_); 241 if (status != ZX_OK) { 242 DISP_ERROR("Could not map HHI mmio\n"); 243 io_buffer_release(&mmio_mipi_dsi_); 244 return status; 245 } 246 247 // Create register IO 248 mipi_dsi_regs_ = fbl::make_unique<hwreg::RegisterIo>(io_buffer_virt(&mmio_mipi_dsi_)); 249 hhi_regs_ = fbl::make_unique<hwreg::RegisterIo>(io_buffer_virt(&mmio_hhi_)); 250 251 initialized_ = true; 252 return ZX_OK; 253} 254 255void AmlDsiHost::Dump() { 256 ZX_DEBUG_ASSERT(initialized_); 257 258 DISP_INFO("%s: DUMPING DSI HOST REGS\n", __func__); 259 DISP_INFO("DW_DSI_VERSION = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VERSION)); 260 DISP_INFO("DW_DSI_PWR_UP = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PWR_UP)); 261 DISP_INFO("DW_DSI_CLKMGR_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_CLKMGR_CFG)); 262 DISP_INFO("DW_DSI_DPI_VCID = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_DPI_VCID)); 263 DISP_INFO("DW_DSI_DPI_COLOR_CODING = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_DPI_COLOR_CODING)); 264 DISP_INFO("DW_DSI_DPI_CFG_POL = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_DPI_CFG_POL)); 265 DISP_INFO("DW_DSI_DPI_LP_CMD_TIM = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_DPI_LP_CMD_TIM)); 266 DISP_INFO("DW_DSI_DBI_VCID = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_DBI_VCID)); 267 DISP_INFO("DW_DSI_DBI_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_DBI_CFG)); 268 DISP_INFO("DW_DSI_DBI_PARTITIONING_EN = 0x%x\n", 269 READ32_REG(MIPI_DSI, DW_DSI_DBI_PARTITIONING_EN)); 270 DISP_INFO("DW_DSI_DBI_CMDSIZE = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_DBI_CMDSIZE)); 271 DISP_INFO("DW_DSI_PCKHDL_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PCKHDL_CFG)); 272 DISP_INFO("DW_DSI_GEN_VCID = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_GEN_VCID)); 273 DISP_INFO("DW_DSI_MODE_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_MODE_CFG)); 274 DISP_INFO("DW_DSI_VID_MODE_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_MODE_CFG)); 275 DISP_INFO("DW_DSI_VID_PKT_SIZE = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_PKT_SIZE)); 276 DISP_INFO("DW_DSI_VID_NUM_CHUNKS = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_NUM_CHUNKS)); 277 DISP_INFO("DW_DSI_VID_NULL_SIZE = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_NULL_SIZE)); 278 DISP_INFO("DW_DSI_VID_HSA_TIME = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_HSA_TIME)); 279 DISP_INFO("DW_DSI_VID_HBP_TIME = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_HBP_TIME)); 280 DISP_INFO("DW_DSI_VID_HLINE_TIME = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_HLINE_TIME)); 281 DISP_INFO("DW_DSI_VID_VSA_LINES = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_VSA_LINES)); 282 DISP_INFO("DW_DSI_VID_VBP_LINES = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_VBP_LINES)); 283 DISP_INFO("DW_DSI_VID_VFP_LINES = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_VFP_LINES)); 284 DISP_INFO("DW_DSI_VID_VACTIVE_LINES = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VID_VACTIVE_LINES)); 285 DISP_INFO("DW_DSI_EDPI_CMD_SIZE = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_EDPI_CMD_SIZE)); 286 DISP_INFO("DW_DSI_CMD_MODE_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_CMD_MODE_CFG)); 287 DISP_INFO("DW_DSI_GEN_HDR = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_GEN_HDR)); 288 DISP_INFO("DW_DSI_GEN_PLD_DATA = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_GEN_PLD_DATA)); 289 DISP_INFO("DW_DSI_CMD_PKT_STATUS = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_CMD_PKT_STATUS)); 290 DISP_INFO("DW_DSI_TO_CNT_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_TO_CNT_CFG)); 291 DISP_INFO("DW_DSI_HS_RD_TO_CNT = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_HS_RD_TO_CNT)); 292 DISP_INFO("DW_DSI_LP_RD_TO_CNT = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_LP_RD_TO_CNT)); 293 DISP_INFO("DW_DSI_HS_WR_TO_CNT = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_HS_WR_TO_CNT)); 294 DISP_INFO("DW_DSI_LP_WR_TO_CNT = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_LP_WR_TO_CNT)); 295 DISP_INFO("DW_DSI_BTA_TO_CNT = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_BTA_TO_CNT)); 296 DISP_INFO("DW_DSI_SDF_3D = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_SDF_3D)); 297 DISP_INFO("DW_DSI_LPCLK_CTRL = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_LPCLK_CTRL)); 298 DISP_INFO("DW_DSI_PHY_TMR_LPCLK_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_TMR_LPCLK_CFG)); 299 DISP_INFO("DW_DSI_PHY_TMR_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_TMR_CFG)); 300 DISP_INFO("DW_DSI_PHY_RSTZ = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_RSTZ)); 301 DISP_INFO("DW_DSI_PHY_IF_CFG = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_IF_CFG)); 302 DISP_INFO("DW_DSI_PHY_ULPS_CTRL = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_ULPS_CTRL)); 303 DISP_INFO("DW_DSI_PHY_TX_TRIGGERS = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_TX_TRIGGERS)); 304 DISP_INFO("DW_DSI_PHY_STATUS = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_STATUS)); 305 DISP_INFO("DW_DSI_PHY_TST_CTRL0 = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0)); 306 DISP_INFO("DW_DSI_PHY_TST_CTRL1 = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL1)); 307 DISP_INFO("DW_DSI_INT_ST0 = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_INT_ST0)); 308 DISP_INFO("DW_DSI_INT_ST1 = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_INT_ST1)); 309 DISP_INFO("DW_DSI_INT_MSK0 = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_INT_MSK0)); 310 DISP_INFO("DW_DSI_INT_MSK1 = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_INT_MSK1)); 311 312 DISP_INFO("MIPI_DSI_TOP_SW_RESET = 0x%x\n", READ32_REG(MIPI_DSI, MIPI_DSI_TOP_SW_RESET)); 313 DISP_INFO("MIPI_DSI_TOP_CLK_CNTL = 0x%x\n", READ32_REG(MIPI_DSI, MIPI_DSI_TOP_CLK_CNTL)); 314 DISP_INFO("MIPI_DSI_TOP_CNTL = 0x%x\n", READ32_REG(MIPI_DSI, MIPI_DSI_TOP_CNTL)); 315 DISP_INFO("MIPI_DSI_TOP_SUSPEND_CNTL = 0x%x\n", 316 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_SUSPEND_CNTL)); 317 DISP_INFO("MIPI_DSI_TOP_SUSPEND_LINE = 0x%x\n", 318 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_SUSPEND_LINE)); 319 DISP_INFO("MIPI_DSI_TOP_SUSPEND_PIX = 0x%x\n", READ32_REG(MIPI_DSI, MIPI_DSI_TOP_SUSPEND_PIX)); 320 DISP_INFO("MIPI_DSI_TOP_MEAS_CNTL = 0x%x\n", READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_CNTL)); 321 DISP_INFO("MIPI_DSI_TOP_STAT = 0x%x\n", READ32_REG(MIPI_DSI, MIPI_DSI_TOP_STAT)); 322 DISP_INFO("MIPI_DSI_TOP_MEAS_STAT_TE0 = 0x%x\n", 323 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_STAT_TE0)); 324 DISP_INFO("MIPI_DSI_TOP_MEAS_STAT_TE1 = 0x%x\n", 325 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_STAT_TE1)); 326 DISP_INFO("MIPI_DSI_TOP_MEAS_STAT_VS0 = 0x%x\n", 327 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_STAT_VS0)); 328 DISP_INFO("MIPI_DSI_TOP_MEAS_STAT_VS1 = 0x%x\n", 329 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_STAT_VS1)); 330 DISP_INFO("MIPI_DSI_TOP_INTR_CNTL_STAT = 0x%x\n", 331 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_INTR_CNTL_STAT)); 332 DISP_INFO("MIPI_DSI_TOP_MEM_PD = 0x%x\n", READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEM_PD)); 333} 334 335} // namespace astro_display 336