Lines Matching refs:WRITE32_REG
109 WRITE32_REG(VPU, VIU_OSD_BLEND_CTRL,
120 WRITE32_REG(VPU, OSD1_BLEND_SRC_CTRL,
127 WRITE32_REG(VPU, OSD2_BLEND_SRC_CTRL,
135 WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_DATA0,
140 WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_ALPHA,
146 WRITE32_REG(VPU,
150 WRITE32_REG(VPU,
154 WRITE32_REG(VPU, VIU_OSD_BLEND_BLEND0_SIZE,
157 WRITE32_REG(VPU, VIU_OSD_BLEND_BLEND1_SIZE,
162 WRITE32_REG(VPU, VPP_OSD1_IN_SIZE,
166 WRITE32_REG(VPU, VPP_OSD1_BLD_H_SCOPE,
168 WRITE32_REG(VPU, VPP_OSD1_BLD_V_SCOPE,
173 WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W3 , data32);
175 WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W4, data32);
177 WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W1, ((fb_width_ - 1) & 0x1fff) << 16);
178 WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W2, ((fb_height_ - 1) & 0x1fff) << 16);
211 WRITE32_REG(VPU, VPU_VPP_OSD_SC_CTRL0, data32);
214 WRITE32_REG(VPU, VPU_VPP_OSD_SC_CTRL0, 0);
227 WRITE32_REG(VPU, VPU_VPP_OSD_SCI_WH_M1, data32);
229 WRITE32_REG(VPU, VPU_VPP_OSD_SCO_H_START_END, data32);
231 WRITE32_REG(VPU, VPU_VPP_OSD_SCO_V_START_END, data32);
240 WRITE32_REG(VPU, VPU_VPP_OSD_VSC_CTRL0, data32);
248 WRITE32_REG(VPU, VPU_VPP_OSD_HSC_CTRL0, data32);
257 WRITE32_REG(VPU, VPU_VPP_OSD_VSC_INI_PHASE, data32);
264 WRITE32_REG(VPU, VPP_POSTBLEND_H_SIZE, display_width_);
270 WRITE32_REG(VPU, VPP_OFIFO_SIZE, regVal);
280 WRITE32_REG(VPU, VPU_VIU_OSD1_FIFO_CTRL_STAT, regVal);
281 WRITE32_REG(VPU, VPU_VIU_OSD2_FIFO_CTRL_STAT, regVal);
289 WRITE32_REG(VPU, VPU_VIU_OSD1_CTRL_STAT , regVal);
290 WRITE32_REG(VPU, VPU_VIU_OSD2_CTRL_STAT , regVal);
299 WRITE32_REG(VPU, VPU_VPP_OSD_SCALE_COEF, osd_filter_coefs_bicubic[i]);
304 WRITE32_REG(VPU, VPU_VPP_OSD_SCALE_COEF, osd_filter_coefs_bicubic[i]);
308 WRITE32_REG(VPU, VPU_VPP_OSD1_BLD_H_SCOPE, display_width_ - 1);
309 WRITE32_REG(VPU, VPU_VPP_OSD1_BLD_V_SCOPE, display_height_ - 1);
310 WRITE32_REG(VPU, VPU_VPP_OUT_H_V_SIZE, display_width_ << 16 | display_height_);