Lines Matching refs:WRITE32_REG
133 WRITE32_REG(DSI_PHY, MIPI_DSI_PHY_CTRL, PHY_CTRL_TXDDRCLK_EN |
141 WRITE32_REG(DSI_PHY, MIPI_DSI_CLK_TIM,
146 WRITE32_REG(DSI_PHY, MIPI_DSI_CLK_TIM1, dsi_phy_cfg_.clk_pre);
148 WRITE32_REG(DSI_PHY, MIPI_DSI_HS_TIM,
153 WRITE32_REG(DSI_PHY, MIPI_DSI_LP_TIM,
157 WRITE32_REG(DSI_PHY, MIPI_DSI_ANA_UP_TIM, ANA_UP_TIME);
158 WRITE32_REG(DSI_PHY, MIPI_DSI_INIT_TIM, dsi_phy_cfg_.init);
159 WRITE32_REG(DSI_PHY, MIPI_DSI_WAKEUP_TIM, dsi_phy_cfg_.wakeup);
160 WRITE32_REG(DSI_PHY, MIPI_DSI_LPOK_TIM, LPOK_TIME);
161 WRITE32_REG(DSI_PHY, MIPI_DSI_ULPS_CHECK, ULPS_CHECK_TIME);
162 WRITE32_REG(DSI_PHY, MIPI_DSI_LP_WCHDOG, LP_WCHDOG_TIME);
163 WRITE32_REG(DSI_PHY, MIPI_DSI_TURN_WCHDOG, TURN_WCHDOG_TIME);
165 WRITE32_REG(DSI_PHY, MIPI_DSI_CHAN_CTRL, 0);
204 WRITE32_REG(MIPI_DSI, DW_DSI_PWR_UP, PWR_UP_RST);
205 WRITE32_REG(DSI_PHY, MIPI_DSI_CHAN_CTRL, 0x1f);
218 WRITE32_REG(MIPI_DSI, DW_DSI_PWR_UP, PWR_UP_ON);
224 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL1, 0x00010044);
225 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x2);
226 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x0);
227 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL1, 0x00000074);
228 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x2);
229 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x0);
232 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_RSTZ, PHY_RSTZ_PWR_UP);
248 WRITE32_REG(MIPI_DSI, DW_DSI_LPCLK_CTRL, (0x1 << LPCLK_CTRL_AUTOCLKLANE_CTRL) |