display/astro-display/vpu.cpp

118     WRITE32_REG(VPU, VPP_HOLD_LINES, 0x08080808);
126     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1,
128     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2,
130     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF00_01,
132     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF02_10,
134     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF11_12,
136     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF20_21,
138     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF22,
140     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_OFFSET0_1,
142     WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_OFFSET2,
147     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1,
149     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2,
151     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF00_01,
153     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF02_10,
155     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF11_12,
157     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF20_21,
159     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF22,
161     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_OFFSET0_1,
163     WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_OFFSET2,
168     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1,
170     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2,
172     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF00_01,
174     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF02_10,
176     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF11_12,
178     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF20_21,
180     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF22,
182     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_OFFSET0_1,
184     WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_OFFSET2,
188     WRITE32_REG(VPU, DOLBY_PATH_CTRL, 0xf);
194     WRITE32_REG(VPU, VPP_POST2_MATRIX_PRE_OFFSET0_1,
196     WRITE32_REG(VPU, VPP_POST2_MATRIX_PRE_OFFSET2,
198     WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF00_01,
200     WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF02_10,
202     WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF11_12,
204     WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF20_21,
206     WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF22,
208     WRITE32_REG(VPU, VPP_POST2_MATRIX_OFFSET0_1,
210     WRITE32_REG(VPU, VPP_POST2_MATRIX_OFFSET2,
219     WRITE32_REG(VPU, VPP_MATRIX_PRE_OFFSET0_1, 0x0FC00E00);
220     WRITE32_REG(VPU, VPP_MATRIX_PRE_OFFSET2, 0x00000E00);
225     WRITE32_REG(VPU, VPP_MATRIX_COEF00_01, 0x04A80000);
226     WRITE32_REG(VPU, VPP_MATRIX_COEF02_10, 0x072C04A8);
227     WRITE32_REG(VPU, VPP_MATRIX_COEF11_12, 0x1F261DDD);
228     WRITE32_REG(VPU, VPP_MATRIX_COEF20_21, 0x04A80876);
229     WRITE32_REG(VPU, VPP_MATRIX_COEF22, 0x0);
230     WRITE32_REG(VPU, VPP_MATRIX_OFFSET0_1, 0x0);
231     WRITE32_REG(VPU, VPP_MATRIX_OFFSET2, 0x0);
239     WRITE32_REG(HHI, HHI_VPU_CLK_CNTL, ((kVpuMux << 9) | (kVpuDiv << 0)));
244     WRITE32_REG(HHI, HHI_VPU_CLKB_CNTL, ((1 << 8) | (1 << 0)));
248     WRITE32_REG(HHI, HHI_VAPBCLK_CNTL, (1 << 30) | (0 << 9) | (1 << 0));
255     WRITE32_REG(VPU, VPU_RDARB_MODE_L1C1, 0x0);
256     WRITE32_REG(VPU, VPU_RDARB_MODE_L1C2, 0x10000);
257     WRITE32_REG(VPU, VPU_RDARB_MODE_L2C1, 0x900000);
258     WRITE32_REG(VPU, VPU_WRARB_MODE_L2C1, 0x20000);