display/astro-display/aml-dsi-host.cpp

22     WRITE32_REG(MIPI_DSI, DW_DSI_PHY_IF_CFG, PHY_IF_CFG_STOP_WAIT_TIME |
26     WRITE32_REG(MIPI_DSI, DW_DSI_DPI_VCID, MIPI_DSI_VIRTUAL_CHAN_ID);
29     WRITE32_REG(MIPI_DSI, DW_DSI_DPI_COLOR_CODING, DPI_COLOR_CODING(SUPPORTED_DPI_FORMAT));
40     WRITE32_REG(MIPI_DSI, DW_DSI_DPI_CFG_POL, 0);
44         WRITE32_REG(MIPI_DSI, DW_DSI_VID_MODE_CFG,VID_MODE_CFG_LP_EN_ALL |
48         WRITE32_REG(MIPI_DSI, DW_DSI_DPI_LP_CMD_TIM, LP_CMD_TIM_OUTVACT(LPCMD_PKT_SIZE) |
52         WRITE32_REG(MIPI_DSI, DW_DSI_VID_PKT_SIZE, disp_setting.h_active);
54         WRITE32_REG(MIPI_DSI, DW_DSI_VID_NUM_CHUNKS, 0);
55         WRITE32_REG(MIPI_DSI, DW_DSI_VID_NULL_SIZE, 0);
58         WRITE32_REG(MIPI_DSI, DW_DSI_VID_HLINE_TIME, disp_setting.h_period);
59         WRITE32_REG(MIPI_DSI, DW_DSI_VID_HSA_TIME, disp_setting.hsync_width);
60         WRITE32_REG(MIPI_DSI, DW_DSI_VID_HBP_TIME, disp_setting.hsync_bp);
61         WRITE32_REG(MIPI_DSI, DW_DSI_VID_VSA_LINES, disp_setting.vsync_width);
62         WRITE32_REG(MIPI_DSI, DW_DSI_VID_VBP_LINES, disp_setting.vsync_bp);
63         WRITE32_REG(MIPI_DSI, DW_DSI_VID_VACTIVE_LINES, disp_setting.v_active);
64         WRITE32_REG(MIPI_DSI, DW_DSI_VID_VFP_LINES, (disp_setting.v_period -
70     WRITE32_REG(MIPI_DSI, DW_DSI_CLKMGR_CFG,
75     WRITE32_REG(MIPI_DSI, DW_DSI_MODE_CFG, opp);
78     WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TMR_LPCLK_CFG,
81     WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TMR_CFG,
89     WRITE32_REG(HHI, HHI_MIPI_CNTL0, MIPI_CNTL0_CMN_REF_GEN_CTRL(0x29) |
95     WRITE32_REG(HHI, HHI_MIPI_CNTL1, MIPI_CNTL1_DSI_VBG_EN | MIPI_CNTL1_CTL);
96     WRITE32_REG(HHI, HHI_MIPI_CNTL2, MIPI_CNTL2_DEFAULT_VAL); // 4 lane
100     WRITE32_REG(HHI, HHI_MIPI_CNTL0, 0);
101     WRITE32_REG(HHI, HHI_MIPI_CNTL1, 0);
102     WRITE32_REG(HHI, HHI_MIPI_CNTL2, 0);
166     WRITE32_REG(MIPI_DSI, MIPI_DSI_TOP_MEM_PD, 0);
170     WRITE32_REG(MIPI_DSI, DW_DSI_CMD_MODE_CFG,CMD_MODE_CFG_CMD_LP_ALL);
173     WRITE32_REG(MIPI_DSI, DW_DSI_PCKHDL_CFG, PCKHDL_CFG_EN_CRC_ECC);