Searched refs:Hexagon (Results 1 - 24 of 24) sorted by relevance

/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
15 #include "Hexagon.h"
37 /// Constants for Hexagon instructions.
62 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
78 case Hexagon::LDriw:
79 case Hexagon::LDrid:
80 case Hexagon::LDrih:
81 case Hexagon
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H A DHexagonRegisterInfo.cpp1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
16 #include "Hexagon.h"
42 : HexagonGenRegisterInfo(Hexagon::R31),
50 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
53 Hexagon::R16, Hexagon
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H A DHexagonSplitTFRCondSets.cpp30 #include "Hexagon.h"
71 return "Hexagon Split TFRCondSets";
94 case Hexagon::TFR_condset_rr:
95 case Hexagon::TFR_condset_rr_f:
96 case Hexagon::TFR_condset_rr64_f: {
101 if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
102 MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
103 Opc1 = Hexagon::TFR_cPt;
104 Opc2 = Hexagon::TFR_cNotPt;
106 else if (MI->getOpcode() == Hexagon
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H A DHexagonSplitConst32AndConst64.cpp59 return "Hexagon Split Const32s and Const64s";
82 if (Opc == Hexagon::CONST32_set) {
87 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
89 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
95 else if (Opc == Hexagon::CONST32_set_jt) {
100 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
102 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
108 else if (Opc == Hexagon::CONST32_Label) {
113 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
115 TII->get(Hexagon
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H A DHexagonVarargsCallingConvention.h53 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
54 Hexagon::R5
66 Hexagon::D0, Hexagon::D1, Hexagon::D2
109 Hexagon
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H A DHexagonNewValueJump.cpp1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
10 // This implements NewValueJump pass in Hexagon.
40 #include "Hexagon.h"
85 return "Hexagon NewValueJump";
101 "Hexagon NewValueJump", false, false)
104 "Hexagon NewValueJump", false, false)
180 if (MII->getOpcode() == Hexagon::CALLv3)
199 // The following pseudo Hexagon instructions sets "use" and "def"
203 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
204 MII->getOpcode() == Hexagon
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H A DHexagonExpandPredSpillCode.cpp9 // The Hexagon processor has no instructions that load or store predicate
20 #include "Hexagon.h"
64 return "Hexagon Expand Predicate Spill Code";
86 if (Opc == Hexagon::STriw_pred) {
94 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
96 if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
97 if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
99 TII->get(Hexagon::CONST32_Int_Real),
101 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
104 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon
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H A DHexagonCFGOptimizer.cpp10 #include "Hexagon.h"
52 return "Hexagon CFG Optimizer";
61 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f)
62 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t);
67 return (Opc == Hexagon::JMP);
77 case Hexagon::JMP_t:
78 NewOpcode = Hexagon::JMP_f;
81 case Hexagon
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H A DHexagonMachineFunctionInfo.h1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
18 namespace Hexagon { namespace in namespace:llvm
24 /// Hexagon target-specific information for each MachineFunction.
59 PacketInfo[MI] |= Hexagon::StartPacket;
62 PacketInfo[MI] |= Hexagon::EndPacket;
66 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
70 (PacketInfo.find(MI)->second & Hexagon::EndPacket));
H A DHexagonPeephole.cpp1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
39 #include "Hexagon.h"
95 return "Hexagon optimize redundant zero and size extends";
109 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
137 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
156 MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
173 if (MI->getOpcode() == Hexagon::LSRd_ri) {
183 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
188 (MI->getOpcode() == Hexagon::NOT_p)) {
212 if (Src.getSubReg() != Hexagon
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H A DHexagonFixupHwLoops.cpp25 #include "Hexagon.h"
45 const char *getPassName() const { return "Hexagon Hardware Loop Fixup"; }
73 "Hexagon Hardware Loops Fixup", false, false)
82 return MI->getOpcode() == Hexagon::LOOP0_r ||
83 MI->getOpcode() == Hexagon::LOOP0_i;
93 /// \brief For Hexagon, if the loop label is to far from the
164 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
169 BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
173 BuildMI(*MBB, MII, DL, TII->get(Hexagon
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H A DHexagonFrameLowering.cpp12 #include "Hexagon.h"
42 cl::desc("Disable Dealloc Return for Hexagon target"));
103 assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) &&
122 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
125 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
127 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
132 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
142 return RetOpcode == Hexagon::TCRETURNtg || RetOpcode == Hexagon::TCRETURNtext;
159 if (MBBI->getOpcode() == Hexagon
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H A DHexagonCopyToCombine.cpp1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
31 #include "Hexagon.h"
77 return "Hexagon Copy-To-Combine Pass";
112 "Hexagon Copy-To-Combine Pass", false, false)
118 case Hexagon::TFR: {
124 return Hexagon::IntRegsRegClass.contains(DestReg) &&
125 Hexagon::IntRegsRegClass.contains(SrcReg);
128 case Hexagon::TFRI: {
135 return Hexagon::IntRegsRegClass.contains(DestReg) &&
139 case Hexagon
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H A DHexagonRegisterInfo.h1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
H A DHexagonISelDAGToDAG.cpp1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
10 // This file defines an instruction selector for the Hexagon target.
15 #include "Hexagon.h"
42 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
47 /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
82 return "Hexagon DAG->DAG Pattern Instruction Selection";
179 /// Hexagon-specific DAG, ready for instruction scheduling.
187 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
322 return Hexagon
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H A DHexagonHardwareLoops.cpp10 // This pass identifies loops where we can generate the Hexagon hardware
43 #include "Hexagon.h"
83 const char *getPassName() const { return "Hexagon Hardware Loops"; }
278 "Hexagon Hardware Loops", false, false)
282 "Hexagon Hardware Loops", false, false)
287 return MI->getOpcode() == Hexagon::LOOP0_r ||
288 MI->getOpcode() == Hexagon::LOOP0_i;
297 DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
357 bool isAdd = (UpdOpc == Hexagon::ADD_ri);
540 case Hexagon
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H A DHexagonVLIWPacketizer.cpp44 #include "Hexagon.h"
84 return "Hexagon Packetizer";
174 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
180 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
268 return ((MI->getOpcode() == Hexagon::CALLR) ||
269 (MI->getOpcode() == Hexagon::CALLRv3));
277 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
295 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
307 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
342 if (RC == &Hexagon
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H A DHexagonISelLowering.cpp1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
44 cl::desc("Control jump table emission on Hexagon target"));
61 // Implement calling convention for Hexagon.
186 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
187 Hexagon
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H A DHexagonCallingConvLower.cpp17 #include "Hexagon.h"
98 // For Hexagon, Return small structures in registers.
101 unsigned Reg = Hexagon::R0;
107 unsigned Reg = Hexagon::D0;
H A DHexagonAsmPrinter.cpp1 //===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===//
11 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
17 #include "Hexagon.h"
62 cl::desc("Insert falign after call instruction for Hexagon target"));
140 // Hexagon never has a prefix.
196 /// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to
232 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
10 // This file provides Hexagon specific target descriptions.
45 InitHexagonMCRegisterInfo(X, Hexagon::R0);
63 0, Hexagon::R30, 0);
/freebsd-9.3-release/contrib/llvm/tools/clang/include/clang/Basic/
H A DTargetBuiltins.h116 /// \brief Hexagon builtins
117 namespace Hexagon { namespace in namespace:clang
/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/InstPrinter/
H A DHexagonInstPrinter.cpp1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
10 // This class prints an Hexagon MCInst to a .s file.
16 #include "Hexagon.h"
50 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
60 Nop.setOpcode (Hexagon::NOP);
/freebsd-9.3-release/contrib/llvm/tools/clang/lib/Basic/
H A DTargets.cpp4245 // Hexagon abstract base class
4266 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;

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