1//===--- Targets.cpp - Implement -arch option and targets -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements construction of a TargetInfo object from a 11// target triple. 12// 13//===----------------------------------------------------------------------===// 14 15#include "clang/Basic/TargetInfo.h" 16#include "clang/Basic/Builtins.h" 17#include "clang/Basic/Diagnostic.h" 18#include "clang/Basic/LangOptions.h" 19#include "clang/Basic/MacroBuilder.h" 20#include "clang/Basic/TargetBuiltins.h" 21#include "clang/Basic/TargetOptions.h" 22#include "llvm/ADT/APFloat.h" 23#include "llvm/ADT/OwningPtr.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/ADT/StringRef.h" 26#include "llvm/ADT/StringSwitch.h" 27#include "llvm/ADT/Triple.h" 28#include "llvm/IR/Type.h" 29#include "llvm/MC/MCSectionMachO.h" 30#include "llvm/Support/ErrorHandling.h" 31#include <algorithm> 32using namespace clang; 33 34//===----------------------------------------------------------------------===// 35// Common code shared among targets. 36//===----------------------------------------------------------------------===// 37 38/// DefineStd - Define a macro name and standard variants. For example if 39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40/// when in GNU mode. 41static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55} 56 57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63} 64 65//===----------------------------------------------------------------------===// 66// Defines specific to certain operating systems. 67//===----------------------------------------------------------------------===// 68 69namespace { 70template<typename TgtInfo> 71class OSTargetInfo : public TgtInfo { 72protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83}; 84} // end anonymous namespace 85 86 87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // If there's an environment specified in the triple, that means we're dealing 142 // with an embedded variant of some sort and don't want the platform 143 // version-min defines, so only add them if there's not one. 144 if (Triple.getEnvironmentName().empty()) { 145 // Set the appropriate OS version define. 146 if (Triple.isiOS()) { 147 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 148 char Str[6]; 149 Str[0] = '0' + Maj; 150 Str[1] = '0' + (Min / 10); 151 Str[2] = '0' + (Min % 10); 152 Str[3] = '0' + (Rev / 10); 153 Str[4] = '0' + (Rev % 10); 154 Str[5] = '\0'; 155 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 156 Str); 157 } else { 158 // Note that the Driver allows versions which aren't representable in the 159 // define (because we only get a single digit for the minor and micro 160 // revision numbers). So, we limit them to the maximum representable 161 // version. 162 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 164 char Str[5]; 165 Str[0] = '0' + (Maj / 10); 166 Str[1] = '0' + (Maj % 10); 167 Str[2] = '0' + std::min(Min, 9U); 168 Str[3] = '0' + std::min(Rev, 9U); 169 Str[4] = '\0'; 170 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 171 } 172 } 173 174 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 175} 176 177namespace { 178template<typename Target> 179class DarwinTargetInfo : public OSTargetInfo<Target> { 180protected: 181 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 182 MacroBuilder &Builder) const { 183 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 184 this->PlatformMinVersion); 185 } 186 187public: 188 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 189 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 190 this->MCountName = "\01mcount"; 191 } 192 193 virtual std::string isValidSectionSpecifier(StringRef SR) const { 194 // Let MCSectionMachO validate this. 195 StringRef Segment, Section; 196 unsigned TAA, StubSize; 197 bool HasTAA; 198 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 199 TAA, HasTAA, StubSize); 200 } 201 202 virtual const char *getStaticInitSectionSpecifier() const { 203 // FIXME: We should return 0 when building kexts. 204 return "__TEXT,__StaticInit,regular,pure_instructions"; 205 } 206 207 /// Darwin does not support protected visibility. Darwin's "default" 208 /// is very similar to ELF's "protected"; Darwin requires a "weak" 209 /// attribute on declarations that can be dynamically replaced. 210 virtual bool hasProtectedVisibility() const { 211 return false; 212 } 213}; 214 215 216// DragonFlyBSD Target 217template<typename Target> 218class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 219protected: 220 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 221 MacroBuilder &Builder) const { 222 // DragonFly defines; list based off of gcc output 223 Builder.defineMacro("__DragonFly__"); 224 Builder.defineMacro("__DragonFly_cc_version", "100001"); 225 Builder.defineMacro("__ELF__"); 226 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 227 Builder.defineMacro("__tune_i386__"); 228 DefineStd(Builder, "unix", Opts); 229 } 230public: 231 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 232 : OSTargetInfo<Target>(Triple) { 233 this->UserLabelPrefix = ""; 234 235 switch (Triple.getArch()) { 236 default: 237 case llvm::Triple::x86: 238 case llvm::Triple::x86_64: 239 this->MCountName = ".mcount"; 240 break; 241 } 242 } 243}; 244 245// FreeBSD Target 246template<typename Target> 247class FreeBSDTargetInfo : public OSTargetInfo<Target> { 248protected: 249 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 250 MacroBuilder &Builder) const { 251 // FreeBSD defines; list based off of gcc output 252 253 unsigned Release = Triple.getOSMajorVersion(); 254 if (Release == 0U) 255 Release = 8; 256 257 Builder.defineMacro("__FreeBSD__", Twine(Release)); 258 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 259 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 260 DefineStd(Builder, "unix", Opts); 261 Builder.defineMacro("__ELF__"); 262 263 // On FreeBSD, wchar_t contains the number of the code point as 264 // used by the character set of the locale. These character sets are 265 // not necessarily a superset of ASCII. 266 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 267 } 268public: 269 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 270 this->UserLabelPrefix = ""; 271 272 switch (Triple.getArch()) { 273 default: 274 case llvm::Triple::x86: 275 case llvm::Triple::x86_64: 276 this->MCountName = ".mcount"; 277 break; 278 case llvm::Triple::mips: 279 case llvm::Triple::mipsel: 280 case llvm::Triple::ppc: 281 case llvm::Triple::ppc64: 282 case llvm::Triple::ppc64le: 283 this->MCountName = "_mcount"; 284 break; 285 case llvm::Triple::arm: 286 this->MCountName = "__mcount"; 287 break; 288 } 289 } 290}; 291 292// GNU/kFreeBSD Target 293template<typename Target> 294class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 295protected: 296 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 297 MacroBuilder &Builder) const { 298 // GNU/kFreeBSD defines; list based off of gcc output 299 300 DefineStd(Builder, "unix", Opts); 301 Builder.defineMacro("__FreeBSD_kernel__"); 302 Builder.defineMacro("__GLIBC__"); 303 Builder.defineMacro("__ELF__"); 304 if (Opts.POSIXThreads) 305 Builder.defineMacro("_REENTRANT"); 306 if (Opts.CPlusPlus) 307 Builder.defineMacro("_GNU_SOURCE"); 308 } 309public: 310 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 311 this->UserLabelPrefix = ""; 312 } 313}; 314 315// Minix Target 316template<typename Target> 317class MinixTargetInfo : public OSTargetInfo<Target> { 318protected: 319 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 320 MacroBuilder &Builder) const { 321 // Minix defines 322 323 Builder.defineMacro("__minix", "3"); 324 Builder.defineMacro("_EM_WSIZE", "4"); 325 Builder.defineMacro("_EM_PSIZE", "4"); 326 Builder.defineMacro("_EM_SSIZE", "2"); 327 Builder.defineMacro("_EM_LSIZE", "4"); 328 Builder.defineMacro("_EM_FSIZE", "4"); 329 Builder.defineMacro("_EM_DSIZE", "8"); 330 Builder.defineMacro("__ELF__"); 331 DefineStd(Builder, "unix", Opts); 332 } 333public: 334 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 335 this->UserLabelPrefix = ""; 336 } 337}; 338 339// Linux target 340template<typename Target> 341class LinuxTargetInfo : public OSTargetInfo<Target> { 342protected: 343 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 344 MacroBuilder &Builder) const { 345 // Linux defines; list based off of gcc output 346 DefineStd(Builder, "unix", Opts); 347 DefineStd(Builder, "linux", Opts); 348 Builder.defineMacro("__gnu_linux__"); 349 Builder.defineMacro("__ELF__"); 350 if (Triple.getEnvironment() == llvm::Triple::Android) 351 Builder.defineMacro("__ANDROID__", "1"); 352 if (Opts.POSIXThreads) 353 Builder.defineMacro("_REENTRANT"); 354 if (Opts.CPlusPlus) 355 Builder.defineMacro("_GNU_SOURCE"); 356 } 357public: 358 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 359 this->UserLabelPrefix = ""; 360 this->WIntType = TargetInfo::UnsignedInt; 361 362 switch (Triple.getArch()) { 363 default: 364 break; 365 case llvm::Triple::ppc: 366 case llvm::Triple::ppc64: 367 case llvm::Triple::ppc64le: 368 this->MCountName = "_mcount"; 369 break; 370 } 371 } 372 373 virtual const char *getStaticInitSectionSpecifier() const { 374 return ".text.startup"; 375 } 376}; 377 378// NetBSD Target 379template<typename Target> 380class NetBSDTargetInfo : public OSTargetInfo<Target> { 381protected: 382 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const { 384 // NetBSD defines; list based off of gcc output 385 Builder.defineMacro("__NetBSD__"); 386 Builder.defineMacro("__unix__"); 387 Builder.defineMacro("__ELF__"); 388 if (Opts.POSIXThreads) 389 Builder.defineMacro("_POSIX_THREADS"); 390 } 391public: 392 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 393 this->UserLabelPrefix = ""; 394 } 395}; 396 397// OpenBSD Target 398template<typename Target> 399class OpenBSDTargetInfo : public OSTargetInfo<Target> { 400protected: 401 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 402 MacroBuilder &Builder) const { 403 // OpenBSD defines; list based off of gcc output 404 405 Builder.defineMacro("__OpenBSD__"); 406 DefineStd(Builder, "unix", Opts); 407 Builder.defineMacro("__ELF__"); 408 if (Opts.POSIXThreads) 409 Builder.defineMacro("_REENTRANT"); 410 } 411public: 412 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 413 this->UserLabelPrefix = ""; 414 this->TLSSupported = false; 415 416 switch (Triple.getArch()) { 417 default: 418 case llvm::Triple::x86: 419 case llvm::Triple::x86_64: 420 case llvm::Triple::arm: 421 case llvm::Triple::sparc: 422 this->MCountName = "__mcount"; 423 break; 424 case llvm::Triple::mips64: 425 case llvm::Triple::mips64el: 426 case llvm::Triple::ppc: 427 case llvm::Triple::sparcv9: 428 this->MCountName = "_mcount"; 429 break; 430 } 431 } 432}; 433 434// Bitrig Target 435template<typename Target> 436class BitrigTargetInfo : public OSTargetInfo<Target> { 437protected: 438 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 439 MacroBuilder &Builder) const { 440 // Bitrig defines; list based off of gcc output 441 442 Builder.defineMacro("__Bitrig__"); 443 DefineStd(Builder, "unix", Opts); 444 Builder.defineMacro("__ELF__"); 445 if (Opts.POSIXThreads) 446 Builder.defineMacro("_REENTRANT"); 447 } 448public: 449 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 450 this->UserLabelPrefix = ""; 451 this->TLSSupported = false; 452 this->MCountName = "__mcount"; 453 } 454}; 455 456// PSP Target 457template<typename Target> 458class PSPTargetInfo : public OSTargetInfo<Target> { 459protected: 460 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 461 MacroBuilder &Builder) const { 462 // PSP defines; list based on the output of the pspdev gcc toolchain. 463 Builder.defineMacro("PSP"); 464 Builder.defineMacro("_PSP"); 465 Builder.defineMacro("__psp__"); 466 Builder.defineMacro("__ELF__"); 467 } 468public: 469 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 470 this->UserLabelPrefix = ""; 471 } 472}; 473 474// PS3 PPU Target 475template<typename Target> 476class PS3PPUTargetInfo : public OSTargetInfo<Target> { 477protected: 478 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 479 MacroBuilder &Builder) const { 480 // PS3 PPU defines. 481 Builder.defineMacro("__PPC__"); 482 Builder.defineMacro("__PPU__"); 483 Builder.defineMacro("__CELLOS_LV2__"); 484 Builder.defineMacro("__ELF__"); 485 Builder.defineMacro("__LP32__"); 486 Builder.defineMacro("_ARCH_PPC64"); 487 Builder.defineMacro("__powerpc64__"); 488 } 489public: 490 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 491 this->UserLabelPrefix = ""; 492 this->LongWidth = this->LongAlign = 32; 493 this->PointerWidth = this->PointerAlign = 32; 494 this->IntMaxType = TargetInfo::SignedLongLong; 495 this->UIntMaxType = TargetInfo::UnsignedLongLong; 496 this->Int64Type = TargetInfo::SignedLongLong; 497 this->SizeType = TargetInfo::UnsignedInt; 498 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 499 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 500 } 501}; 502 503// FIXME: Need a real SPU target. 504// PS3 SPU Target 505template<typename Target> 506class PS3SPUTargetInfo : public OSTargetInfo<Target> { 507protected: 508 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const { 510 // PS3 PPU defines. 511 Builder.defineMacro("__SPU__"); 512 Builder.defineMacro("__ELF__"); 513 } 514public: 515 PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 516 this->UserLabelPrefix = ""; 517 } 518}; 519 520// AuroraUX target 521template<typename Target> 522class AuroraUXTargetInfo : public OSTargetInfo<Target> { 523protected: 524 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const { 526 DefineStd(Builder, "sun", Opts); 527 DefineStd(Builder, "unix", Opts); 528 Builder.defineMacro("__ELF__"); 529 Builder.defineMacro("__svr4__"); 530 Builder.defineMacro("__SVR4"); 531 } 532public: 533 AuroraUXTargetInfo(const llvm::Triple &Triple) 534 : OSTargetInfo<Target>(Triple) { 535 this->UserLabelPrefix = ""; 536 this->WCharType = this->SignedLong; 537 // FIXME: WIntType should be SignedLong 538 } 539}; 540 541// Solaris target 542template<typename Target> 543class SolarisTargetInfo : public OSTargetInfo<Target> { 544protected: 545 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 546 MacroBuilder &Builder) const { 547 DefineStd(Builder, "sun", Opts); 548 DefineStd(Builder, "unix", Opts); 549 Builder.defineMacro("__ELF__"); 550 Builder.defineMacro("__svr4__"); 551 Builder.defineMacro("__SVR4"); 552 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 553 // newer, but to 500 for everything else. feature_test.h has a check to 554 // ensure that you are not using C99 with an old version of X/Open or C89 555 // with a new version. 556 if (Opts.C99 || Opts.C11) 557 Builder.defineMacro("_XOPEN_SOURCE", "600"); 558 else 559 Builder.defineMacro("_XOPEN_SOURCE", "500"); 560 if (Opts.CPlusPlus) 561 Builder.defineMacro("__C99FEATURES__"); 562 Builder.defineMacro("_LARGEFILE_SOURCE"); 563 Builder.defineMacro("_LARGEFILE64_SOURCE"); 564 Builder.defineMacro("__EXTENSIONS__"); 565 Builder.defineMacro("_REENTRANT"); 566 } 567public: 568 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 569 this->UserLabelPrefix = ""; 570 this->WCharType = this->SignedInt; 571 // FIXME: WIntType should be SignedLong 572 } 573}; 574 575// Windows target 576template<typename Target> 577class WindowsTargetInfo : public OSTargetInfo<Target> { 578protected: 579 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 580 MacroBuilder &Builder) const { 581 Builder.defineMacro("_WIN32"); 582 } 583 void getVisualStudioDefines(const LangOptions &Opts, 584 MacroBuilder &Builder) const { 585 if (Opts.CPlusPlus) { 586 if (Opts.RTTI) 587 Builder.defineMacro("_CPPRTTI"); 588 589 if (Opts.Exceptions) 590 Builder.defineMacro("_CPPUNWIND"); 591 } 592 593 if (!Opts.CharIsSigned) 594 Builder.defineMacro("_CHAR_UNSIGNED"); 595 596 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 597 // but it works for now. 598 if (Opts.POSIXThreads) 599 Builder.defineMacro("_MT"); 600 601 if (Opts.MSCVersion != 0) 602 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 603 604 if (Opts.MicrosoftExt) { 605 Builder.defineMacro("_MSC_EXTENSIONS"); 606 607 if (Opts.CPlusPlus11) { 608 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 609 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 610 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 611 } 612 } 613 614 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 615 } 616 617public: 618 WindowsTargetInfo(const llvm::Triple &Triple) 619 : OSTargetInfo<Target>(Triple) {} 620}; 621 622template <typename Target> 623class NaClTargetInfo : public OSTargetInfo<Target> { 624protected: 625 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 626 MacroBuilder &Builder) const { 627 if (Opts.POSIXThreads) 628 Builder.defineMacro("_REENTRANT"); 629 if (Opts.CPlusPlus) 630 Builder.defineMacro("_GNU_SOURCE"); 631 632 DefineStd(Builder, "unix", Opts); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__native_client__"); 635 } 636 637public: 638 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 639 this->UserLabelPrefix = ""; 640 this->LongAlign = 32; 641 this->LongWidth = 32; 642 this->PointerAlign = 32; 643 this->PointerWidth = 32; 644 this->IntMaxType = TargetInfo::SignedLongLong; 645 this->UIntMaxType = TargetInfo::UnsignedLongLong; 646 this->Int64Type = TargetInfo::SignedLongLong; 647 this->DoubleAlign = 64; 648 this->LongDoubleWidth = 64; 649 this->LongDoubleAlign = 64; 650 this->SizeType = TargetInfo::UnsignedInt; 651 this->PtrDiffType = TargetInfo::SignedInt; 652 this->IntPtrType = TargetInfo::SignedInt; 653 // RegParmMax is inherited from the underlying architecture 654 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 655 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 656 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 657 } 658 virtual typename Target::CallingConvCheckResult checkCallingConvention( 659 CallingConv CC) const { 660 return CC == CC_PnaclCall ? Target::CCCR_OK : 661 Target::checkCallingConvention(CC); 662 } 663}; 664} // end anonymous namespace. 665 666//===----------------------------------------------------------------------===// 667// Specific target implementations. 668//===----------------------------------------------------------------------===// 669 670namespace { 671// PPC abstract base class 672class PPCTargetInfo : public TargetInfo { 673 static const Builtin::Info BuiltinInfo[]; 674 static const char * const GCCRegNames[]; 675 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 676 std::string CPU; 677 678 // Target cpu features. 679 bool HasVSX; 680 681public: 682 PPCTargetInfo(const llvm::Triple &Triple) 683 : TargetInfo(Triple), HasVSX(false) { 684 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 685 LongDoubleWidth = LongDoubleAlign = 128; 686 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 687 } 688 689 /// \brief Flags for architecture specific defines. 690 typedef enum { 691 ArchDefineNone = 0, 692 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 693 ArchDefinePpcgr = 1 << 1, 694 ArchDefinePpcsq = 1 << 2, 695 ArchDefine440 = 1 << 3, 696 ArchDefine603 = 1 << 4, 697 ArchDefine604 = 1 << 5, 698 ArchDefinePwr4 = 1 << 6, 699 ArchDefinePwr5 = 1 << 7, 700 ArchDefinePwr5x = 1 << 8, 701 ArchDefinePwr6 = 1 << 9, 702 ArchDefinePwr6x = 1 << 10, 703 ArchDefinePwr7 = 1 << 11, 704 ArchDefineA2 = 1 << 12, 705 ArchDefineA2q = 1 << 13 706 } ArchDefineTypes; 707 708 // Note: GCC recognizes the following additional cpus: 709 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 710 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 711 // titan, rs64. 712 virtual bool setCPU(const std::string &Name) { 713 bool CPUKnown = llvm::StringSwitch<bool>(Name) 714 .Case("generic", true) 715 .Case("440", true) 716 .Case("450", true) 717 .Case("601", true) 718 .Case("602", true) 719 .Case("603", true) 720 .Case("603e", true) 721 .Case("603ev", true) 722 .Case("604", true) 723 .Case("604e", true) 724 .Case("620", true) 725 .Case("630", true) 726 .Case("g3", true) 727 .Case("7400", true) 728 .Case("g4", true) 729 .Case("7450", true) 730 .Case("g4+", true) 731 .Case("750", true) 732 .Case("970", true) 733 .Case("g5", true) 734 .Case("a2", true) 735 .Case("a2q", true) 736 .Case("e500mc", true) 737 .Case("e5500", true) 738 .Case("power3", true) 739 .Case("pwr3", true) 740 .Case("power4", true) 741 .Case("pwr4", true) 742 .Case("power5", true) 743 .Case("pwr5", true) 744 .Case("power5x", true) 745 .Case("pwr5x", true) 746 .Case("power6", true) 747 .Case("pwr6", true) 748 .Case("power6x", true) 749 .Case("pwr6x", true) 750 .Case("power7", true) 751 .Case("pwr7", true) 752 .Case("powerpc", true) 753 .Case("ppc", true) 754 .Case("powerpc64", true) 755 .Case("ppc64", true) 756 .Case("powerpc64le", true) 757 .Case("ppc64le", true) 758 .Default(false); 759 760 if (CPUKnown) 761 CPU = Name; 762 763 return CPUKnown; 764 } 765 766 virtual void getTargetBuiltins(const Builtin::Info *&Records, 767 unsigned &NumRecords) const { 768 Records = BuiltinInfo; 769 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 770 } 771 772 virtual bool isCLZForZeroUndef() const { return false; } 773 774 virtual void getTargetDefines(const LangOptions &Opts, 775 MacroBuilder &Builder) const; 776 777 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 778 779 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 780 DiagnosticsEngine &Diags); 781 virtual bool hasFeature(StringRef Feature) const; 782 783 virtual void getGCCRegNames(const char * const *&Names, 784 unsigned &NumNames) const; 785 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 786 unsigned &NumAliases) const; 787 virtual bool validateAsmConstraint(const char *&Name, 788 TargetInfo::ConstraintInfo &Info) const { 789 switch (*Name) { 790 default: return false; 791 case 'O': // Zero 792 break; 793 case 'b': // Base register 794 case 'f': // Floating point register 795 Info.setAllowsRegister(); 796 break; 797 // FIXME: The following are added to allow parsing. 798 // I just took a guess at what the actions should be. 799 // Also, is more specific checking needed? I.e. specific registers? 800 case 'd': // Floating point register (containing 64-bit value) 801 case 'v': // Altivec vector register 802 Info.setAllowsRegister(); 803 break; 804 case 'w': 805 switch (Name[1]) { 806 case 'd':// VSX vector register to hold vector double data 807 case 'f':// VSX vector register to hold vector float data 808 case 's':// VSX vector register to hold scalar float data 809 case 'a':// Any VSX register 810 break; 811 default: 812 return false; 813 } 814 Info.setAllowsRegister(); 815 Name++; // Skip over 'w'. 816 break; 817 case 'h': // `MQ', `CTR', or `LINK' register 818 case 'q': // `MQ' register 819 case 'c': // `CTR' register 820 case 'l': // `LINK' register 821 case 'x': // `CR' register (condition register) number 0 822 case 'y': // `CR' register (condition register) 823 case 'z': // `XER[CA]' carry bit (part of the XER register) 824 Info.setAllowsRegister(); 825 break; 826 case 'I': // Signed 16-bit constant 827 case 'J': // Unsigned 16-bit constant shifted left 16 bits 828 // (use `L' instead for SImode constants) 829 case 'K': // Unsigned 16-bit constant 830 case 'L': // Signed 16-bit constant shifted left 16 bits 831 case 'M': // Constant larger than 31 832 case 'N': // Exact power of 2 833 case 'P': // Constant whose negation is a signed 16-bit constant 834 case 'G': // Floating point constant that can be loaded into a 835 // register with one instruction per word 836 case 'H': // Integer/Floating point constant that can be loaded 837 // into a register using three instructions 838 break; 839 case 'm': // Memory operand. Note that on PowerPC targets, m can 840 // include addresses that update the base register. It 841 // is therefore only safe to use `m' in an asm statement 842 // if that asm statement accesses the operand exactly once. 843 // The asm statement must also use `%U<opno>' as a 844 // placeholder for the "update" flag in the corresponding 845 // load or store instruction. For example: 846 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 847 // is correct but: 848 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 849 // is not. Use es rather than m if you don't want the base 850 // register to be updated. 851 case 'e': 852 if (Name[1] != 's') 853 return false; 854 // es: A "stable" memory operand; that is, one which does not 855 // include any automodification of the base register. Unlike 856 // `m', this constraint can be used in asm statements that 857 // might access the operand several times, or that might not 858 // access it at all. 859 Info.setAllowsMemory(); 860 Name++; // Skip over 'e'. 861 break; 862 case 'Q': // Memory operand that is an offset from a register (it is 863 // usually better to use `m' or `es' in asm statements) 864 case 'Z': // Memory operand that is an indexed or indirect from a 865 // register (it is usually better to use `m' or `es' in 866 // asm statements) 867 Info.setAllowsMemory(); 868 Info.setAllowsRegister(); 869 break; 870 case 'R': // AIX TOC entry 871 case 'a': // Address operand that is an indexed or indirect from a 872 // register (`p' is preferable for asm statements) 873 case 'S': // Constant suitable as a 64-bit mask operand 874 case 'T': // Constant suitable as a 32-bit mask operand 875 case 'U': // System V Release 4 small data area reference 876 case 't': // AND masks that can be performed by two rldic{l, r} 877 // instructions 878 case 'W': // Vector constant that does not require memory 879 case 'j': // Vector constant that is all zeros. 880 break; 881 // End FIXME. 882 } 883 return true; 884 } 885 virtual const char *getClobbers() const { 886 return ""; 887 } 888 int getEHDataRegisterNumber(unsigned RegNo) const { 889 if (RegNo == 0) return 3; 890 if (RegNo == 1) return 4; 891 return -1; 892 } 893}; 894 895const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 896#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 897#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 898 ALL_LANGUAGES }, 899#include "clang/Basic/BuiltinsPPC.def" 900}; 901 902 /// handleTargetFeatures - Perform initialization based on the user 903/// configured set of features. 904bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 905 DiagnosticsEngine &Diags) { 906 // Remember the maximum enabled sselevel. 907 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 908 // Ignore disabled features. 909 if (Features[i][0] == '-') 910 continue; 911 912 StringRef Feature = StringRef(Features[i]).substr(1); 913 914 if (Feature == "vsx") { 915 HasVSX = true; 916 continue; 917 } 918 919 // TODO: Finish this list and add an assert that we've handled them 920 // all. 921 } 922 923 return true; 924} 925 926/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 927/// #defines that are not tied to a specific subtarget. 928void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 929 MacroBuilder &Builder) const { 930 // Target identification. 931 Builder.defineMacro("__ppc__"); 932 Builder.defineMacro("__PPC__"); 933 Builder.defineMacro("_ARCH_PPC"); 934 Builder.defineMacro("__powerpc__"); 935 Builder.defineMacro("__POWERPC__"); 936 if (PointerWidth == 64) { 937 Builder.defineMacro("_ARCH_PPC64"); 938 Builder.defineMacro("__powerpc64__"); 939 Builder.defineMacro("__ppc64__"); 940 Builder.defineMacro("__PPC64__"); 941 } 942 943 // Target properties. 944 if (getTriple().getArch() == llvm::Triple::ppc64le) { 945 Builder.defineMacro("_LITTLE_ENDIAN"); 946 Builder.defineMacro("__LITTLE_ENDIAN__"); 947 } else { 948 if (getTriple().getOS() != llvm::Triple::NetBSD && 949 getTriple().getOS() != llvm::Triple::OpenBSD) 950 Builder.defineMacro("_BIG_ENDIAN"); 951 Builder.defineMacro("__BIG_ENDIAN__"); 952 } 953 954 // Subtarget options. 955 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 956 Builder.defineMacro("__REGISTER_PREFIX__", ""); 957 958 // FIXME: Should be controlled by command line option. 959 if (LongDoubleWidth == 128) 960 Builder.defineMacro("__LONG_DOUBLE_128__"); 961 962 if (Opts.AltiVec) { 963 Builder.defineMacro("__VEC__", "10206"); 964 Builder.defineMacro("__ALTIVEC__"); 965 } 966 967 // CPU identification. 968 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 969 .Case("440", ArchDefineName) 970 .Case("450", ArchDefineName | ArchDefine440) 971 .Case("601", ArchDefineName) 972 .Case("602", ArchDefineName | ArchDefinePpcgr) 973 .Case("603", ArchDefineName | ArchDefinePpcgr) 974 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 975 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 976 .Case("604", ArchDefineName | ArchDefinePpcgr) 977 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 978 .Case("620", ArchDefineName | ArchDefinePpcgr) 979 .Case("630", ArchDefineName | ArchDefinePpcgr) 980 .Case("7400", ArchDefineName | ArchDefinePpcgr) 981 .Case("7450", ArchDefineName | ArchDefinePpcgr) 982 .Case("750", ArchDefineName | ArchDefinePpcgr) 983 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 984 | ArchDefinePpcsq) 985 .Case("a2", ArchDefineA2) 986 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 987 .Case("pwr3", ArchDefinePpcgr) 988 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 989 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 990 | ArchDefinePpcsq) 991 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 992 | ArchDefinePpcgr | ArchDefinePpcsq) 993 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 994 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 995 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 996 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 997 | ArchDefinePpcsq) 998 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 999 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1000 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1001 .Case("power3", ArchDefinePpcgr) 1002 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1003 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1004 | ArchDefinePpcsq) 1005 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1006 | ArchDefinePpcgr | ArchDefinePpcsq) 1007 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1008 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1009 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1010 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1011 | ArchDefinePpcsq) 1012 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1013 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1014 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1015 .Default(ArchDefineNone); 1016 1017 if (defs & ArchDefineName) 1018 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1019 if (defs & ArchDefinePpcgr) 1020 Builder.defineMacro("_ARCH_PPCGR"); 1021 if (defs & ArchDefinePpcsq) 1022 Builder.defineMacro("_ARCH_PPCSQ"); 1023 if (defs & ArchDefine440) 1024 Builder.defineMacro("_ARCH_440"); 1025 if (defs & ArchDefine603) 1026 Builder.defineMacro("_ARCH_603"); 1027 if (defs & ArchDefine604) 1028 Builder.defineMacro("_ARCH_604"); 1029 if (defs & ArchDefinePwr4) 1030 Builder.defineMacro("_ARCH_PWR4"); 1031 if (defs & ArchDefinePwr5) 1032 Builder.defineMacro("_ARCH_PWR5"); 1033 if (defs & ArchDefinePwr5x) 1034 Builder.defineMacro("_ARCH_PWR5X"); 1035 if (defs & ArchDefinePwr6) 1036 Builder.defineMacro("_ARCH_PWR6"); 1037 if (defs & ArchDefinePwr6x) 1038 Builder.defineMacro("_ARCH_PWR6X"); 1039 if (defs & ArchDefinePwr7) 1040 Builder.defineMacro("_ARCH_PWR7"); 1041 if (defs & ArchDefineA2) 1042 Builder.defineMacro("_ARCH_A2"); 1043 if (defs & ArchDefineA2q) { 1044 Builder.defineMacro("_ARCH_A2Q"); 1045 Builder.defineMacro("_ARCH_QP"); 1046 } 1047 1048 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1049 Builder.defineMacro("__bg__"); 1050 Builder.defineMacro("__THW_BLUEGENE__"); 1051 Builder.defineMacro("__bgq__"); 1052 Builder.defineMacro("__TOS_BGQ__"); 1053 } 1054 1055 if (HasVSX) 1056 Builder.defineMacro("__VSX__"); 1057 1058 // FIXME: The following are not yet generated here by Clang, but are 1059 // generated by GCC: 1060 // 1061 // _SOFT_FLOAT_ 1062 // __RECIP_PRECISION__ 1063 // __APPLE_ALTIVEC__ 1064 // __RECIP__ 1065 // __RECIPF__ 1066 // __RSQRTE__ 1067 // __RSQRTEF__ 1068 // _SOFT_DOUBLE_ 1069 // __NO_LWSYNC__ 1070 // __HAVE_BSWAP__ 1071 // __LONGDOUBLE128 1072 // __CMODEL_MEDIUM__ 1073 // __CMODEL_LARGE__ 1074 // _CALL_SYSV 1075 // _CALL_DARWIN 1076 // __NO_FPRS__ 1077} 1078 1079void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1080 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1081 .Case("7400", true) 1082 .Case("g4", true) 1083 .Case("7450", true) 1084 .Case("g4+", true) 1085 .Case("970", true) 1086 .Case("g5", true) 1087 .Case("pwr6", true) 1088 .Case("pwr7", true) 1089 .Case("ppc64", true) 1090 .Case("ppc64le", true) 1091 .Default(false); 1092 1093 Features["qpx"] = (CPU == "a2q"); 1094} 1095 1096bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1097 return Feature == "powerpc"; 1098} 1099 1100 1101const char * const PPCTargetInfo::GCCRegNames[] = { 1102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1104 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1105 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1106 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1107 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1108 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1109 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1110 "mq", "lr", "ctr", "ap", 1111 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1112 "xer", 1113 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1114 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1115 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1116 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1117 "vrsave", "vscr", 1118 "spe_acc", "spefscr", 1119 "sfp" 1120}; 1121 1122void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1123 unsigned &NumNames) const { 1124 Names = GCCRegNames; 1125 NumNames = llvm::array_lengthof(GCCRegNames); 1126} 1127 1128const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1129 // While some of these aliases do map to different registers 1130 // they still share the same register name. 1131 { { "0" }, "r0" }, 1132 { { "1"}, "r1" }, 1133 { { "2" }, "r2" }, 1134 { { "3" }, "r3" }, 1135 { { "4" }, "r4" }, 1136 { { "5" }, "r5" }, 1137 { { "6" }, "r6" }, 1138 { { "7" }, "r7" }, 1139 { { "8" }, "r8" }, 1140 { { "9" }, "r9" }, 1141 { { "10" }, "r10" }, 1142 { { "11" }, "r11" }, 1143 { { "12" }, "r12" }, 1144 { { "13" }, "r13" }, 1145 { { "14" }, "r14" }, 1146 { { "15" }, "r15" }, 1147 { { "16" }, "r16" }, 1148 { { "17" }, "r17" }, 1149 { { "18" }, "r18" }, 1150 { { "19" }, "r19" }, 1151 { { "20" }, "r20" }, 1152 { { "21" }, "r21" }, 1153 { { "22" }, "r22" }, 1154 { { "23" }, "r23" }, 1155 { { "24" }, "r24" }, 1156 { { "25" }, "r25" }, 1157 { { "26" }, "r26" }, 1158 { { "27" }, "r27" }, 1159 { { "28" }, "r28" }, 1160 { { "29" }, "r29" }, 1161 { { "30" }, "r30" }, 1162 { { "31" }, "r31" }, 1163 { { "fr0" }, "f0" }, 1164 { { "fr1" }, "f1" }, 1165 { { "fr2" }, "f2" }, 1166 { { "fr3" }, "f3" }, 1167 { { "fr4" }, "f4" }, 1168 { { "fr5" }, "f5" }, 1169 { { "fr6" }, "f6" }, 1170 { { "fr7" }, "f7" }, 1171 { { "fr8" }, "f8" }, 1172 { { "fr9" }, "f9" }, 1173 { { "fr10" }, "f10" }, 1174 { { "fr11" }, "f11" }, 1175 { { "fr12" }, "f12" }, 1176 { { "fr13" }, "f13" }, 1177 { { "fr14" }, "f14" }, 1178 { { "fr15" }, "f15" }, 1179 { { "fr16" }, "f16" }, 1180 { { "fr17" }, "f17" }, 1181 { { "fr18" }, "f18" }, 1182 { { "fr19" }, "f19" }, 1183 { { "fr20" }, "f20" }, 1184 { { "fr21" }, "f21" }, 1185 { { "fr22" }, "f22" }, 1186 { { "fr23" }, "f23" }, 1187 { { "fr24" }, "f24" }, 1188 { { "fr25" }, "f25" }, 1189 { { "fr26" }, "f26" }, 1190 { { "fr27" }, "f27" }, 1191 { { "fr28" }, "f28" }, 1192 { { "fr29" }, "f29" }, 1193 { { "fr30" }, "f30" }, 1194 { { "fr31" }, "f31" }, 1195 { { "cc" }, "cr0" }, 1196}; 1197 1198void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1199 unsigned &NumAliases) const { 1200 Aliases = GCCRegAliases; 1201 NumAliases = llvm::array_lengthof(GCCRegAliases); 1202} 1203} // end anonymous namespace. 1204 1205namespace { 1206class PPC32TargetInfo : public PPCTargetInfo { 1207public: 1208 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1209 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1210 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1211 1212 switch (getTriple().getOS()) { 1213 case llvm::Triple::Linux: 1214 case llvm::Triple::FreeBSD: 1215 case llvm::Triple::NetBSD: 1216 SizeType = UnsignedInt; 1217 PtrDiffType = SignedInt; 1218 IntPtrType = SignedInt; 1219 break; 1220 default: 1221 break; 1222 } 1223 1224 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1225 LongDoubleWidth = LongDoubleAlign = 64; 1226 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1227 } 1228 1229 // PPC32 supports atomics up to 4 bytes. 1230 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1231 } 1232 1233 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1234 // This is the ELF definition, and is overridden by the Darwin sub-target 1235 return TargetInfo::PowerABIBuiltinVaList; 1236 } 1237}; 1238} // end anonymous namespace. 1239 1240// Note: ABI differences may eventually require us to have a separate 1241// TargetInfo for little endian. 1242namespace { 1243class PPC64TargetInfo : public PPCTargetInfo { 1244public: 1245 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1246 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1247 IntMaxType = SignedLong; 1248 UIntMaxType = UnsignedLong; 1249 Int64Type = SignedLong; 1250 1251 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1252 LongDoubleWidth = LongDoubleAlign = 64; 1253 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1254 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1255 "i64:64:64-f32:32:32-f64:64:64-" 1256 "v128:128:128-n32:64"; 1257 } else 1258 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1259 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1260 "v128:128:128-n32:64"; 1261 1262 // PPC64 supports atomics up to 8 bytes. 1263 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1264 } 1265 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1266 return TargetInfo::CharPtrBuiltinVaList; 1267 } 1268}; 1269} // end anonymous namespace. 1270 1271 1272namespace { 1273class DarwinPPC32TargetInfo : 1274 public DarwinTargetInfo<PPC32TargetInfo> { 1275public: 1276 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1277 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1278 HasAlignMac68kSupport = true; 1279 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1280 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1281 LongLongAlign = 32; 1282 SuitableAlign = 128; 1283 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1284 "i64:32:64-f32:32:32-f64:32:64-v128:128:128-n32"; 1285 } 1286 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1287 return TargetInfo::CharPtrBuiltinVaList; 1288 } 1289}; 1290 1291class DarwinPPC64TargetInfo : 1292 public DarwinTargetInfo<PPC64TargetInfo> { 1293public: 1294 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1295 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1296 HasAlignMac68kSupport = true; 1297 SuitableAlign = 128; 1298 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1299 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1300 } 1301}; 1302} // end anonymous namespace. 1303 1304namespace { 1305 static const unsigned NVPTXAddrSpaceMap[] = { 1306 1, // opencl_global 1307 3, // opencl_local 1308 4, // opencl_constant 1309 1, // cuda_device 1310 4, // cuda_constant 1311 3, // cuda_shared 1312 }; 1313 class NVPTXTargetInfo : public TargetInfo { 1314 static const char * const GCCRegNames[]; 1315 static const Builtin::Info BuiltinInfo[]; 1316 public: 1317 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1318 BigEndian = false; 1319 TLSSupported = false; 1320 LongWidth = LongAlign = 64; 1321 AddrSpaceMap = &NVPTXAddrSpaceMap; 1322 UseAddrSpaceMapMangling = true; 1323 // Define available target features 1324 // These must be defined in sorted order! 1325 NoAsmVariants = true; 1326 } 1327 virtual void getTargetDefines(const LangOptions &Opts, 1328 MacroBuilder &Builder) const { 1329 Builder.defineMacro("__PTX__"); 1330 Builder.defineMacro("__NVPTX__"); 1331 } 1332 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1333 unsigned &NumRecords) const { 1334 Records = BuiltinInfo; 1335 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1336 } 1337 virtual bool hasFeature(StringRef Feature) const { 1338 return Feature == "ptx" || Feature == "nvptx"; 1339 } 1340 1341 virtual void getGCCRegNames(const char * const *&Names, 1342 unsigned &NumNames) const; 1343 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1344 unsigned &NumAliases) const { 1345 // No aliases. 1346 Aliases = 0; 1347 NumAliases = 0; 1348 } 1349 virtual bool validateAsmConstraint(const char *&Name, 1350 TargetInfo::ConstraintInfo &Info) const { 1351 switch (*Name) { 1352 default: return false; 1353 case 'c': 1354 case 'h': 1355 case 'r': 1356 case 'l': 1357 case 'f': 1358 case 'd': 1359 Info.setAllowsRegister(); 1360 return true; 1361 } 1362 } 1363 virtual const char *getClobbers() const { 1364 // FIXME: Is this really right? 1365 return ""; 1366 } 1367 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1368 // FIXME: implement 1369 return TargetInfo::CharPtrBuiltinVaList; 1370 } 1371 virtual bool setCPU(const std::string &Name) { 1372 bool Valid = llvm::StringSwitch<bool>(Name) 1373 .Case("sm_20", true) 1374 .Case("sm_21", true) 1375 .Case("sm_30", true) 1376 .Case("sm_35", true) 1377 .Default(false); 1378 1379 return Valid; 1380 } 1381 }; 1382 1383 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1384#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1385#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1386 ALL_LANGUAGES }, 1387#include "clang/Basic/BuiltinsNVPTX.def" 1388 }; 1389 1390 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1391 "r0" 1392 }; 1393 1394 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1395 unsigned &NumNames) const { 1396 Names = GCCRegNames; 1397 NumNames = llvm::array_lengthof(GCCRegNames); 1398 } 1399 1400 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1401 public: 1402 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1403 PointerWidth = PointerAlign = 32; 1404 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1405 DescriptionString 1406 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1407 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1408 "n16:32:64"; 1409 } 1410 }; 1411 1412 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1413 public: 1414 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1415 PointerWidth = PointerAlign = 64; 1416 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1417 DescriptionString 1418 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1419 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1420 "n16:32:64"; 1421 } 1422 }; 1423} 1424 1425namespace { 1426 1427static const unsigned R600AddrSpaceMap[] = { 1428 1, // opencl_global 1429 3, // opencl_local 1430 2, // opencl_constant 1431 1, // cuda_device 1432 2, // cuda_constant 1433 3 // cuda_shared 1434}; 1435 1436static const char *DescriptionStringR600 = 1437 "e" 1438 "-p:32:32:32" 1439 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 1440 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1441 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1442 "-n32:64"; 1443 1444static const char *DescriptionStringR600DoubleOps = 1445 "e" 1446 "-p:32:32:32" 1447 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1448 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1449 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1450 "-n32:64"; 1451 1452static const char *DescriptionStringSI = 1453 "e" 1454 "-p:64:64:64" 1455 "-p3:32:32:32" 1456 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1457 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1458 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1459 "-n32:64"; 1460 1461class R600TargetInfo : public TargetInfo { 1462 /// \brief The GPU profiles supported by the R600 target. 1463 enum GPUKind { 1464 GK_NONE, 1465 GK_R600, 1466 GK_R600_DOUBLE_OPS, 1467 GK_R700, 1468 GK_R700_DOUBLE_OPS, 1469 GK_EVERGREEN, 1470 GK_EVERGREEN_DOUBLE_OPS, 1471 GK_NORTHERN_ISLANDS, 1472 GK_CAYMAN, 1473 GK_SOUTHERN_ISLANDS, 1474 GK_SEA_ISLANDS 1475 } GPU; 1476 1477public: 1478 R600TargetInfo(const llvm::Triple &Triple) 1479 : TargetInfo(Triple), GPU(GK_R600) { 1480 DescriptionString = DescriptionStringR600; 1481 AddrSpaceMap = &R600AddrSpaceMap; 1482 UseAddrSpaceMapMangling = true; 1483 } 1484 1485 virtual const char * getClobbers() const { 1486 return ""; 1487 } 1488 1489 virtual void getGCCRegNames(const char * const *&Names, 1490 unsigned &numNames) const { 1491 Names = NULL; 1492 numNames = 0; 1493 } 1494 1495 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1496 unsigned &NumAliases) const { 1497 Aliases = NULL; 1498 NumAliases = 0; 1499 } 1500 1501 virtual bool validateAsmConstraint(const char *&Name, 1502 TargetInfo::ConstraintInfo &info) const { 1503 return true; 1504 } 1505 1506 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1507 unsigned &NumRecords) const { 1508 Records = NULL; 1509 NumRecords = 0; 1510 } 1511 1512 1513 virtual void getTargetDefines(const LangOptions &Opts, 1514 MacroBuilder &Builder) const { 1515 Builder.defineMacro("__R600__"); 1516 } 1517 1518 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1519 return TargetInfo::CharPtrBuiltinVaList; 1520 } 1521 1522 virtual bool setCPU(const std::string &Name) { 1523 GPU = llvm::StringSwitch<GPUKind>(Name) 1524 .Case("r600" , GK_R600) 1525 .Case("rv610", GK_R600) 1526 .Case("rv620", GK_R600) 1527 .Case("rv630", GK_R600) 1528 .Case("rv635", GK_R600) 1529 .Case("rs780", GK_R600) 1530 .Case("rs880", GK_R600) 1531 .Case("rv670", GK_R600_DOUBLE_OPS) 1532 .Case("rv710", GK_R700) 1533 .Case("rv730", GK_R700) 1534 .Case("rv740", GK_R700_DOUBLE_OPS) 1535 .Case("rv770", GK_R700_DOUBLE_OPS) 1536 .Case("palm", GK_EVERGREEN) 1537 .Case("cedar", GK_EVERGREEN) 1538 .Case("sumo", GK_EVERGREEN) 1539 .Case("sumo2", GK_EVERGREEN) 1540 .Case("redwood", GK_EVERGREEN) 1541 .Case("juniper", GK_EVERGREEN) 1542 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1543 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1544 .Case("barts", GK_NORTHERN_ISLANDS) 1545 .Case("turks", GK_NORTHERN_ISLANDS) 1546 .Case("caicos", GK_NORTHERN_ISLANDS) 1547 .Case("cayman", GK_CAYMAN) 1548 .Case("aruba", GK_CAYMAN) 1549 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1550 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1551 .Case("verde", GK_SOUTHERN_ISLANDS) 1552 .Case("oland", GK_SOUTHERN_ISLANDS) 1553 .Case("bonaire", GK_SEA_ISLANDS) 1554 .Case("kabini", GK_SEA_ISLANDS) 1555 .Case("kaveri", GK_SEA_ISLANDS) 1556 .Case("hawaii", GK_SEA_ISLANDS) 1557 .Default(GK_NONE); 1558 1559 if (GPU == GK_NONE) { 1560 return false; 1561 } 1562 1563 // Set the correct data layout 1564 switch (GPU) { 1565 case GK_NONE: 1566 case GK_R600: 1567 case GK_R700: 1568 case GK_EVERGREEN: 1569 case GK_NORTHERN_ISLANDS: 1570 DescriptionString = DescriptionStringR600; 1571 break; 1572 case GK_R600_DOUBLE_OPS: 1573 case GK_R700_DOUBLE_OPS: 1574 case GK_EVERGREEN_DOUBLE_OPS: 1575 case GK_CAYMAN: 1576 DescriptionString = DescriptionStringR600DoubleOps; 1577 break; 1578 case GK_SOUTHERN_ISLANDS: 1579 case GK_SEA_ISLANDS: 1580 DescriptionString = DescriptionStringSI; 1581 break; 1582 } 1583 1584 return true; 1585 } 1586}; 1587 1588} // end anonymous namespace 1589 1590namespace { 1591// Namespace for x86 abstract base class 1592const Builtin::Info BuiltinInfo[] = { 1593#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1594#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1595 ALL_LANGUAGES }, 1596#include "clang/Basic/BuiltinsX86.def" 1597}; 1598 1599static const char* const GCCRegNames[] = { 1600 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1601 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1602 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1603 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1604 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1605 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1606 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1607 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1608 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1609}; 1610 1611const TargetInfo::AddlRegName AddlRegNames[] = { 1612 { { "al", "ah", "eax", "rax" }, 0 }, 1613 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1614 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1615 { { "dl", "dh", "edx", "rdx" }, 1 }, 1616 { { "esi", "rsi" }, 4 }, 1617 { { "edi", "rdi" }, 5 }, 1618 { { "esp", "rsp" }, 7 }, 1619 { { "ebp", "rbp" }, 6 }, 1620}; 1621 1622// X86 target abstract base class; x86-32 and x86-64 are very close, so 1623// most of the implementation can be shared. 1624class X86TargetInfo : public TargetInfo { 1625 enum X86SSEEnum { 1626 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1627 } SSELevel; 1628 enum MMX3DNowEnum { 1629 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1630 } MMX3DNowLevel; 1631 enum XOPEnum { 1632 NoXOP, 1633 SSE4A, 1634 FMA4, 1635 XOP 1636 } XOPLevel; 1637 1638 bool HasAES; 1639 bool HasPCLMUL; 1640 bool HasLZCNT; 1641 bool HasRDRND; 1642 bool HasBMI; 1643 bool HasBMI2; 1644 bool HasPOPCNT; 1645 bool HasRTM; 1646 bool HasPRFCHW; 1647 bool HasRDSEED; 1648 bool HasTBM; 1649 bool HasFMA; 1650 bool HasF16C; 1651 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1652 bool HasSHA; 1653 bool HasCX16; 1654 1655 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1656 /// 1657 /// Each enumeration represents a particular CPU supported by Clang. These 1658 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1659 enum CPUKind { 1660 CK_Generic, 1661 1662 /// \name i386 1663 /// i386-generation processors. 1664 //@{ 1665 CK_i386, 1666 //@} 1667 1668 /// \name i486 1669 /// i486-generation processors. 1670 //@{ 1671 CK_i486, 1672 CK_WinChipC6, 1673 CK_WinChip2, 1674 CK_C3, 1675 //@} 1676 1677 /// \name i586 1678 /// i586-generation processors, P5 microarchitecture based. 1679 //@{ 1680 CK_i586, 1681 CK_Pentium, 1682 CK_PentiumMMX, 1683 //@} 1684 1685 /// \name i686 1686 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1687 //@{ 1688 CK_i686, 1689 CK_PentiumPro, 1690 CK_Pentium2, 1691 CK_Pentium3, 1692 CK_Pentium3M, 1693 CK_PentiumM, 1694 CK_C3_2, 1695 1696 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1697 /// Clang however has some logic to suport this. 1698 // FIXME: Warn, deprecate, and potentially remove this. 1699 CK_Yonah, 1700 //@} 1701 1702 /// \name Netburst 1703 /// Netburst microarchitecture based processors. 1704 //@{ 1705 CK_Pentium4, 1706 CK_Pentium4M, 1707 CK_Prescott, 1708 CK_Nocona, 1709 //@} 1710 1711 /// \name Core 1712 /// Core microarchitecture based processors. 1713 //@{ 1714 CK_Core2, 1715 1716 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1717 /// codename which GCC no longer accepts as an option to -march, but Clang 1718 /// has some logic for recognizing it. 1719 // FIXME: Warn, deprecate, and potentially remove this. 1720 CK_Penryn, 1721 //@} 1722 1723 /// \name Atom 1724 /// Atom processors 1725 //@{ 1726 CK_Atom, 1727 CK_Silvermont, 1728 //@} 1729 1730 /// \name Nehalem 1731 /// Nehalem microarchitecture based processors. 1732 //@{ 1733 CK_Corei7, 1734 CK_Corei7AVX, 1735 CK_CoreAVXi, 1736 CK_CoreAVX2, 1737 //@} 1738 1739 /// \name Knights Landing 1740 /// Knights Landing processor. 1741 CK_KNL, 1742 1743 /// \name K6 1744 /// K6 architecture processors. 1745 //@{ 1746 CK_K6, 1747 CK_K6_2, 1748 CK_K6_3, 1749 //@} 1750 1751 /// \name K7 1752 /// K7 architecture processors. 1753 //@{ 1754 CK_Athlon, 1755 CK_AthlonThunderbird, 1756 CK_Athlon4, 1757 CK_AthlonXP, 1758 CK_AthlonMP, 1759 //@} 1760 1761 /// \name K8 1762 /// K8 architecture processors. 1763 //@{ 1764 CK_Athlon64, 1765 CK_Athlon64SSE3, 1766 CK_AthlonFX, 1767 CK_K8, 1768 CK_K8SSE3, 1769 CK_Opteron, 1770 CK_OpteronSSE3, 1771 CK_AMDFAM10, 1772 //@} 1773 1774 /// \name Bobcat 1775 /// Bobcat architecture processors. 1776 //@{ 1777 CK_BTVER1, 1778 CK_BTVER2, 1779 //@} 1780 1781 /// \name Bulldozer 1782 /// Bulldozer architecture processors. 1783 //@{ 1784 CK_BDVER1, 1785 CK_BDVER2, 1786 CK_BDVER3, 1787 //@} 1788 1789 /// This specification is deprecated and will be removed in the future. 1790 /// Users should prefer \see CK_K8. 1791 // FIXME: Warn on this when the CPU is set to it. 1792 CK_x86_64, 1793 //@} 1794 1795 /// \name Geode 1796 /// Geode processors. 1797 //@{ 1798 CK_Geode 1799 //@} 1800 } CPU; 1801 1802 enum FPMathKind { 1803 FP_Default, 1804 FP_SSE, 1805 FP_387 1806 } FPMath; 1807 1808public: 1809 X86TargetInfo(const llvm::Triple &Triple) 1810 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1811 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1812 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1813 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1814 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1815 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1816 FPMath(FP_Default) { 1817 BigEndian = false; 1818 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1819 } 1820 virtual unsigned getFloatEvalMethod() const { 1821 // X87 evaluates with 80 bits "long double" precision. 1822 return SSELevel == NoSSE ? 2 : 0; 1823 } 1824 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1825 unsigned &NumRecords) const { 1826 Records = BuiltinInfo; 1827 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1828 } 1829 virtual void getGCCRegNames(const char * const *&Names, 1830 unsigned &NumNames) const { 1831 Names = GCCRegNames; 1832 NumNames = llvm::array_lengthof(GCCRegNames); 1833 } 1834 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1835 unsigned &NumAliases) const { 1836 Aliases = 0; 1837 NumAliases = 0; 1838 } 1839 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1840 unsigned &NumNames) const { 1841 Names = AddlRegNames; 1842 NumNames = llvm::array_lengthof(AddlRegNames); 1843 } 1844 virtual bool validateAsmConstraint(const char *&Name, 1845 TargetInfo::ConstraintInfo &info) const; 1846 virtual std::string convertConstraint(const char *&Constraint) const; 1847 virtual const char *getClobbers() const { 1848 return "~{dirflag},~{fpsr},~{flags}"; 1849 } 1850 virtual void getTargetDefines(const LangOptions &Opts, 1851 MacroBuilder &Builder) const; 1852 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1853 bool Enabled); 1854 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1855 bool Enabled); 1856 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1857 bool Enabled); 1858 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1859 StringRef Name, bool Enabled) const { 1860 setFeatureEnabledImpl(Features, Name, Enabled); 1861 } 1862 // This exists purely to cut down on the number of virtual calls in 1863 // getDefaultFeatures which calls this repeatedly. 1864 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1865 StringRef Name, bool Enabled); 1866 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1867 virtual bool hasFeature(StringRef Feature) const; 1868 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 1869 DiagnosticsEngine &Diags); 1870 virtual const char* getABI() const { 1871 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1872 return "avx"; 1873 else if (getTriple().getArch() == llvm::Triple::x86 && 1874 MMX3DNowLevel == NoMMX3DNow) 1875 return "no-mmx"; 1876 return ""; 1877 } 1878 virtual bool setCPU(const std::string &Name) { 1879 CPU = llvm::StringSwitch<CPUKind>(Name) 1880 .Case("i386", CK_i386) 1881 .Case("i486", CK_i486) 1882 .Case("winchip-c6", CK_WinChipC6) 1883 .Case("winchip2", CK_WinChip2) 1884 .Case("c3", CK_C3) 1885 .Case("i586", CK_i586) 1886 .Case("pentium", CK_Pentium) 1887 .Case("pentium-mmx", CK_PentiumMMX) 1888 .Case("i686", CK_i686) 1889 .Case("pentiumpro", CK_PentiumPro) 1890 .Case("pentium2", CK_Pentium2) 1891 .Case("pentium3", CK_Pentium3) 1892 .Case("pentium3m", CK_Pentium3M) 1893 .Case("pentium-m", CK_PentiumM) 1894 .Case("c3-2", CK_C3_2) 1895 .Case("yonah", CK_Yonah) 1896 .Case("pentium4", CK_Pentium4) 1897 .Case("pentium4m", CK_Pentium4M) 1898 .Case("prescott", CK_Prescott) 1899 .Case("nocona", CK_Nocona) 1900 .Case("core2", CK_Core2) 1901 .Case("penryn", CK_Penryn) 1902 .Case("atom", CK_Atom) 1903 .Case("slm", CK_Silvermont) 1904 .Case("corei7", CK_Corei7) 1905 .Case("corei7-avx", CK_Corei7AVX) 1906 .Case("core-avx-i", CK_CoreAVXi) 1907 .Case("core-avx2", CK_CoreAVX2) 1908 .Case("knl", CK_KNL) 1909 .Case("k6", CK_K6) 1910 .Case("k6-2", CK_K6_2) 1911 .Case("k6-3", CK_K6_3) 1912 .Case("athlon", CK_Athlon) 1913 .Case("athlon-tbird", CK_AthlonThunderbird) 1914 .Case("athlon-4", CK_Athlon4) 1915 .Case("athlon-xp", CK_AthlonXP) 1916 .Case("athlon-mp", CK_AthlonMP) 1917 .Case("athlon64", CK_Athlon64) 1918 .Case("athlon64-sse3", CK_Athlon64SSE3) 1919 .Case("athlon-fx", CK_AthlonFX) 1920 .Case("k8", CK_K8) 1921 .Case("k8-sse3", CK_K8SSE3) 1922 .Case("opteron", CK_Opteron) 1923 .Case("opteron-sse3", CK_OpteronSSE3) 1924 .Case("amdfam10", CK_AMDFAM10) 1925 .Case("btver1", CK_BTVER1) 1926 .Case("btver2", CK_BTVER2) 1927 .Case("bdver1", CK_BDVER1) 1928 .Case("bdver2", CK_BDVER2) 1929 .Case("bdver3", CK_BDVER3) 1930 .Case("x86-64", CK_x86_64) 1931 .Case("geode", CK_Geode) 1932 .Default(CK_Generic); 1933 1934 // Perform any per-CPU checks necessary to determine if this CPU is 1935 // acceptable. 1936 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1937 // invalid without explaining *why*. 1938 switch (CPU) { 1939 case CK_Generic: 1940 // No processor selected! 1941 return false; 1942 1943 case CK_i386: 1944 case CK_i486: 1945 case CK_WinChipC6: 1946 case CK_WinChip2: 1947 case CK_C3: 1948 case CK_i586: 1949 case CK_Pentium: 1950 case CK_PentiumMMX: 1951 case CK_i686: 1952 case CK_PentiumPro: 1953 case CK_Pentium2: 1954 case CK_Pentium3: 1955 case CK_Pentium3M: 1956 case CK_PentiumM: 1957 case CK_Yonah: 1958 case CK_C3_2: 1959 case CK_Pentium4: 1960 case CK_Pentium4M: 1961 case CK_Prescott: 1962 case CK_K6: 1963 case CK_K6_2: 1964 case CK_K6_3: 1965 case CK_Athlon: 1966 case CK_AthlonThunderbird: 1967 case CK_Athlon4: 1968 case CK_AthlonXP: 1969 case CK_AthlonMP: 1970 case CK_Geode: 1971 // Only accept certain architectures when compiling in 32-bit mode. 1972 if (getTriple().getArch() != llvm::Triple::x86) 1973 return false; 1974 1975 // Fallthrough 1976 case CK_Nocona: 1977 case CK_Core2: 1978 case CK_Penryn: 1979 case CK_Atom: 1980 case CK_Silvermont: 1981 case CK_Corei7: 1982 case CK_Corei7AVX: 1983 case CK_CoreAVXi: 1984 case CK_CoreAVX2: 1985 case CK_KNL: 1986 case CK_Athlon64: 1987 case CK_Athlon64SSE3: 1988 case CK_AthlonFX: 1989 case CK_K8: 1990 case CK_K8SSE3: 1991 case CK_Opteron: 1992 case CK_OpteronSSE3: 1993 case CK_AMDFAM10: 1994 case CK_BTVER1: 1995 case CK_BTVER2: 1996 case CK_BDVER1: 1997 case CK_BDVER2: 1998 case CK_BDVER3: 1999 case CK_x86_64: 2000 return true; 2001 } 2002 llvm_unreachable("Unhandled CPU kind"); 2003 } 2004 2005 virtual bool setFPMath(StringRef Name); 2006 2007 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 2008 // We accept all non-ARM calling conventions 2009 return (CC == CC_X86ThisCall || 2010 CC == CC_X86FastCall || 2011 CC == CC_X86StdCall || 2012 CC == CC_C || 2013 CC == CC_X86Pascal || 2014 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2015 } 2016 2017 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 2018 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2019 } 2020}; 2021 2022bool X86TargetInfo::setFPMath(StringRef Name) { 2023 if (Name == "387") { 2024 FPMath = FP_387; 2025 return true; 2026 } 2027 if (Name == "sse") { 2028 FPMath = FP_SSE; 2029 return true; 2030 } 2031 return false; 2032} 2033 2034void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2035 // FIXME: This *really* should not be here. 2036 2037 // X86_64 always has SSE2. 2038 if (getTriple().getArch() == llvm::Triple::x86_64) 2039 setFeatureEnabledImpl(Features, "sse2", true); 2040 2041 switch (CPU) { 2042 case CK_Generic: 2043 case CK_i386: 2044 case CK_i486: 2045 case CK_i586: 2046 case CK_Pentium: 2047 case CK_i686: 2048 case CK_PentiumPro: 2049 break; 2050 case CK_PentiumMMX: 2051 case CK_Pentium2: 2052 setFeatureEnabledImpl(Features, "mmx", true); 2053 break; 2054 case CK_Pentium3: 2055 case CK_Pentium3M: 2056 setFeatureEnabledImpl(Features, "sse", true); 2057 break; 2058 case CK_PentiumM: 2059 case CK_Pentium4: 2060 case CK_Pentium4M: 2061 case CK_x86_64: 2062 setFeatureEnabledImpl(Features, "sse2", true); 2063 break; 2064 case CK_Yonah: 2065 case CK_Prescott: 2066 case CK_Nocona: 2067 setFeatureEnabledImpl(Features, "sse3", true); 2068 setFeatureEnabledImpl(Features, "cx16", true); 2069 break; 2070 case CK_Core2: 2071 setFeatureEnabledImpl(Features, "ssse3", true); 2072 setFeatureEnabledImpl(Features, "cx16", true); 2073 break; 2074 case CK_Penryn: 2075 setFeatureEnabledImpl(Features, "sse4.1", true); 2076 setFeatureEnabledImpl(Features, "cx16", true); 2077 break; 2078 case CK_Atom: 2079 setFeatureEnabledImpl(Features, "ssse3", true); 2080 setFeatureEnabledImpl(Features, "cx16", true); 2081 break; 2082 case CK_Silvermont: 2083 setFeatureEnabledImpl(Features, "sse4.2", true); 2084 setFeatureEnabledImpl(Features, "aes", true); 2085 setFeatureEnabledImpl(Features, "cx16", true); 2086 setFeatureEnabledImpl(Features, "pclmul", true); 2087 break; 2088 case CK_Corei7: 2089 setFeatureEnabledImpl(Features, "sse4.2", true); 2090 setFeatureEnabledImpl(Features, "cx16", true); 2091 break; 2092 case CK_Corei7AVX: 2093 setFeatureEnabledImpl(Features, "avx", true); 2094 setFeatureEnabledImpl(Features, "aes", true); 2095 setFeatureEnabledImpl(Features, "cx16", true); 2096 setFeatureEnabledImpl(Features, "pclmul", true); 2097 break; 2098 case CK_CoreAVXi: 2099 setFeatureEnabledImpl(Features, "avx", true); 2100 setFeatureEnabledImpl(Features, "aes", true); 2101 setFeatureEnabledImpl(Features, "pclmul", true); 2102 setFeatureEnabledImpl(Features, "rdrnd", true); 2103 setFeatureEnabledImpl(Features, "f16c", true); 2104 break; 2105 case CK_CoreAVX2: 2106 setFeatureEnabledImpl(Features, "avx2", true); 2107 setFeatureEnabledImpl(Features, "aes", true); 2108 setFeatureEnabledImpl(Features, "pclmul", true); 2109 setFeatureEnabledImpl(Features, "lzcnt", true); 2110 setFeatureEnabledImpl(Features, "rdrnd", true); 2111 setFeatureEnabledImpl(Features, "f16c", true); 2112 setFeatureEnabledImpl(Features, "bmi", true); 2113 setFeatureEnabledImpl(Features, "bmi2", true); 2114 setFeatureEnabledImpl(Features, "rtm", true); 2115 setFeatureEnabledImpl(Features, "fma", true); 2116 setFeatureEnabledImpl(Features, "cx16", true); 2117 break; 2118 case CK_KNL: 2119 setFeatureEnabledImpl(Features, "avx512f", true); 2120 setFeatureEnabledImpl(Features, "avx512cd", true); 2121 setFeatureEnabledImpl(Features, "avx512er", true); 2122 setFeatureEnabledImpl(Features, "avx512pf", true); 2123 setFeatureEnabledImpl(Features, "aes", true); 2124 setFeatureEnabledImpl(Features, "pclmul", true); 2125 setFeatureEnabledImpl(Features, "lzcnt", true); 2126 setFeatureEnabledImpl(Features, "rdrnd", true); 2127 setFeatureEnabledImpl(Features, "f16c", true); 2128 setFeatureEnabledImpl(Features, "bmi", true); 2129 setFeatureEnabledImpl(Features, "bmi2", true); 2130 setFeatureEnabledImpl(Features, "rtm", true); 2131 setFeatureEnabledImpl(Features, "fma", true); 2132 break; 2133 case CK_K6: 2134 case CK_WinChipC6: 2135 setFeatureEnabledImpl(Features, "mmx", true); 2136 break; 2137 case CK_K6_2: 2138 case CK_K6_3: 2139 case CK_WinChip2: 2140 case CK_C3: 2141 setFeatureEnabledImpl(Features, "3dnow", true); 2142 break; 2143 case CK_Athlon: 2144 case CK_AthlonThunderbird: 2145 case CK_Geode: 2146 setFeatureEnabledImpl(Features, "3dnowa", true); 2147 break; 2148 case CK_Athlon4: 2149 case CK_AthlonXP: 2150 case CK_AthlonMP: 2151 setFeatureEnabledImpl(Features, "sse", true); 2152 setFeatureEnabledImpl(Features, "3dnowa", true); 2153 break; 2154 case CK_K8: 2155 case CK_Opteron: 2156 case CK_Athlon64: 2157 case CK_AthlonFX: 2158 setFeatureEnabledImpl(Features, "sse2", true); 2159 setFeatureEnabledImpl(Features, "3dnowa", true); 2160 break; 2161 case CK_K8SSE3: 2162 case CK_OpteronSSE3: 2163 case CK_Athlon64SSE3: 2164 setFeatureEnabledImpl(Features, "sse3", true); 2165 setFeatureEnabledImpl(Features, "3dnowa", true); 2166 break; 2167 case CK_AMDFAM10: 2168 setFeatureEnabledImpl(Features, "sse3", true); 2169 setFeatureEnabledImpl(Features, "sse4a", true); 2170 setFeatureEnabledImpl(Features, "3dnowa", true); 2171 setFeatureEnabledImpl(Features, "lzcnt", true); 2172 setFeatureEnabledImpl(Features, "popcnt", true); 2173 break; 2174 case CK_BTVER1: 2175 setFeatureEnabledImpl(Features, "ssse3", true); 2176 setFeatureEnabledImpl(Features, "sse4a", true); 2177 setFeatureEnabledImpl(Features, "cx16", true); 2178 setFeatureEnabledImpl(Features, "lzcnt", true); 2179 setFeatureEnabledImpl(Features, "popcnt", true); 2180 setFeatureEnabledImpl(Features, "prfchw", true); 2181 break; 2182 case CK_BTVER2: 2183 setFeatureEnabledImpl(Features, "avx", true); 2184 setFeatureEnabledImpl(Features, "sse4a", true); 2185 setFeatureEnabledImpl(Features, "lzcnt", true); 2186 setFeatureEnabledImpl(Features, "aes", true); 2187 setFeatureEnabledImpl(Features, "pclmul", true); 2188 setFeatureEnabledImpl(Features, "prfchw", true); 2189 setFeatureEnabledImpl(Features, "bmi", true); 2190 setFeatureEnabledImpl(Features, "f16c", true); 2191 setFeatureEnabledImpl(Features, "cx16", true); 2192 break; 2193 case CK_BDVER1: 2194 setFeatureEnabledImpl(Features, "xop", true); 2195 setFeatureEnabledImpl(Features, "lzcnt", true); 2196 setFeatureEnabledImpl(Features, "aes", true); 2197 setFeatureEnabledImpl(Features, "pclmul", true); 2198 setFeatureEnabledImpl(Features, "prfchw", true); 2199 setFeatureEnabledImpl(Features, "cx16", true); 2200 break; 2201 case CK_BDVER2: 2202 case CK_BDVER3: 2203 setFeatureEnabledImpl(Features, "xop", true); 2204 setFeatureEnabledImpl(Features, "lzcnt", true); 2205 setFeatureEnabledImpl(Features, "aes", true); 2206 setFeatureEnabledImpl(Features, "pclmul", true); 2207 setFeatureEnabledImpl(Features, "prfchw", true); 2208 setFeatureEnabledImpl(Features, "bmi", true); 2209 setFeatureEnabledImpl(Features, "fma", true); 2210 setFeatureEnabledImpl(Features, "f16c", true); 2211 setFeatureEnabledImpl(Features, "tbm", true); 2212 setFeatureEnabledImpl(Features, "cx16", true); 2213 break; 2214 case CK_C3_2: 2215 setFeatureEnabledImpl(Features, "sse", true); 2216 break; 2217 } 2218} 2219 2220void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2221 X86SSEEnum Level, bool Enabled) { 2222 if (Enabled) { 2223 switch (Level) { 2224 case AVX512F: 2225 Features["avx512f"] = true; 2226 case AVX2: 2227 Features["avx2"] = true; 2228 case AVX: 2229 Features["avx"] = true; 2230 case SSE42: 2231 Features["sse4.2"] = true; 2232 case SSE41: 2233 Features["sse4.1"] = true; 2234 case SSSE3: 2235 Features["ssse3"] = true; 2236 case SSE3: 2237 Features["sse3"] = true; 2238 case SSE2: 2239 Features["sse2"] = true; 2240 case SSE1: 2241 Features["sse"] = true; 2242 case NoSSE: 2243 break; 2244 } 2245 return; 2246 } 2247 2248 switch (Level) { 2249 case NoSSE: 2250 case SSE1: 2251 Features["sse"] = false; 2252 case SSE2: 2253 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2254 Features["sha"] = false; 2255 case SSE3: 2256 Features["sse3"] = false; 2257 setXOPLevel(Features, NoXOP, false); 2258 case SSSE3: 2259 Features["ssse3"] = false; 2260 case SSE41: 2261 Features["sse4.1"] = false; 2262 case SSE42: 2263 Features["sse4.2"] = false; 2264 case AVX: 2265 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2266 setXOPLevel(Features, FMA4, false); 2267 case AVX2: 2268 Features["avx2"] = false; 2269 case AVX512F: 2270 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2271 Features["avx512pf"] = false; 2272 } 2273} 2274 2275void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2276 MMX3DNowEnum Level, bool Enabled) { 2277 if (Enabled) { 2278 switch (Level) { 2279 case AMD3DNowAthlon: 2280 Features["3dnowa"] = true; 2281 case AMD3DNow: 2282 Features["3dnow"] = true; 2283 case MMX: 2284 Features["mmx"] = true; 2285 case NoMMX3DNow: 2286 break; 2287 } 2288 return; 2289 } 2290 2291 switch (Level) { 2292 case NoMMX3DNow: 2293 case MMX: 2294 Features["mmx"] = false; 2295 case AMD3DNow: 2296 Features["3dnow"] = false; 2297 case AMD3DNowAthlon: 2298 Features["3dnowa"] = false; 2299 } 2300} 2301 2302void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2303 bool Enabled) { 2304 if (Enabled) { 2305 switch (Level) { 2306 case XOP: 2307 Features["xop"] = true; 2308 case FMA4: 2309 Features["fma4"] = true; 2310 setSSELevel(Features, AVX, true); 2311 case SSE4A: 2312 Features["sse4a"] = true; 2313 setSSELevel(Features, SSE3, true); 2314 case NoXOP: 2315 break; 2316 } 2317 return; 2318 } 2319 2320 switch (Level) { 2321 case NoXOP: 2322 case SSE4A: 2323 Features["sse4a"] = false; 2324 case FMA4: 2325 Features["fma4"] = false; 2326 case XOP: 2327 Features["xop"] = false; 2328 } 2329} 2330 2331void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2332 StringRef Name, bool Enabled) { 2333 // FIXME: This *really* should not be here. We need some way of translating 2334 // options into llvm subtarget features. 2335 if (Name == "sse4") 2336 Name = "sse4.2"; 2337 2338 Features[Name] = Enabled; 2339 2340 if (Name == "mmx") { 2341 setMMXLevel(Features, MMX, Enabled); 2342 } else if (Name == "sse") { 2343 setSSELevel(Features, SSE1, Enabled); 2344 } else if (Name == "sse2") { 2345 setSSELevel(Features, SSE2, Enabled); 2346 } else if (Name == "sse3") { 2347 setSSELevel(Features, SSE3, Enabled); 2348 } else if (Name == "ssse3") { 2349 setSSELevel(Features, SSSE3, Enabled); 2350 } else if (Name == "sse4.2") { 2351 setSSELevel(Features, SSE42, Enabled); 2352 } else if (Name == "sse4.1") { 2353 setSSELevel(Features, SSE41, Enabled); 2354 } else if (Name == "3dnow") { 2355 setMMXLevel(Features, AMD3DNow, Enabled); 2356 } else if (Name == "3dnowa") { 2357 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2358 } else if (Name == "aes") { 2359 if (Enabled) 2360 setSSELevel(Features, SSE2, Enabled); 2361 } else if (Name == "pclmul") { 2362 if (Enabled) 2363 setSSELevel(Features, SSE2, Enabled); 2364 } else if (Name == "avx") { 2365 setSSELevel(Features, AVX, Enabled); 2366 } else if (Name == "avx2") { 2367 setSSELevel(Features, AVX2, Enabled); 2368 } else if (Name == "avx512f") { 2369 setSSELevel(Features, AVX512F, Enabled); 2370 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2371 if (Enabled) 2372 setSSELevel(Features, AVX512F, Enabled); 2373 } else if (Name == "fma") { 2374 if (Enabled) 2375 setSSELevel(Features, AVX, Enabled); 2376 } else if (Name == "fma4") { 2377 setXOPLevel(Features, FMA4, Enabled); 2378 } else if (Name == "xop") { 2379 setXOPLevel(Features, XOP, Enabled); 2380 } else if (Name == "sse4a") { 2381 setXOPLevel(Features, SSE4A, Enabled); 2382 } else if (Name == "f16c") { 2383 if (Enabled) 2384 setSSELevel(Features, AVX, Enabled); 2385 } else if (Name == "sha") { 2386 if (Enabled) 2387 setSSELevel(Features, SSE2, Enabled); 2388 } 2389} 2390 2391/// handleTargetFeatures - Perform initialization based on the user 2392/// configured set of features. 2393bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2394 DiagnosticsEngine &Diags) { 2395 // Remember the maximum enabled sselevel. 2396 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2397 // Ignore disabled features. 2398 if (Features[i][0] == '-') 2399 continue; 2400 2401 StringRef Feature = StringRef(Features[i]).substr(1); 2402 2403 if (Feature == "aes") { 2404 HasAES = true; 2405 continue; 2406 } 2407 2408 if (Feature == "pclmul") { 2409 HasPCLMUL = true; 2410 continue; 2411 } 2412 2413 if (Feature == "lzcnt") { 2414 HasLZCNT = true; 2415 continue; 2416 } 2417 2418 if (Feature == "rdrnd") { 2419 HasRDRND = true; 2420 continue; 2421 } 2422 2423 if (Feature == "bmi") { 2424 HasBMI = true; 2425 continue; 2426 } 2427 2428 if (Feature == "bmi2") { 2429 HasBMI2 = true; 2430 continue; 2431 } 2432 2433 if (Feature == "popcnt") { 2434 HasPOPCNT = true; 2435 continue; 2436 } 2437 2438 if (Feature == "rtm") { 2439 HasRTM = true; 2440 continue; 2441 } 2442 2443 if (Feature == "prfchw") { 2444 HasPRFCHW = true; 2445 continue; 2446 } 2447 2448 if (Feature == "rdseed") { 2449 HasRDSEED = true; 2450 continue; 2451 } 2452 2453 if (Feature == "tbm") { 2454 HasTBM = true; 2455 continue; 2456 } 2457 2458 if (Feature == "fma") { 2459 HasFMA = true; 2460 continue; 2461 } 2462 2463 if (Feature == "f16c") { 2464 HasF16C = true; 2465 continue; 2466 } 2467 2468 if (Feature == "avx512cd") { 2469 HasAVX512CD = true; 2470 continue; 2471 } 2472 2473 if (Feature == "avx512er") { 2474 HasAVX512ER = true; 2475 continue; 2476 } 2477 2478 if (Feature == "avx512pf") { 2479 HasAVX512PF = true; 2480 continue; 2481 } 2482 2483 if (Feature == "sha") { 2484 HasSHA = true; 2485 continue; 2486 } 2487 2488 if (Feature == "cx16") { 2489 HasCX16 = true; 2490 continue; 2491 } 2492 2493 assert(Features[i][0] == '+' && "Invalid target feature!"); 2494 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2495 .Case("avx512f", AVX512F) 2496 .Case("avx2", AVX2) 2497 .Case("avx", AVX) 2498 .Case("sse4.2", SSE42) 2499 .Case("sse4.1", SSE41) 2500 .Case("ssse3", SSSE3) 2501 .Case("sse3", SSE3) 2502 .Case("sse2", SSE2) 2503 .Case("sse", SSE1) 2504 .Default(NoSSE); 2505 SSELevel = std::max(SSELevel, Level); 2506 2507 MMX3DNowEnum ThreeDNowLevel = 2508 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2509 .Case("3dnowa", AMD3DNowAthlon) 2510 .Case("3dnow", AMD3DNow) 2511 .Case("mmx", MMX) 2512 .Default(NoMMX3DNow); 2513 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2514 2515 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2516 .Case("xop", XOP) 2517 .Case("fma4", FMA4) 2518 .Case("sse4a", SSE4A) 2519 .Default(NoXOP); 2520 XOPLevel = std::max(XOPLevel, XLevel); 2521 } 2522 2523 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2524 // Can't do this earlier because we need to be able to explicitly enable 2525 // popcnt and still disable sse4.2. 2526 if (!HasPOPCNT && SSELevel >= SSE42 && 2527 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2528 HasPOPCNT = true; 2529 Features.push_back("+popcnt"); 2530 } 2531 2532 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2533 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2534 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2535 HasPRFCHW = true; 2536 Features.push_back("+prfchw"); 2537 } 2538 2539 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2540 // matches the selected sse level. 2541 if (FPMath == FP_SSE && SSELevel < SSE1) { 2542 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2543 return false; 2544 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2545 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2546 return false; 2547 } 2548 2549 // Don't tell the backend if we're turning off mmx; it will end up disabling 2550 // SSE, which we don't want. 2551 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2552 // then enable MMX. 2553 std::vector<std::string>::iterator it; 2554 it = std::find(Features.begin(), Features.end(), "-mmx"); 2555 if (it != Features.end()) 2556 Features.erase(it); 2557 else if (SSELevel > NoSSE) 2558 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2559 return true; 2560} 2561 2562/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2563/// definitions for this particular subtarget. 2564void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2565 MacroBuilder &Builder) const { 2566 // Target identification. 2567 if (getTriple().getArch() == llvm::Triple::x86_64) { 2568 Builder.defineMacro("__amd64__"); 2569 Builder.defineMacro("__amd64"); 2570 Builder.defineMacro("__x86_64"); 2571 Builder.defineMacro("__x86_64__"); 2572 } else { 2573 DefineStd(Builder, "i386", Opts); 2574 } 2575 2576 // Subtarget options. 2577 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2578 // truly should be based on -mtune options. 2579 switch (CPU) { 2580 case CK_Generic: 2581 break; 2582 case CK_i386: 2583 // The rest are coming from the i386 define above. 2584 Builder.defineMacro("__tune_i386__"); 2585 break; 2586 case CK_i486: 2587 case CK_WinChipC6: 2588 case CK_WinChip2: 2589 case CK_C3: 2590 defineCPUMacros(Builder, "i486"); 2591 break; 2592 case CK_PentiumMMX: 2593 Builder.defineMacro("__pentium_mmx__"); 2594 Builder.defineMacro("__tune_pentium_mmx__"); 2595 // Fallthrough 2596 case CK_i586: 2597 case CK_Pentium: 2598 defineCPUMacros(Builder, "i586"); 2599 defineCPUMacros(Builder, "pentium"); 2600 break; 2601 case CK_Pentium3: 2602 case CK_Pentium3M: 2603 case CK_PentiumM: 2604 Builder.defineMacro("__tune_pentium3__"); 2605 // Fallthrough 2606 case CK_Pentium2: 2607 case CK_C3_2: 2608 Builder.defineMacro("__tune_pentium2__"); 2609 // Fallthrough 2610 case CK_PentiumPro: 2611 Builder.defineMacro("__tune_i686__"); 2612 Builder.defineMacro("__tune_pentiumpro__"); 2613 // Fallthrough 2614 case CK_i686: 2615 Builder.defineMacro("__i686"); 2616 Builder.defineMacro("__i686__"); 2617 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2618 Builder.defineMacro("__pentiumpro"); 2619 Builder.defineMacro("__pentiumpro__"); 2620 break; 2621 case CK_Pentium4: 2622 case CK_Pentium4M: 2623 defineCPUMacros(Builder, "pentium4"); 2624 break; 2625 case CK_Yonah: 2626 case CK_Prescott: 2627 case CK_Nocona: 2628 defineCPUMacros(Builder, "nocona"); 2629 break; 2630 case CK_Core2: 2631 case CK_Penryn: 2632 defineCPUMacros(Builder, "core2"); 2633 break; 2634 case CK_Atom: 2635 defineCPUMacros(Builder, "atom"); 2636 break; 2637 case CK_Silvermont: 2638 defineCPUMacros(Builder, "slm"); 2639 break; 2640 case CK_Corei7: 2641 case CK_Corei7AVX: 2642 case CK_CoreAVXi: 2643 case CK_CoreAVX2: 2644 defineCPUMacros(Builder, "corei7"); 2645 break; 2646 case CK_KNL: 2647 defineCPUMacros(Builder, "knl"); 2648 break; 2649 case CK_K6_2: 2650 Builder.defineMacro("__k6_2__"); 2651 Builder.defineMacro("__tune_k6_2__"); 2652 // Fallthrough 2653 case CK_K6_3: 2654 if (CPU != CK_K6_2) { // In case of fallthrough 2655 // FIXME: GCC may be enabling these in cases where some other k6 2656 // architecture is specified but -m3dnow is explicitly provided. The 2657 // exact semantics need to be determined and emulated here. 2658 Builder.defineMacro("__k6_3__"); 2659 Builder.defineMacro("__tune_k6_3__"); 2660 } 2661 // Fallthrough 2662 case CK_K6: 2663 defineCPUMacros(Builder, "k6"); 2664 break; 2665 case CK_Athlon: 2666 case CK_AthlonThunderbird: 2667 case CK_Athlon4: 2668 case CK_AthlonXP: 2669 case CK_AthlonMP: 2670 defineCPUMacros(Builder, "athlon"); 2671 if (SSELevel != NoSSE) { 2672 Builder.defineMacro("__athlon_sse__"); 2673 Builder.defineMacro("__tune_athlon_sse__"); 2674 } 2675 break; 2676 case CK_K8: 2677 case CK_K8SSE3: 2678 case CK_x86_64: 2679 case CK_Opteron: 2680 case CK_OpteronSSE3: 2681 case CK_Athlon64: 2682 case CK_Athlon64SSE3: 2683 case CK_AthlonFX: 2684 defineCPUMacros(Builder, "k8"); 2685 break; 2686 case CK_AMDFAM10: 2687 defineCPUMacros(Builder, "amdfam10"); 2688 break; 2689 case CK_BTVER1: 2690 defineCPUMacros(Builder, "btver1"); 2691 break; 2692 case CK_BTVER2: 2693 defineCPUMacros(Builder, "btver2"); 2694 break; 2695 case CK_BDVER1: 2696 defineCPUMacros(Builder, "bdver1"); 2697 break; 2698 case CK_BDVER2: 2699 defineCPUMacros(Builder, "bdver2"); 2700 break; 2701 case CK_BDVER3: 2702 defineCPUMacros(Builder, "bdver3"); 2703 break; 2704 case CK_Geode: 2705 defineCPUMacros(Builder, "geode"); 2706 break; 2707 } 2708 2709 // Target properties. 2710 Builder.defineMacro("__LITTLE_ENDIAN__"); 2711 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2712 2713 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2714 // functions in glibc header files that use FP Stack inline asm which the 2715 // backend can't deal with (PR879). 2716 Builder.defineMacro("__NO_MATH_INLINES"); 2717 2718 if (HasAES) 2719 Builder.defineMacro("__AES__"); 2720 2721 if (HasPCLMUL) 2722 Builder.defineMacro("__PCLMUL__"); 2723 2724 if (HasLZCNT) 2725 Builder.defineMacro("__LZCNT__"); 2726 2727 if (HasRDRND) 2728 Builder.defineMacro("__RDRND__"); 2729 2730 if (HasBMI) 2731 Builder.defineMacro("__BMI__"); 2732 2733 if (HasBMI2) 2734 Builder.defineMacro("__BMI2__"); 2735 2736 if (HasPOPCNT) 2737 Builder.defineMacro("__POPCNT__"); 2738 2739 if (HasRTM) 2740 Builder.defineMacro("__RTM__"); 2741 2742 if (HasPRFCHW) 2743 Builder.defineMacro("__PRFCHW__"); 2744 2745 if (HasRDSEED) 2746 Builder.defineMacro("__RDSEED__"); 2747 2748 if (HasTBM) 2749 Builder.defineMacro("__TBM__"); 2750 2751 switch (XOPLevel) { 2752 case XOP: 2753 Builder.defineMacro("__XOP__"); 2754 case FMA4: 2755 Builder.defineMacro("__FMA4__"); 2756 case SSE4A: 2757 Builder.defineMacro("__SSE4A__"); 2758 case NoXOP: 2759 break; 2760 } 2761 2762 if (HasFMA) 2763 Builder.defineMacro("__FMA__"); 2764 2765 if (HasF16C) 2766 Builder.defineMacro("__F16C__"); 2767 2768 if (HasAVX512CD) 2769 Builder.defineMacro("__AVX512CD__"); 2770 if (HasAVX512ER) 2771 Builder.defineMacro("__AVX512ER__"); 2772 if (HasAVX512PF) 2773 Builder.defineMacro("__AVX512PF__"); 2774 2775 if (HasSHA) 2776 Builder.defineMacro("__SHA__"); 2777 2778 if (HasCX16) 2779 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2780 2781 // Each case falls through to the previous one here. 2782 switch (SSELevel) { 2783 case AVX512F: 2784 Builder.defineMacro("__AVX512F__"); 2785 case AVX2: 2786 Builder.defineMacro("__AVX2__"); 2787 case AVX: 2788 Builder.defineMacro("__AVX__"); 2789 case SSE42: 2790 Builder.defineMacro("__SSE4_2__"); 2791 case SSE41: 2792 Builder.defineMacro("__SSE4_1__"); 2793 case SSSE3: 2794 Builder.defineMacro("__SSSE3__"); 2795 case SSE3: 2796 Builder.defineMacro("__SSE3__"); 2797 case SSE2: 2798 Builder.defineMacro("__SSE2__"); 2799 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2800 case SSE1: 2801 Builder.defineMacro("__SSE__"); 2802 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2803 case NoSSE: 2804 break; 2805 } 2806 2807 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2808 switch (SSELevel) { 2809 case AVX512F: 2810 case AVX2: 2811 case AVX: 2812 case SSE42: 2813 case SSE41: 2814 case SSSE3: 2815 case SSE3: 2816 case SSE2: 2817 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2818 break; 2819 case SSE1: 2820 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2821 break; 2822 default: 2823 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2824 } 2825 } 2826 2827 // Each case falls through to the previous one here. 2828 switch (MMX3DNowLevel) { 2829 case AMD3DNowAthlon: 2830 Builder.defineMacro("__3dNOW_A__"); 2831 case AMD3DNow: 2832 Builder.defineMacro("__3dNOW__"); 2833 case MMX: 2834 Builder.defineMacro("__MMX__"); 2835 case NoMMX3DNow: 2836 break; 2837 } 2838 2839 if (CPU >= CK_i486) { 2840 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2841 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2842 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2843 } 2844 if (CPU >= CK_i586) 2845 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2846} 2847 2848bool X86TargetInfo::hasFeature(StringRef Feature) const { 2849 return llvm::StringSwitch<bool>(Feature) 2850 .Case("aes", HasAES) 2851 .Case("avx", SSELevel >= AVX) 2852 .Case("avx2", SSELevel >= AVX2) 2853 .Case("avx512f", SSELevel >= AVX512F) 2854 .Case("avx512cd", HasAVX512CD) 2855 .Case("avx512er", HasAVX512ER) 2856 .Case("avx512pf", HasAVX512PF) 2857 .Case("bmi", HasBMI) 2858 .Case("bmi2", HasBMI2) 2859 .Case("cx16", HasCX16) 2860 .Case("f16c", HasF16C) 2861 .Case("fma", HasFMA) 2862 .Case("fma4", XOPLevel >= FMA4) 2863 .Case("tbm", HasTBM) 2864 .Case("lzcnt", HasLZCNT) 2865 .Case("rdrnd", HasRDRND) 2866 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2867 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2868 .Case("mmx", MMX3DNowLevel >= MMX) 2869 .Case("pclmul", HasPCLMUL) 2870 .Case("popcnt", HasPOPCNT) 2871 .Case("rtm", HasRTM) 2872 .Case("prfchw", HasPRFCHW) 2873 .Case("rdseed", HasRDSEED) 2874 .Case("sha", HasSHA) 2875 .Case("sse", SSELevel >= SSE1) 2876 .Case("sse2", SSELevel >= SSE2) 2877 .Case("sse3", SSELevel >= SSE3) 2878 .Case("ssse3", SSELevel >= SSSE3) 2879 .Case("sse4.1", SSELevel >= SSE41) 2880 .Case("sse4.2", SSELevel >= SSE42) 2881 .Case("sse4a", XOPLevel >= SSE4A) 2882 .Case("x86", true) 2883 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2884 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2885 .Case("xop", XOPLevel >= XOP) 2886 .Default(false); 2887} 2888 2889bool 2890X86TargetInfo::validateAsmConstraint(const char *&Name, 2891 TargetInfo::ConstraintInfo &Info) const { 2892 switch (*Name) { 2893 default: return false; 2894 case 'Y': // first letter of a pair: 2895 switch (*(Name+1)) { 2896 default: return false; 2897 case '0': // First SSE register. 2898 case 't': // Any SSE register, when SSE2 is enabled. 2899 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2900 case 'm': // any MMX register, when inter-unit moves enabled. 2901 break; // falls through to setAllowsRegister. 2902 } 2903 case 'a': // eax. 2904 case 'b': // ebx. 2905 case 'c': // ecx. 2906 case 'd': // edx. 2907 case 'S': // esi. 2908 case 'D': // edi. 2909 case 'A': // edx:eax. 2910 case 'f': // any x87 floating point stack register. 2911 case 't': // top of floating point stack. 2912 case 'u': // second from top of floating point stack. 2913 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2914 case 'y': // Any MMX register. 2915 case 'x': // Any SSE register. 2916 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2917 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2918 case 'l': // "Index" registers: any general register that can be used as an 2919 // index in a base+index memory access. 2920 Info.setAllowsRegister(); 2921 return true; 2922 case 'C': // SSE floating point constant. 2923 case 'G': // x87 floating point constant. 2924 case 'e': // 32-bit signed integer constant for use with zero-extending 2925 // x86_64 instructions. 2926 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2927 // x86_64 instructions. 2928 return true; 2929 } 2930} 2931 2932 2933std::string 2934X86TargetInfo::convertConstraint(const char *&Constraint) const { 2935 switch (*Constraint) { 2936 case 'a': return std::string("{ax}"); 2937 case 'b': return std::string("{bx}"); 2938 case 'c': return std::string("{cx}"); 2939 case 'd': return std::string("{dx}"); 2940 case 'S': return std::string("{si}"); 2941 case 'D': return std::string("{di}"); 2942 case 'p': // address 2943 return std::string("im"); 2944 case 't': // top of floating point stack. 2945 return std::string("{st}"); 2946 case 'u': // second from top of floating point stack. 2947 return std::string("{st(1)}"); // second from top of floating point stack. 2948 default: 2949 return std::string(1, *Constraint); 2950 } 2951} 2952} // end anonymous namespace 2953 2954namespace { 2955// X86-32 generic target 2956class X86_32TargetInfo : public X86TargetInfo { 2957public: 2958 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2959 DoubleAlign = LongLongAlign = 32; 2960 LongDoubleWidth = 96; 2961 LongDoubleAlign = 32; 2962 SuitableAlign = 128; 2963 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2964 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2965 "a0:0:64-f80:32:32-n8:16:32-S128"; 2966 SizeType = UnsignedInt; 2967 PtrDiffType = SignedInt; 2968 IntPtrType = SignedInt; 2969 RegParmMax = 3; 2970 2971 // Use fpret for all types. 2972 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2973 (1 << TargetInfo::Double) | 2974 (1 << TargetInfo::LongDouble)); 2975 2976 // x86-32 has atomics up to 8 bytes 2977 // FIXME: Check that we actually have cmpxchg8b before setting 2978 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2979 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2980 } 2981 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2982 return TargetInfo::CharPtrBuiltinVaList; 2983 } 2984 2985 int getEHDataRegisterNumber(unsigned RegNo) const { 2986 if (RegNo == 0) return 0; 2987 if (RegNo == 1) return 2; 2988 return -1; 2989 } 2990 virtual bool validateInputSize(StringRef Constraint, 2991 unsigned Size) const { 2992 switch (Constraint[0]) { 2993 default: break; 2994 case 'a': 2995 case 'b': 2996 case 'c': 2997 case 'd': 2998 return Size <= 32; 2999 } 3000 3001 return true; 3002 } 3003}; 3004} // end anonymous namespace 3005 3006namespace { 3007class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3008public: 3009 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3010 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3011 3012 virtual unsigned getFloatEvalMethod() const { 3013 unsigned Major, Minor, Micro; 3014 getTriple().getOSVersion(Major, Minor, Micro); 3015 // New NetBSD uses the default rounding mode. 3016 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3017 return X86_32TargetInfo::getFloatEvalMethod(); 3018 // NetBSD before 6.99.26 defaults to "double" rounding. 3019 return 1; 3020 } 3021}; 3022} // end anonymous namespace 3023 3024namespace { 3025class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3026public: 3027 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3028 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3029 SizeType = UnsignedLong; 3030 IntPtrType = SignedLong; 3031 PtrDiffType = SignedLong; 3032 } 3033}; 3034} // end anonymous namespace 3035 3036namespace { 3037class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3038public: 3039 BitrigI386TargetInfo(const llvm::Triple &Triple) 3040 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3041 SizeType = UnsignedLong; 3042 IntPtrType = SignedLong; 3043 PtrDiffType = SignedLong; 3044 } 3045}; 3046} // end anonymous namespace 3047 3048namespace { 3049class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3050public: 3051 DarwinI386TargetInfo(const llvm::Triple &Triple) 3052 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3053 LongDoubleWidth = 128; 3054 LongDoubleAlign = 128; 3055 SuitableAlign = 128; 3056 MaxVectorAlign = 256; 3057 SizeType = UnsignedLong; 3058 IntPtrType = SignedLong; 3059 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3060 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 3061 "a0:0:64-f80:128:128-n8:16:32-S128"; 3062 HasAlignMac68kSupport = true; 3063 } 3064 3065}; 3066} // end anonymous namespace 3067 3068namespace { 3069// x86-32 Windows target 3070class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3071public: 3072 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3073 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3074 TLSSupported = false; 3075 WCharType = UnsignedShort; 3076 DoubleAlign = LongLongAlign = 64; 3077 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3078 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 3079 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 3080 } 3081 virtual void getTargetDefines(const LangOptions &Opts, 3082 MacroBuilder &Builder) const { 3083 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3084 } 3085}; 3086} // end anonymous namespace 3087 3088namespace { 3089 3090// x86-32 Windows Visual Studio target 3091class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3092public: 3093 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3094 : WindowsX86_32TargetInfo(Triple) { 3095 LongDoubleWidth = LongDoubleAlign = 64; 3096 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3097 } 3098 virtual void getTargetDefines(const LangOptions &Opts, 3099 MacroBuilder &Builder) const { 3100 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3101 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3102 // The value of the following reflects processor type. 3103 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3104 // We lost the original triple, so we use the default. 3105 Builder.defineMacro("_M_IX86", "600"); 3106 } 3107}; 3108} // end anonymous namespace 3109 3110namespace { 3111// x86-32 MinGW target 3112class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3113public: 3114 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3115 : WindowsX86_32TargetInfo(Triple) {} 3116 virtual void getTargetDefines(const LangOptions &Opts, 3117 MacroBuilder &Builder) const { 3118 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3119 DefineStd(Builder, "WIN32", Opts); 3120 DefineStd(Builder, "WINNT", Opts); 3121 Builder.defineMacro("_X86_"); 3122 Builder.defineMacro("__MSVCRT__"); 3123 Builder.defineMacro("__MINGW32__"); 3124 3125 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3126 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3127 if (Opts.MicrosoftExt) 3128 // Provide "as-is" __declspec. 3129 Builder.defineMacro("__declspec", "__declspec"); 3130 else 3131 // Provide alias of __attribute__ like mingw32-gcc. 3132 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3133 } 3134}; 3135} // end anonymous namespace 3136 3137namespace { 3138// x86-32 Cygwin target 3139class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3140public: 3141 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3142 : X86_32TargetInfo(Triple) { 3143 TLSSupported = false; 3144 WCharType = UnsignedShort; 3145 DoubleAlign = LongLongAlign = 64; 3146 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3147 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3148 "a0:0:64-f80:32:32-n8:16:32-S32"; 3149 } 3150 virtual void getTargetDefines(const LangOptions &Opts, 3151 MacroBuilder &Builder) const { 3152 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3153 Builder.defineMacro("_X86_"); 3154 Builder.defineMacro("__CYGWIN__"); 3155 Builder.defineMacro("__CYGWIN32__"); 3156 DefineStd(Builder, "unix", Opts); 3157 if (Opts.CPlusPlus) 3158 Builder.defineMacro("_GNU_SOURCE"); 3159 } 3160}; 3161} // end anonymous namespace 3162 3163namespace { 3164// x86-32 Haiku target 3165class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3166public: 3167 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3168 SizeType = UnsignedLong; 3169 IntPtrType = SignedLong; 3170 PtrDiffType = SignedLong; 3171 ProcessIDType = SignedLong; 3172 this->UserLabelPrefix = ""; 3173 this->TLSSupported = false; 3174 } 3175 virtual void getTargetDefines(const LangOptions &Opts, 3176 MacroBuilder &Builder) const { 3177 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3178 Builder.defineMacro("__INTEL__"); 3179 Builder.defineMacro("__HAIKU__"); 3180 } 3181}; 3182} // end anonymous namespace 3183 3184// RTEMS Target 3185template<typename Target> 3186class RTEMSTargetInfo : public OSTargetInfo<Target> { 3187protected: 3188 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3189 MacroBuilder &Builder) const { 3190 // RTEMS defines; list based off of gcc output 3191 3192 Builder.defineMacro("__rtems__"); 3193 Builder.defineMacro("__ELF__"); 3194 } 3195 3196public: 3197 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3198 this->UserLabelPrefix = ""; 3199 3200 switch (Triple.getArch()) { 3201 default: 3202 case llvm::Triple::x86: 3203 // this->MCountName = ".mcount"; 3204 break; 3205 case llvm::Triple::mips: 3206 case llvm::Triple::mipsel: 3207 case llvm::Triple::ppc: 3208 case llvm::Triple::ppc64: 3209 case llvm::Triple::ppc64le: 3210 // this->MCountName = "_mcount"; 3211 break; 3212 case llvm::Triple::arm: 3213 // this->MCountName = "__mcount"; 3214 break; 3215 } 3216 } 3217}; 3218 3219namespace { 3220// x86-32 RTEMS target 3221class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3222public: 3223 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3224 SizeType = UnsignedLong; 3225 IntPtrType = SignedLong; 3226 PtrDiffType = SignedLong; 3227 this->UserLabelPrefix = ""; 3228 } 3229 virtual void getTargetDefines(const LangOptions &Opts, 3230 MacroBuilder &Builder) const { 3231 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3232 Builder.defineMacro("__INTEL__"); 3233 Builder.defineMacro("__rtems__"); 3234 } 3235}; 3236} // end anonymous namespace 3237 3238namespace { 3239// x86-64 generic target 3240class X86_64TargetInfo : public X86TargetInfo { 3241public: 3242 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3243 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3244 LongDoubleWidth = 128; 3245 LongDoubleAlign = 128; 3246 LargeArrayMinWidth = 128; 3247 LargeArrayAlign = 128; 3248 SuitableAlign = 128; 3249 IntMaxType = SignedLong; 3250 UIntMaxType = UnsignedLong; 3251 Int64Type = SignedLong; 3252 RegParmMax = 6; 3253 3254 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3255 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3256 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 3257 3258 // Use fpret only for long double. 3259 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3260 3261 // Use fp2ret for _Complex long double. 3262 ComplexLongDoubleUsesFP2Ret = true; 3263 3264 // x86-64 has atomics up to 16 bytes. 3265 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3266 // on CPUs with cmpxchg16b 3267 MaxAtomicPromoteWidth = 128; 3268 MaxAtomicInlineWidth = 64; 3269 } 3270 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3271 return TargetInfo::X86_64ABIBuiltinVaList; 3272 } 3273 3274 int getEHDataRegisterNumber(unsigned RegNo) const { 3275 if (RegNo == 0) return 0; 3276 if (RegNo == 1) return 1; 3277 return -1; 3278 } 3279 3280 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3281 return (CC == CC_C || 3282 CC == CC_IntelOclBicc || 3283 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3284 } 3285 3286 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3287 return CC_C; 3288 } 3289 3290}; 3291} // end anonymous namespace 3292 3293namespace { 3294// x86-64 Windows target 3295class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3296public: 3297 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3298 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3299 TLSSupported = false; 3300 WCharType = UnsignedShort; 3301 LongWidth = LongAlign = 32; 3302 DoubleAlign = LongLongAlign = 64; 3303 IntMaxType = SignedLongLong; 3304 UIntMaxType = UnsignedLongLong; 3305 Int64Type = SignedLongLong; 3306 SizeType = UnsignedLongLong; 3307 PtrDiffType = SignedLongLong; 3308 IntPtrType = SignedLongLong; 3309 this->UserLabelPrefix = ""; 3310 } 3311 virtual void getTargetDefines(const LangOptions &Opts, 3312 MacroBuilder &Builder) const { 3313 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3314 Builder.defineMacro("_WIN64"); 3315 } 3316 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3317 return TargetInfo::CharPtrBuiltinVaList; 3318 } 3319 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3320 return (CC == CC_C || 3321 CC == CC_IntelOclBicc || 3322 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3323 } 3324}; 3325} // end anonymous namespace 3326 3327namespace { 3328// x86-64 Windows Visual Studio target 3329class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3330public: 3331 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3332 : WindowsX86_64TargetInfo(Triple) { 3333 LongDoubleWidth = LongDoubleAlign = 64; 3334 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3335 } 3336 virtual void getTargetDefines(const LangOptions &Opts, 3337 MacroBuilder &Builder) const { 3338 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3339 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3340 Builder.defineMacro("_M_X64"); 3341 Builder.defineMacro("_M_AMD64"); 3342 } 3343}; 3344} // end anonymous namespace 3345 3346namespace { 3347// x86-64 MinGW target 3348class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3349public: 3350 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3351 : WindowsX86_64TargetInfo(Triple) {} 3352 virtual void getTargetDefines(const LangOptions &Opts, 3353 MacroBuilder &Builder) const { 3354 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3355 DefineStd(Builder, "WIN64", Opts); 3356 Builder.defineMacro("__MSVCRT__"); 3357 Builder.defineMacro("__MINGW32__"); 3358 Builder.defineMacro("__MINGW64__"); 3359 3360 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3361 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3362 if (Opts.MicrosoftExt) 3363 // Provide "as-is" __declspec. 3364 Builder.defineMacro("__declspec", "__declspec"); 3365 else 3366 // Provide alias of __attribute__ like mingw32-gcc. 3367 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3368 } 3369}; 3370} // end anonymous namespace 3371 3372namespace { 3373class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3374public: 3375 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3376 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3377 Int64Type = SignedLongLong; 3378 MaxVectorAlign = 256; 3379 } 3380}; 3381} // end anonymous namespace 3382 3383namespace { 3384class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3385public: 3386 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3387 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3388 IntMaxType = SignedLongLong; 3389 UIntMaxType = UnsignedLongLong; 3390 Int64Type = SignedLongLong; 3391 } 3392}; 3393} // end anonymous namespace 3394 3395namespace { 3396class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3397public: 3398 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3399 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3400 IntMaxType = SignedLongLong; 3401 UIntMaxType = UnsignedLongLong; 3402 Int64Type = SignedLongLong; 3403 } 3404}; 3405} 3406 3407namespace { 3408class AArch64TargetInfo : public TargetInfo { 3409 static const char * const GCCRegNames[]; 3410 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3411 3412 enum FPUModeEnum { 3413 FPUMode, 3414 NeonMode 3415 }; 3416 3417 unsigned FPU; 3418 unsigned Crypto; 3419 static const Builtin::Info BuiltinInfo[]; 3420 3421public: 3422 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3423 BigEndian = false; 3424 LongWidth = LongAlign = 64; 3425 LongDoubleWidth = LongDoubleAlign = 128; 3426 PointerWidth = PointerAlign = 64; 3427 SuitableAlign = 128; 3428 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3429 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-" 3430 "f128:128:128-n32:64-S128"; 3431 3432 WCharType = UnsignedInt; 3433 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3434 3435 // AArch64 backend supports 64-bit operations at the moment. In principle 3436 // 128-bit is possible if register-pairs are used. 3437 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3438 3439 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3440 } 3441 virtual void getTargetDefines(const LangOptions &Opts, 3442 MacroBuilder &Builder) const { 3443 // GCC defines theses currently 3444 Builder.defineMacro("__aarch64__"); 3445 Builder.defineMacro("__AARCH64EL__"); 3446 3447 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3448 Builder.defineMacro("__ARM_ACLE", "200"); 3449 Builder.defineMacro("__ARM_ARCH", "8"); 3450 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3451 3452 Builder.defineMacro("__ARM_64BIT_STATE"); 3453 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3454 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3455 3456 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3457 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3458 Builder.defineMacro("__ARM_FEATURE_FMA"); 3459 Builder.defineMacro("__ARM_FEATURE_DIV"); 3460 3461 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3462 3463 // 0xe implies support for half, single and double precision operations. 3464 Builder.defineMacro("__ARM_FP", "0xe"); 3465 3466 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3467 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3468 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3469 3470 if (Opts.FastMath || Opts.FiniteMathOnly) 3471 Builder.defineMacro("__ARM_FP_FAST"); 3472 3473 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3474 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3475 3476 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3477 Opts.ShortWChar ? "2" : "4"); 3478 3479 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3480 Opts.ShortEnums ? "1" : "4"); 3481 3482 if (BigEndian) 3483 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3484 3485 if (FPU == NeonMode) { 3486 Builder.defineMacro("__ARM_NEON"); 3487 // 64-bit NEON supports half, single and double precision operations. 3488 Builder.defineMacro("__ARM_NEON_FP", "7"); 3489 } 3490 3491 if (Crypto) { 3492 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3493 } 3494 } 3495 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3496 unsigned &NumRecords) const { 3497 Records = BuiltinInfo; 3498 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3499 } 3500 virtual bool hasFeature(StringRef Feature) const { 3501 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3502 } 3503 3504 virtual bool setCPU(const std::string &Name) { 3505 return llvm::StringSwitch<bool>(Name) 3506 .Case("generic", true) 3507 .Cases("cortex-a53", "cortex-a57", true) 3508 .Default(false); 3509 } 3510 3511 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3512 DiagnosticsEngine &Diags) { 3513 FPU = FPUMode; 3514 Crypto = 0; 3515 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3516 if (Features[i] == "+neon") 3517 FPU = NeonMode; 3518 if (Features[i] == "+crypto") 3519 Crypto = 1; 3520 } 3521 return true; 3522 } 3523 3524 virtual void getGCCRegNames(const char *const *&Names, 3525 unsigned &NumNames) const; 3526 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3527 unsigned &NumAliases) const; 3528 3529 virtual bool isCLZForZeroUndef() const { return false; } 3530 3531 virtual bool validateAsmConstraint(const char *&Name, 3532 TargetInfo::ConstraintInfo &Info) const { 3533 switch (*Name) { 3534 default: return false; 3535 case 'w': // An FP/SIMD vector register 3536 Info.setAllowsRegister(); 3537 return true; 3538 case 'I': // Constant that can be used with an ADD instruction 3539 case 'J': // Constant that can be used with a SUB instruction 3540 case 'K': // Constant that can be used with a 32-bit logical instruction 3541 case 'L': // Constant that can be used with a 64-bit logical instruction 3542 case 'M': // Constant that can be used as a 32-bit MOV immediate 3543 case 'N': // Constant that can be used as a 64-bit MOV immediate 3544 case 'Y': // Floating point constant zero 3545 case 'Z': // Integer constant zero 3546 return true; 3547 case 'Q': // A memory reference with base register and no offset 3548 Info.setAllowsMemory(); 3549 return true; 3550 case 'S': // A symbolic address 3551 Info.setAllowsRegister(); 3552 return true; 3553 case 'U': 3554 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3555 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3556 // Usa: An absolute symbolic address 3557 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3558 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3559 } 3560 } 3561 3562 virtual const char *getClobbers() const { 3563 // There are no AArch64 clobbers shared by all asm statements. 3564 return ""; 3565 } 3566 3567 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3568 return TargetInfo::AArch64ABIBuiltinVaList; 3569 } 3570}; 3571 3572const char * const AArch64TargetInfo::GCCRegNames[] = { 3573 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3574 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3575 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3576 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3577 3578 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3579 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3580 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3581 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3582 3583 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3584 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3585 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3586 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3587 3588 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3589 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3590 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3591 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3592 3593 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3594 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3595 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3596 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3597 3598 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3599 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3600 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3601 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3602 3603 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3604 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3605 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3606 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3607}; 3608 3609void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3610 unsigned &NumNames) const { 3611 Names = GCCRegNames; 3612 NumNames = llvm::array_lengthof(GCCRegNames); 3613} 3614 3615const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3616 { { "x16" }, "ip0"}, 3617 { { "x17" }, "ip1"}, 3618 { { "x29" }, "fp" }, 3619 { { "x30" }, "lr" } 3620}; 3621 3622void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3623 unsigned &NumAliases) const { 3624 Aliases = GCCRegAliases; 3625 NumAliases = llvm::array_lengthof(GCCRegAliases); 3626 3627} 3628 3629const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3630#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3631#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3632 ALL_LANGUAGES }, 3633#include "clang/Basic/BuiltinsAArch64.def" 3634}; 3635 3636} // end anonymous namespace 3637 3638namespace { 3639class ARMTargetInfo : public TargetInfo { 3640 // Possible FPU choices. 3641 enum FPUMode { 3642 VFP2FPU = (1 << 0), 3643 VFP3FPU = (1 << 1), 3644 VFP4FPU = (1 << 2), 3645 NeonFPU = (1 << 3), 3646 FPARMV8 = (1 << 4) 3647 }; 3648 3649 // Possible HWDiv features. 3650 enum HWDivMode { 3651 HWDivThumb = (1 << 0), 3652 HWDivARM = (1 << 1) 3653 }; 3654 3655 static bool FPUModeIsVFP(FPUMode Mode) { 3656 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3657 } 3658 3659 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3660 static const char * const GCCRegNames[]; 3661 3662 std::string ABI, CPU; 3663 3664 enum { 3665 FP_Default, 3666 FP_VFP, 3667 FP_Neon 3668 } FPMath; 3669 3670 unsigned FPU : 5; 3671 3672 unsigned IsAAPCS : 1; 3673 unsigned IsThumb : 1; 3674 unsigned HWDiv : 2; 3675 3676 // Initialized via features. 3677 unsigned SoftFloat : 1; 3678 unsigned SoftFloatABI : 1; 3679 3680 unsigned CRC : 1; 3681 3682 static const Builtin::Info BuiltinInfo[]; 3683 3684 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3685 // On linux, binaries targeting old cpus call functions in libgcc to 3686 // perform atomic operations. The implementation in libgcc then calls into 3687 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3688 // is that if we assume the kernel is at least as recent as the hardware, 3689 // it is safe to use atomic instructions on armv6 and newer. 3690 if (!T.isOSLinux() && 3691 T.getOS() != llvm::Triple::FreeBSD && 3692 T.getOS() != llvm::Triple::NetBSD && 3693 T.getOS() != llvm::Triple::Bitrig) 3694 return false; 3695 StringRef ArchName = T.getArchName(); 3696 if (T.getArch() == llvm::Triple::arm) { 3697 if (!ArchName.startswith("armv")) 3698 return false; 3699 StringRef VersionStr = ArchName.substr(4); 3700 unsigned Version; 3701 if (VersionStr.getAsInteger(10, Version)) 3702 return false; 3703 return Version >= 6; 3704 } 3705 assert(T.getArch() == llvm::Triple::thumb); 3706 if (!ArchName.startswith("thumbv")) 3707 return false; 3708 StringRef VersionStr = ArchName.substr(6); 3709 unsigned Version; 3710 if (VersionStr.getAsInteger(10, Version)) 3711 return false; 3712 return Version >= 7; 3713 } 3714 3715public: 3716 ARMTargetInfo(const llvm::Triple &Triple) 3717 : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"), 3718 FPMath(FP_Default), IsAAPCS(true) { 3719 BigEndian = false; 3720 switch (getTriple().getOS()) { 3721 case llvm::Triple::NetBSD: 3722 SizeType = UnsignedLong; 3723 PtrDiffType = SignedLong; 3724 WCharType = SignedInt; 3725 break; 3726 default: 3727 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3728 WCharType = UnsignedInt; 3729 SizeType = UnsignedInt; 3730 PtrDiffType = SignedInt; 3731 break; 3732 } 3733 3734 // {} in inline assembly are neon specifiers, not assembly variant 3735 // specifiers. 3736 NoAsmVariants = true; 3737 3738 // FIXME: Should we just treat this as a feature? 3739 IsThumb = getTriple().getArchName().startswith("thumb"); 3740 if (IsThumb) { 3741 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3742 // so set preferred for small types to 32. 3743 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3744 "i64:64:64-f32:32:32-f64:64:64-" 3745 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3746 } else { 3747 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3748 "i64:64:64-f32:32:32-f64:64:64-" 3749 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3750 } 3751 3752 // ARM targets default to using the ARM C++ ABI. 3753 TheCXXABI.set(TargetCXXABI::GenericARM); 3754 3755 // ARM has atomics up to 8 bytes 3756 MaxAtomicPromoteWidth = 64; 3757 if (shouldUseInlineAtomic(getTriple())) 3758 MaxAtomicInlineWidth = 64; 3759 3760 // Do force alignment of members that follow zero length bitfields. If 3761 // the alignment of the zero-length bitfield is greater than the member 3762 // that follows it, `bar', `bar' will be aligned as the type of the 3763 // zero length bitfield. 3764 UseZeroLengthBitfieldAlignment = true; 3765 } 3766 virtual const char *getABI() const { return ABI.c_str(); } 3767 virtual bool setABI(const std::string &Name) { 3768 ABI = Name; 3769 3770 // The defaults (above) are for AAPCS, check if we need to change them. 3771 // 3772 // FIXME: We need support for -meabi... we could just mangle it into the 3773 // name. 3774 if (Name == "apcs-gnu") { 3775 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3776 // size_t is unsigned int on FreeBSD. 3777 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3778 SizeType = UnsignedLong; 3779 3780 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3781 WCharType = SignedInt; 3782 3783 // Do not respect the alignment of bit-field types when laying out 3784 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3785 UseBitFieldTypeAlignment = false; 3786 3787 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3788 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3789 /// gcc. 3790 ZeroLengthBitfieldBoundary = 32; 3791 3792 IsAAPCS = false; 3793 3794 if (IsThumb) { 3795 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3796 // so set preferred for small types to 32. 3797 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3798 "i64:32:64-f32:32:32-f64:32:64-" 3799 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3800 } else { 3801 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3802 "i64:32:64-f32:32:32-f64:32:64-" 3803 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3804 } 3805 3806 // FIXME: Override "preferred align" for double and long long. 3807 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3808 // size_t is unsigned long on Darwin. 3809 if (getTriple().isOSDarwin()) 3810 SizeType = UnsignedLong; 3811 IsAAPCS = true; 3812 // FIXME: Enumerated types are variable width in straight AAPCS. 3813 } else if (Name == "aapcs-linux") { 3814 IsAAPCS = true; 3815 } else 3816 return false; 3817 3818 return true; 3819 } 3820 3821 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3822 StringRef ArchName = getTriple().getArchName(); 3823 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3824 Features["vfp2"] = true; 3825 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3826 CPU == "cortex-a9-mp") { 3827 Features["vfp3"] = true; 3828 Features["neon"] = true; 3829 } 3830 else if (CPU == "cortex-a5") { 3831 Features["vfp4"] = true; 3832 Features["neon"] = true; 3833 } else if (CPU == "swift" || CPU == "cortex-a7" || CPU == "cortex-a15") { 3834 Features["vfp4"] = true; 3835 Features["neon"] = true; 3836 Features["hwdiv"] = true; 3837 Features["hwdiv-arm"] = true; 3838 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3839 Features["fp-armv8"] = true; 3840 Features["neon"] = true; 3841 Features["hwdiv"] = true; 3842 Features["hwdiv-arm"] = true; 3843 Features["crc"] = true; 3844 } else if (CPU == "cortex-r5" || CPU == "cortex-m3" || 3845 CPU == "cortex-m4" || 3846 // Enable the hwdiv extension for all v8a AArch32 cores by 3847 // default. 3848 ArchName == "armv8a" || ArchName == "armv8" || 3849 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3850 Features["hwdiv"] = true; 3851 Features["hwdiv-arm"] = true; 3852 } 3853 } 3854 3855 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3856 DiagnosticsEngine &Diags) { 3857 FPU = 0; 3858 CRC = 0; 3859 SoftFloat = SoftFloatABI = false; 3860 HWDiv = 0; 3861 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3862 if (Features[i] == "+soft-float") 3863 SoftFloat = true; 3864 else if (Features[i] == "+soft-float-abi") 3865 SoftFloatABI = true; 3866 else if (Features[i] == "+vfp2") 3867 FPU |= VFP2FPU; 3868 else if (Features[i] == "+vfp3") 3869 FPU |= VFP3FPU; 3870 else if (Features[i] == "+vfp4") 3871 FPU |= VFP4FPU; 3872 else if (Features[i] == "+fp-armv8") 3873 FPU |= FPARMV8; 3874 else if (Features[i] == "+neon") 3875 FPU |= NeonFPU; 3876 else if (Features[i] == "+hwdiv") 3877 HWDiv |= HWDivThumb; 3878 else if (Features[i] == "+hwdiv-arm") 3879 HWDiv |= HWDivARM; 3880 else if (Features[i] == "+crc") 3881 CRC = 1; 3882 } 3883 3884 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3885 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3886 return false; 3887 } 3888 3889 if (FPMath == FP_Neon) 3890 Features.push_back("+neonfp"); 3891 else if (FPMath == FP_VFP) 3892 Features.push_back("-neonfp"); 3893 3894 // Remove front-end specific options which the backend handles differently. 3895 std::vector<std::string>::iterator it; 3896 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3897 if (it != Features.end()) 3898 Features.erase(it); 3899 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3900 if (it != Features.end()) 3901 Features.erase(it); 3902 return true; 3903 } 3904 3905 virtual bool hasFeature(StringRef Feature) const { 3906 return llvm::StringSwitch<bool>(Feature) 3907 .Case("arm", true) 3908 .Case("softfloat", SoftFloat) 3909 .Case("thumb", IsThumb) 3910 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3911 .Case("hwdiv", HWDiv & HWDivThumb) 3912 .Case("hwdiv-arm", HWDiv & HWDivARM) 3913 .Default(false); 3914 } 3915 // FIXME: Should we actually have some table instead of these switches? 3916 static const char *getCPUDefineSuffix(StringRef Name) { 3917 return llvm::StringSwitch<const char*>(Name) 3918 .Cases("arm8", "arm810", "4") 3919 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3920 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3921 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3922 .Case("ep9312", "4T") 3923 .Cases("arm10tdmi", "arm1020t", "5T") 3924 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3925 .Case("arm926ej-s", "5TEJ") 3926 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3927 .Cases("xscale", "iwmmxt", "5TE") 3928 .Case("arm1136j-s", "6J") 3929 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3930 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3931 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3932 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 3933 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A") 3934 .Cases("cortex-r4", "cortex-r5", "7R") 3935 .Case("cortex-a9-mp", "7F") 3936 .Case("swift", "7S") 3937 .Cases("cortex-m3", "cortex-m4", "7M") 3938 .Case("cortex-m0", "6M") 3939 .Cases("cortex-a53", "cortex-a57", "8A") 3940 .Default(0); 3941 } 3942 static const char *getCPUProfile(StringRef Name) { 3943 return llvm::StringSwitch<const char*>(Name) 3944 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3945 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A") 3946 .Cases("cortex-a53", "cortex-a57", "A") 3947 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3948 .Cases("cortex-r4", "cortex-r5", "R") 3949 .Default(""); 3950 } 3951 virtual bool setCPU(const std::string &Name) { 3952 if (!getCPUDefineSuffix(Name)) 3953 return false; 3954 3955 CPU = Name; 3956 return true; 3957 } 3958 virtual bool setFPMath(StringRef Name); 3959 virtual void getTargetDefines(const LangOptions &Opts, 3960 MacroBuilder &Builder) const { 3961 // Target identification. 3962 Builder.defineMacro("__arm"); 3963 Builder.defineMacro("__arm__"); 3964 3965 // Target properties. 3966 Builder.defineMacro("__ARMEL__"); 3967 Builder.defineMacro("__LITTLE_ENDIAN__"); 3968 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3969 3970 StringRef CPUArch = getCPUDefineSuffix(CPU); 3971 unsigned int CPUArchVer; 3972 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3973 llvm_unreachable("Invalid char for architecture version number"); 3974 } 3975 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3976 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3977 StringRef CPUProfile = getCPUProfile(CPU); 3978 if (!CPUProfile.empty()) 3979 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3980 3981 // Subtarget options. 3982 3983 // FIXME: It's more complicated than this and we don't really support 3984 // interworking. 3985 if (5 <= CPUArchVer && CPUArchVer <= 7) 3986 Builder.defineMacro("__THUMB_INTERWORK__"); 3987 3988 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3989 // Embedded targets on Darwin follow AAPCS, but not EABI. 3990 if (!getTriple().isOSDarwin()) 3991 Builder.defineMacro("__ARM_EABI__"); 3992 Builder.defineMacro("__ARM_PCS", "1"); 3993 3994 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3995 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3996 } 3997 3998 if (SoftFloat) 3999 Builder.defineMacro("__SOFTFP__"); 4000 4001 if (CPU == "xscale") 4002 Builder.defineMacro("__XSCALE__"); 4003 4004 if (IsThumb) { 4005 Builder.defineMacro("__THUMBEL__"); 4006 Builder.defineMacro("__thumb__"); 4007 if (CPUArch == "6T2" || CPUArchVer == 7) 4008 Builder.defineMacro("__thumb2__"); 4009 } 4010 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4011 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4012 4013 // Note, this is always on in gcc, even though it doesn't make sense. 4014 Builder.defineMacro("__APCS_32__"); 4015 4016 if (FPUModeIsVFP((FPUMode) FPU)) { 4017 Builder.defineMacro("__VFP_FP__"); 4018 if (FPU & VFP2FPU) 4019 Builder.defineMacro("__ARM_VFPV2__"); 4020 if (FPU & VFP3FPU) 4021 Builder.defineMacro("__ARM_VFPV3__"); 4022 if (FPU & VFP4FPU) 4023 Builder.defineMacro("__ARM_VFPV4__"); 4024 } 4025 4026 // This only gets set when Neon instructions are actually available, unlike 4027 // the VFP define, hence the soft float and arch check. This is subtly 4028 // different from gcc, we follow the intent which was that it should be set 4029 // when Neon instructions are actually available. 4030 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) 4031 Builder.defineMacro("__ARM_NEON__"); 4032 4033 if (CRC) 4034 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4035 4036 if (CPUArchVer >= 6 && CPUArch != "6M") { 4037 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4038 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4039 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4040 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4041 } 4042 } 4043 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4044 unsigned &NumRecords) const { 4045 Records = BuiltinInfo; 4046 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4047 } 4048 virtual bool isCLZForZeroUndef() const { return false; } 4049 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4050 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4051 } 4052 virtual void getGCCRegNames(const char * const *&Names, 4053 unsigned &NumNames) const; 4054 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4055 unsigned &NumAliases) const; 4056 virtual bool validateAsmConstraint(const char *&Name, 4057 TargetInfo::ConstraintInfo &Info) const { 4058 switch (*Name) { 4059 default: break; 4060 case 'l': // r0-r7 4061 case 'h': // r8-r15 4062 case 'w': // VFP Floating point register single precision 4063 case 'P': // VFP Floating point register double precision 4064 Info.setAllowsRegister(); 4065 return true; 4066 case 'Q': // A memory address that is a single base register. 4067 Info.setAllowsMemory(); 4068 return true; 4069 case 'U': // a memory reference... 4070 switch (Name[1]) { 4071 case 'q': // ...ARMV4 ldrsb 4072 case 'v': // ...VFP load/store (reg+constant offset) 4073 case 'y': // ...iWMMXt load/store 4074 case 't': // address valid for load/store opaque types wider 4075 // than 128-bits 4076 case 'n': // valid address for Neon doubleword vector load/store 4077 case 'm': // valid address for Neon element and structure load/store 4078 case 's': // valid address for non-offset loads/stores of quad-word 4079 // values in four ARM registers 4080 Info.setAllowsMemory(); 4081 Name++; 4082 return true; 4083 } 4084 } 4085 return false; 4086 } 4087 virtual std::string convertConstraint(const char *&Constraint) const { 4088 std::string R; 4089 switch (*Constraint) { 4090 case 'U': // Two-character constraint; add "^" hint for later parsing. 4091 R = std::string("^") + std::string(Constraint, 2); 4092 Constraint++; 4093 break; 4094 case 'p': // 'p' should be translated to 'r' by default. 4095 R = std::string("r"); 4096 break; 4097 default: 4098 return std::string(1, *Constraint); 4099 } 4100 return R; 4101 } 4102 virtual bool validateConstraintModifier(StringRef Constraint, 4103 const char Modifier, 4104 unsigned Size) const { 4105 bool isOutput = (Constraint[0] == '='); 4106 bool isInOut = (Constraint[0] == '+'); 4107 4108 // Strip off constraint modifiers. 4109 while (Constraint[0] == '=' || 4110 Constraint[0] == '+' || 4111 Constraint[0] == '&') 4112 Constraint = Constraint.substr(1); 4113 4114 switch (Constraint[0]) { 4115 default: break; 4116 case 'r': { 4117 switch (Modifier) { 4118 default: 4119 return (isInOut || isOutput || Size <= 64); 4120 case 'q': 4121 // A register of size 32 cannot fit a vector type. 4122 return false; 4123 } 4124 } 4125 } 4126 4127 return true; 4128 } 4129 virtual const char *getClobbers() const { 4130 // FIXME: Is this really right? 4131 return ""; 4132 } 4133 4134 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 4135 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4136 } 4137 4138 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4139 if (RegNo == 0) return 0; 4140 if (RegNo == 1) return 1; 4141 return -1; 4142 } 4143}; 4144 4145bool ARMTargetInfo::setFPMath(StringRef Name) { 4146 if (Name == "neon") { 4147 FPMath = FP_Neon; 4148 return true; 4149 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4150 Name == "vfp4") { 4151 FPMath = FP_VFP; 4152 return true; 4153 } 4154 return false; 4155} 4156 4157const char * const ARMTargetInfo::GCCRegNames[] = { 4158 // Integer registers 4159 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4160 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4161 4162 // Float registers 4163 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4164 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4165 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4166 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4167 4168 // Double registers 4169 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4170 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4171 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4172 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4173 4174 // Quad registers 4175 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4176 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4177}; 4178 4179void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4180 unsigned &NumNames) const { 4181 Names = GCCRegNames; 4182 NumNames = llvm::array_lengthof(GCCRegNames); 4183} 4184 4185const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4186 { { "a1" }, "r0" }, 4187 { { "a2" }, "r1" }, 4188 { { "a3" }, "r2" }, 4189 { { "a4" }, "r3" }, 4190 { { "v1" }, "r4" }, 4191 { { "v2" }, "r5" }, 4192 { { "v3" }, "r6" }, 4193 { { "v4" }, "r7" }, 4194 { { "v5" }, "r8" }, 4195 { { "v6", "rfp" }, "r9" }, 4196 { { "sl" }, "r10" }, 4197 { { "fp" }, "r11" }, 4198 { { "ip" }, "r12" }, 4199 { { "r13" }, "sp" }, 4200 { { "r14" }, "lr" }, 4201 { { "r15" }, "pc" }, 4202 // The S, D and Q registers overlap, but aren't really aliases; we 4203 // don't want to substitute one of these for a different-sized one. 4204}; 4205 4206void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4207 unsigned &NumAliases) const { 4208 Aliases = GCCRegAliases; 4209 NumAliases = llvm::array_lengthof(GCCRegAliases); 4210} 4211 4212const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4213#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4214#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4215 ALL_LANGUAGES }, 4216#include "clang/Basic/BuiltinsARM.def" 4217}; 4218} // end anonymous namespace. 4219 4220namespace { 4221class DarwinARMTargetInfo : 4222 public DarwinTargetInfo<ARMTargetInfo> { 4223protected: 4224 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4225 MacroBuilder &Builder) const { 4226 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4227 } 4228 4229public: 4230 DarwinARMTargetInfo(const llvm::Triple &Triple) 4231 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4232 HasAlignMac68kSupport = true; 4233 // iOS always has 64-bit atomic instructions. 4234 // FIXME: This should be based off of the target features in ARMTargetInfo. 4235 MaxAtomicInlineWidth = 64; 4236 4237 // Darwin on iOS uses a variant of the ARM C++ ABI. 4238 TheCXXABI.set(TargetCXXABI::iOS); 4239 } 4240}; 4241} // end anonymous namespace. 4242 4243 4244namespace { 4245// Hexagon abstract base class 4246class HexagonTargetInfo : public TargetInfo { 4247 static const Builtin::Info BuiltinInfo[]; 4248 static const char * const GCCRegNames[]; 4249 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4250 std::string CPU; 4251public: 4252 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4253 BigEndian = false; 4254 DescriptionString = ("e-p:32:32:32-" 4255 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 4256 "f64:64:64-f32:32:32-a0:0-n32"); 4257 4258 // {} in inline assembly are packet specifiers, not assembly variant 4259 // specifiers. 4260 NoAsmVariants = true; 4261 } 4262 4263 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4264 unsigned &NumRecords) const { 4265 Records = BuiltinInfo; 4266 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4267 } 4268 4269 virtual bool validateAsmConstraint(const char *&Name, 4270 TargetInfo::ConstraintInfo &Info) const { 4271 return true; 4272 } 4273 4274 virtual void getTargetDefines(const LangOptions &Opts, 4275 MacroBuilder &Builder) const; 4276 4277 virtual bool hasFeature(StringRef Feature) const { 4278 return Feature == "hexagon"; 4279 } 4280 4281 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4282 return TargetInfo::CharPtrBuiltinVaList; 4283 } 4284 virtual void getGCCRegNames(const char * const *&Names, 4285 unsigned &NumNames) const; 4286 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4287 unsigned &NumAliases) const; 4288 virtual const char *getClobbers() const { 4289 return ""; 4290 } 4291 4292 static const char *getHexagonCPUSuffix(StringRef Name) { 4293 return llvm::StringSwitch<const char*>(Name) 4294 .Case("hexagonv4", "4") 4295 .Case("hexagonv5", "5") 4296 .Default(0); 4297 } 4298 4299 virtual bool setCPU(const std::string &Name) { 4300 if (!getHexagonCPUSuffix(Name)) 4301 return false; 4302 4303 CPU = Name; 4304 return true; 4305 } 4306}; 4307 4308void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4309 MacroBuilder &Builder) const { 4310 Builder.defineMacro("qdsp6"); 4311 Builder.defineMacro("__qdsp6", "1"); 4312 Builder.defineMacro("__qdsp6__", "1"); 4313 4314 Builder.defineMacro("hexagon"); 4315 Builder.defineMacro("__hexagon", "1"); 4316 Builder.defineMacro("__hexagon__", "1"); 4317 4318 if(CPU == "hexagonv1") { 4319 Builder.defineMacro("__HEXAGON_V1__"); 4320 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4321 if(Opts.HexagonQdsp6Compat) { 4322 Builder.defineMacro("__QDSP6_V1__"); 4323 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4324 } 4325 } 4326 else if(CPU == "hexagonv2") { 4327 Builder.defineMacro("__HEXAGON_V2__"); 4328 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4329 if(Opts.HexagonQdsp6Compat) { 4330 Builder.defineMacro("__QDSP6_V2__"); 4331 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4332 } 4333 } 4334 else if(CPU == "hexagonv3") { 4335 Builder.defineMacro("__HEXAGON_V3__"); 4336 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4337 if(Opts.HexagonQdsp6Compat) { 4338 Builder.defineMacro("__QDSP6_V3__"); 4339 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4340 } 4341 } 4342 else if(CPU == "hexagonv4") { 4343 Builder.defineMacro("__HEXAGON_V4__"); 4344 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4345 if(Opts.HexagonQdsp6Compat) { 4346 Builder.defineMacro("__QDSP6_V4__"); 4347 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4348 } 4349 } 4350 else if(CPU == "hexagonv5") { 4351 Builder.defineMacro("__HEXAGON_V5__"); 4352 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4353 if(Opts.HexagonQdsp6Compat) { 4354 Builder.defineMacro("__QDSP6_V5__"); 4355 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4356 } 4357 } 4358} 4359 4360const char * const HexagonTargetInfo::GCCRegNames[] = { 4361 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4362 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4363 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4364 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4365 "p0", "p1", "p2", "p3", 4366 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4367}; 4368 4369void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4370 unsigned &NumNames) const { 4371 Names = GCCRegNames; 4372 NumNames = llvm::array_lengthof(GCCRegNames); 4373} 4374 4375 4376const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4377 { { "sp" }, "r29" }, 4378 { { "fp" }, "r30" }, 4379 { { "lr" }, "r31" }, 4380 }; 4381 4382void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4383 unsigned &NumAliases) const { 4384 Aliases = GCCRegAliases; 4385 NumAliases = llvm::array_lengthof(GCCRegAliases); 4386} 4387 4388 4389const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4390#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4391#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4392 ALL_LANGUAGES }, 4393#include "clang/Basic/BuiltinsHexagon.def" 4394}; 4395} 4396 4397 4398namespace { 4399// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4400class SparcTargetInfo : public TargetInfo { 4401 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4402 static const char * const GCCRegNames[]; 4403 bool SoftFloat; 4404public: 4405 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4406 4407 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4408 DiagnosticsEngine &Diags) { 4409 SoftFloat = false; 4410 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4411 if (Features[i] == "+soft-float") 4412 SoftFloat = true; 4413 return true; 4414 } 4415 virtual void getTargetDefines(const LangOptions &Opts, 4416 MacroBuilder &Builder) const { 4417 DefineStd(Builder, "sparc", Opts); 4418 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4419 4420 if (SoftFloat) 4421 Builder.defineMacro("SOFT_FLOAT", "1"); 4422 } 4423 4424 virtual bool hasFeature(StringRef Feature) const { 4425 return llvm::StringSwitch<bool>(Feature) 4426 .Case("softfloat", SoftFloat) 4427 .Case("sparc", true) 4428 .Default(false); 4429 } 4430 4431 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4432 unsigned &NumRecords) const { 4433 // FIXME: Implement! 4434 } 4435 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4436 return TargetInfo::VoidPtrBuiltinVaList; 4437 } 4438 virtual void getGCCRegNames(const char * const *&Names, 4439 unsigned &NumNames) const; 4440 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4441 unsigned &NumAliases) const; 4442 virtual bool validateAsmConstraint(const char *&Name, 4443 TargetInfo::ConstraintInfo &info) const { 4444 // FIXME: Implement! 4445 return false; 4446 } 4447 virtual const char *getClobbers() const { 4448 // FIXME: Implement! 4449 return ""; 4450 } 4451}; 4452 4453const char * const SparcTargetInfo::GCCRegNames[] = { 4454 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4455 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4456 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4457 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4458}; 4459 4460void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4461 unsigned &NumNames) const { 4462 Names = GCCRegNames; 4463 NumNames = llvm::array_lengthof(GCCRegNames); 4464} 4465 4466const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4467 { { "g0" }, "r0" }, 4468 { { "g1" }, "r1" }, 4469 { { "g2" }, "r2" }, 4470 { { "g3" }, "r3" }, 4471 { { "g4" }, "r4" }, 4472 { { "g5" }, "r5" }, 4473 { { "g6" }, "r6" }, 4474 { { "g7" }, "r7" }, 4475 { { "o0" }, "r8" }, 4476 { { "o1" }, "r9" }, 4477 { { "o2" }, "r10" }, 4478 { { "o3" }, "r11" }, 4479 { { "o4" }, "r12" }, 4480 { { "o5" }, "r13" }, 4481 { { "o6", "sp" }, "r14" }, 4482 { { "o7" }, "r15" }, 4483 { { "l0" }, "r16" }, 4484 { { "l1" }, "r17" }, 4485 { { "l2" }, "r18" }, 4486 { { "l3" }, "r19" }, 4487 { { "l4" }, "r20" }, 4488 { { "l5" }, "r21" }, 4489 { { "l6" }, "r22" }, 4490 { { "l7" }, "r23" }, 4491 { { "i0" }, "r24" }, 4492 { { "i1" }, "r25" }, 4493 { { "i2" }, "r26" }, 4494 { { "i3" }, "r27" }, 4495 { { "i4" }, "r28" }, 4496 { { "i5" }, "r29" }, 4497 { { "i6", "fp" }, "r30" }, 4498 { { "i7" }, "r31" }, 4499}; 4500 4501void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4502 unsigned &NumAliases) const { 4503 Aliases = GCCRegAliases; 4504 NumAliases = llvm::array_lengthof(GCCRegAliases); 4505} 4506 4507// SPARC v8 is the 32-bit mode selected by Triple::sparc. 4508class SparcV8TargetInfo : public SparcTargetInfo { 4509public: 4510 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4511 // FIXME: Support Sparc quad-precision long double? 4512 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4513 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4514 } 4515 4516 virtual void getTargetDefines(const LangOptions &Opts, 4517 MacroBuilder &Builder) const { 4518 SparcTargetInfo::getTargetDefines(Opts, Builder); 4519 Builder.defineMacro("__sparcv8"); 4520 } 4521}; 4522 4523// SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4524class SparcV9TargetInfo : public SparcTargetInfo { 4525public: 4526 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4527 // FIXME: Support Sparc quad-precision long double? 4528 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4529 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"; 4530 // This is an LP64 platform. 4531 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4532 4533 // OpenBSD uses long long for int64_t and intmax_t. 4534 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4535 IntMaxType = SignedLongLong; 4536 UIntMaxType = UnsignedLongLong; 4537 } else { 4538 IntMaxType = SignedLong; 4539 UIntMaxType = UnsignedLong; 4540 } 4541 Int64Type = IntMaxType; 4542 4543 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4544 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4545 LongDoubleWidth = 128; 4546 LongDoubleAlign = 128; 4547 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4548 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4549 } 4550 4551 virtual void getTargetDefines(const LangOptions &Opts, 4552 MacroBuilder &Builder) const { 4553 SparcTargetInfo::getTargetDefines(Opts, Builder); 4554 Builder.defineMacro("__sparcv9"); 4555 Builder.defineMacro("__arch64__"); 4556 // Solaris and its derivative AuroraUX don't need these variants, but the 4557 // BSDs do. 4558 if (getTriple().getOS() != llvm::Triple::Solaris && 4559 getTriple().getOS() != llvm::Triple::AuroraUX) { 4560 Builder.defineMacro("__sparc64__"); 4561 Builder.defineMacro("__sparc_v9__"); 4562 Builder.defineMacro("__sparcv9__"); 4563 } 4564 } 4565 4566 virtual bool setCPU(const std::string &Name) { 4567 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4568 .Case("v9", true) 4569 .Case("ultrasparc", true) 4570 .Case("ultrasparc3", true) 4571 .Case("niagara", true) 4572 .Case("niagara2", true) 4573 .Case("niagara3", true) 4574 .Case("niagara4", true) 4575 .Default(false); 4576 4577 // No need to store the CPU yet. There aren't any CPU-specific 4578 // macros to define. 4579 return CPUKnown; 4580 } 4581}; 4582 4583} // end anonymous namespace. 4584 4585namespace { 4586class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4587public: 4588 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4589 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4590 SizeType = UnsignedInt; 4591 PtrDiffType = SignedInt; 4592 } 4593}; 4594class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4595public: 4596 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4597 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4598 SizeType = UnsignedInt; 4599 PtrDiffType = SignedInt; 4600 } 4601}; 4602} // end anonymous namespace. 4603 4604namespace { 4605 class SystemZTargetInfo : public TargetInfo { 4606 static const char *const GCCRegNames[]; 4607 4608 public: 4609 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4610 TLSSupported = true; 4611 IntWidth = IntAlign = 32; 4612 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4613 PointerWidth = PointerAlign = 64; 4614 LongDoubleWidth = 128; 4615 LongDoubleAlign = 64; 4616 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4617 MinGlobalAlign = 16; 4618 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64" 4619 "-f32:32-f64:64-f128:64-a0:8:16-n32:64"; 4620 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4621 } 4622 virtual void getTargetDefines(const LangOptions &Opts, 4623 MacroBuilder &Builder) const { 4624 Builder.defineMacro("__s390__"); 4625 Builder.defineMacro("__s390x__"); 4626 Builder.defineMacro("__zarch__"); 4627 Builder.defineMacro("__LONG_DOUBLE_128__"); 4628 } 4629 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4630 unsigned &NumRecords) const { 4631 // FIXME: Implement. 4632 Records = 0; 4633 NumRecords = 0; 4634 } 4635 4636 virtual void getGCCRegNames(const char *const *&Names, 4637 unsigned &NumNames) const; 4638 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4639 unsigned &NumAliases) const { 4640 // No aliases. 4641 Aliases = 0; 4642 NumAliases = 0; 4643 } 4644 virtual bool validateAsmConstraint(const char *&Name, 4645 TargetInfo::ConstraintInfo &info) const; 4646 virtual const char *getClobbers() const { 4647 // FIXME: Is this really right? 4648 return ""; 4649 } 4650 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4651 return TargetInfo::SystemZBuiltinVaList; 4652 } 4653 virtual bool setCPU(const std::string &Name) { 4654 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4655 .Case("z10", true) 4656 .Case("z196", true) 4657 .Case("zEC12", true) 4658 .Default(false); 4659 4660 // No need to store the CPU yet. There aren't any CPU-specific 4661 // macros to define. 4662 return CPUKnown; 4663 } 4664 }; 4665 4666 const char *const SystemZTargetInfo::GCCRegNames[] = { 4667 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4668 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4669 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4670 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4671 }; 4672 4673 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4674 unsigned &NumNames) const { 4675 Names = GCCRegNames; 4676 NumNames = llvm::array_lengthof(GCCRegNames); 4677 } 4678 4679 bool SystemZTargetInfo:: 4680 validateAsmConstraint(const char *&Name, 4681 TargetInfo::ConstraintInfo &Info) const { 4682 switch (*Name) { 4683 default: 4684 return false; 4685 4686 case 'a': // Address register 4687 case 'd': // Data register (equivalent to 'r') 4688 case 'f': // Floating-point register 4689 Info.setAllowsRegister(); 4690 return true; 4691 4692 case 'I': // Unsigned 8-bit constant 4693 case 'J': // Unsigned 12-bit constant 4694 case 'K': // Signed 16-bit constant 4695 case 'L': // Signed 20-bit displacement (on all targets we support) 4696 case 'M': // 0x7fffffff 4697 return true; 4698 4699 case 'Q': // Memory with base and unsigned 12-bit displacement 4700 case 'R': // Likewise, plus an index 4701 case 'S': // Memory with base and signed 20-bit displacement 4702 case 'T': // Likewise, plus an index 4703 Info.setAllowsMemory(); 4704 return true; 4705 } 4706 } 4707} 4708 4709namespace { 4710 class MSP430TargetInfo : public TargetInfo { 4711 static const char * const GCCRegNames[]; 4712 public: 4713 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4714 BigEndian = false; 4715 TLSSupported = false; 4716 IntWidth = 16; IntAlign = 16; 4717 LongWidth = 32; LongLongWidth = 64; 4718 LongAlign = LongLongAlign = 16; 4719 PointerWidth = 16; PointerAlign = 16; 4720 SuitableAlign = 16; 4721 SizeType = UnsignedInt; 4722 IntMaxType = SignedLongLong; 4723 UIntMaxType = UnsignedLongLong; 4724 IntPtrType = SignedInt; 4725 PtrDiffType = SignedInt; 4726 SigAtomicType = SignedLong; 4727 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 4728 } 4729 virtual void getTargetDefines(const LangOptions &Opts, 4730 MacroBuilder &Builder) const { 4731 Builder.defineMacro("MSP430"); 4732 Builder.defineMacro("__MSP430__"); 4733 // FIXME: defines for different 'flavours' of MCU 4734 } 4735 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4736 unsigned &NumRecords) const { 4737 // FIXME: Implement. 4738 Records = 0; 4739 NumRecords = 0; 4740 } 4741 virtual bool hasFeature(StringRef Feature) const { 4742 return Feature == "msp430"; 4743 } 4744 virtual void getGCCRegNames(const char * const *&Names, 4745 unsigned &NumNames) const; 4746 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4747 unsigned &NumAliases) const { 4748 // No aliases. 4749 Aliases = 0; 4750 NumAliases = 0; 4751 } 4752 virtual bool validateAsmConstraint(const char *&Name, 4753 TargetInfo::ConstraintInfo &info) const { 4754 // No target constraints for now. 4755 return false; 4756 } 4757 virtual const char *getClobbers() const { 4758 // FIXME: Is this really right? 4759 return ""; 4760 } 4761 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4762 // FIXME: implement 4763 return TargetInfo::CharPtrBuiltinVaList; 4764 } 4765 }; 4766 4767 const char * const MSP430TargetInfo::GCCRegNames[] = { 4768 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4769 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4770 }; 4771 4772 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4773 unsigned &NumNames) const { 4774 Names = GCCRegNames; 4775 NumNames = llvm::array_lengthof(GCCRegNames); 4776 } 4777} 4778 4779namespace { 4780 4781 // LLVM and Clang cannot be used directly to output native binaries for 4782 // target, but is used to compile C code to llvm bitcode with correct 4783 // type and alignment information. 4784 // 4785 // TCE uses the llvm bitcode as input and uses it for generating customized 4786 // target processor and program binary. TCE co-design environment is 4787 // publicly available in http://tce.cs.tut.fi 4788 4789 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4790 3, // opencl_global 4791 4, // opencl_local 4792 5, // opencl_constant 4793 0, // cuda_device 4794 0, // cuda_constant 4795 0 // cuda_shared 4796 }; 4797 4798 class TCETargetInfo : public TargetInfo{ 4799 public: 4800 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4801 TLSSupported = false; 4802 IntWidth = 32; 4803 LongWidth = LongLongWidth = 32; 4804 PointerWidth = 32; 4805 IntAlign = 32; 4806 LongAlign = LongLongAlign = 32; 4807 PointerAlign = 32; 4808 SuitableAlign = 32; 4809 SizeType = UnsignedInt; 4810 IntMaxType = SignedLong; 4811 UIntMaxType = UnsignedLong; 4812 IntPtrType = SignedInt; 4813 PtrDiffType = SignedInt; 4814 FloatWidth = 32; 4815 FloatAlign = 32; 4816 DoubleWidth = 32; 4817 DoubleAlign = 32; 4818 LongDoubleWidth = 32; 4819 LongDoubleAlign = 32; 4820 FloatFormat = &llvm::APFloat::IEEEsingle; 4821 DoubleFormat = &llvm::APFloat::IEEEsingle; 4822 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4823 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 4824 "i16:16:32-i32:32:32-i64:32:32-" 4825 "f32:32:32-f64:32:32-v64:32:32-" 4826 "v128:32:32-a0:0:32-n32"; 4827 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4828 UseAddrSpaceMapMangling = true; 4829 } 4830 4831 virtual void getTargetDefines(const LangOptions &Opts, 4832 MacroBuilder &Builder) const { 4833 DefineStd(Builder, "tce", Opts); 4834 Builder.defineMacro("__TCE__"); 4835 Builder.defineMacro("__TCE_V1__"); 4836 } 4837 virtual bool hasFeature(StringRef Feature) const { 4838 return Feature == "tce"; 4839 } 4840 4841 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4842 unsigned &NumRecords) const {} 4843 virtual const char *getClobbers() const { 4844 return ""; 4845 } 4846 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4847 return TargetInfo::VoidPtrBuiltinVaList; 4848 } 4849 virtual void getGCCRegNames(const char * const *&Names, 4850 unsigned &NumNames) const {} 4851 virtual bool validateAsmConstraint(const char *&Name, 4852 TargetInfo::ConstraintInfo &info) const { 4853 return true; 4854 } 4855 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4856 unsigned &NumAliases) const {} 4857 }; 4858} 4859 4860namespace { 4861class MipsTargetInfoBase : public TargetInfo { 4862 virtual void setDescriptionString() = 0; 4863 4864 static const Builtin::Info BuiltinInfo[]; 4865 std::string CPU; 4866 bool IsMips16; 4867 bool IsMicromips; 4868 bool IsNan2008; 4869 bool IsSingleFloat; 4870 enum MipsFloatABI { 4871 HardFloat, SoftFloat 4872 } FloatABI; 4873 enum DspRevEnum { 4874 NoDSP, DSP1, DSP2 4875 } DspRev; 4876 bool HasMSA; 4877 4878protected: 4879 bool HasFP64; 4880 std::string ABI; 4881 4882public: 4883 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4884 const std::string &CPUStr) 4885 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4886 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4887 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4888 4889 virtual const char *getABI() const { return ABI.c_str(); } 4890 virtual bool setABI(const std::string &Name) = 0; 4891 virtual bool setCPU(const std::string &Name) { 4892 CPU = Name; 4893 return true; 4894 } 4895 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4896 Features[ABI] = true; 4897 Features[CPU] = true; 4898 } 4899 4900 virtual void getTargetDefines(const LangOptions &Opts, 4901 MacroBuilder &Builder) const { 4902 DefineStd(Builder, "mips", Opts); 4903 Builder.defineMacro("_mips"); 4904 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4905 4906 switch (FloatABI) { 4907 case HardFloat: 4908 Builder.defineMacro("__mips_hard_float", Twine(1)); 4909 break; 4910 case SoftFloat: 4911 Builder.defineMacro("__mips_soft_float", Twine(1)); 4912 break; 4913 } 4914 4915 if (IsSingleFloat) 4916 Builder.defineMacro("__mips_single_float", Twine(1)); 4917 4918 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 4919 Builder.defineMacro("_MIPS_FPSET", 4920 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 4921 4922 if (IsMips16) 4923 Builder.defineMacro("__mips16", Twine(1)); 4924 4925 if (IsMicromips) 4926 Builder.defineMacro("__mips_micromips", Twine(1)); 4927 4928 if (IsNan2008) 4929 Builder.defineMacro("__mips_nan2008", Twine(1)); 4930 4931 switch (DspRev) { 4932 default: 4933 break; 4934 case DSP1: 4935 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4936 Builder.defineMacro("__mips_dsp", Twine(1)); 4937 break; 4938 case DSP2: 4939 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4940 Builder.defineMacro("__mips_dspr2", Twine(1)); 4941 Builder.defineMacro("__mips_dsp", Twine(1)); 4942 break; 4943 } 4944 4945 if (HasMSA) 4946 Builder.defineMacro("__mips_msa", Twine(1)); 4947 4948 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4949 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4950 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4951 4952 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4953 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4954 } 4955 4956 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4957 unsigned &NumRecords) const { 4958 Records = BuiltinInfo; 4959 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4960 } 4961 virtual bool hasFeature(StringRef Feature) const { 4962 return llvm::StringSwitch<bool>(Feature) 4963 .Case("mips", true) 4964 .Case("fp64", HasFP64) 4965 .Default(false); 4966 } 4967 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4968 return TargetInfo::VoidPtrBuiltinVaList; 4969 } 4970 virtual void getGCCRegNames(const char * const *&Names, 4971 unsigned &NumNames) const { 4972 static const char *const GCCRegNames[] = { 4973 // CPU register names 4974 // Must match second column of GCCRegAliases 4975 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4976 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4977 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4978 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4979 // Floating point register names 4980 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4981 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4982 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4983 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4984 // Hi/lo and condition register names 4985 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4986 "$fcc5","$fcc6","$fcc7", 4987 // MSA register names 4988 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 4989 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 4990 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 4991 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 4992 // MSA control register names 4993 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 4994 "$msarequest", "$msamap", "$msaunmap" 4995 }; 4996 Names = GCCRegNames; 4997 NumNames = llvm::array_lengthof(GCCRegNames); 4998 } 4999 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5000 unsigned &NumAliases) const = 0; 5001 virtual bool validateAsmConstraint(const char *&Name, 5002 TargetInfo::ConstraintInfo &Info) const { 5003 switch (*Name) { 5004 default: 5005 return false; 5006 5007 case 'r': // CPU registers. 5008 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5009 case 'y': // Equivalent to "r", backwards compatibility only. 5010 case 'f': // floating-point registers. 5011 case 'c': // $25 for indirect jumps 5012 case 'l': // lo register 5013 case 'x': // hilo register pair 5014 Info.setAllowsRegister(); 5015 return true; 5016 case 'R': // An address that can be used in a non-macro load or store 5017 Info.setAllowsMemory(); 5018 return true; 5019 } 5020 } 5021 5022 virtual const char *getClobbers() const { 5023 // FIXME: Implement! 5024 return ""; 5025 } 5026 5027 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 5028 DiagnosticsEngine &Diags) { 5029 IsMips16 = false; 5030 IsMicromips = false; 5031 IsNan2008 = false; 5032 IsSingleFloat = false; 5033 FloatABI = HardFloat; 5034 DspRev = NoDSP; 5035 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5036 5037 for (std::vector<std::string>::iterator it = Features.begin(), 5038 ie = Features.end(); it != ie; ++it) { 5039 if (*it == "+single-float") 5040 IsSingleFloat = true; 5041 else if (*it == "+soft-float") 5042 FloatABI = SoftFloat; 5043 else if (*it == "+mips16") 5044 IsMips16 = true; 5045 else if (*it == "+micromips") 5046 IsMicromips = true; 5047 else if (*it == "+dsp") 5048 DspRev = std::max(DspRev, DSP1); 5049 else if (*it == "+dspr2") 5050 DspRev = std::max(DspRev, DSP2); 5051 else if (*it == "+msa") 5052 HasMSA = true; 5053 else if (*it == "+fp64") 5054 HasFP64 = true; 5055 else if (*it == "-fp64") 5056 HasFP64 = false; 5057 else if (*it == "+nan2008") 5058 IsNan2008 = true; 5059 } 5060 5061 // Remove front-end specific options. 5062 std::vector<std::string>::iterator it = 5063 std::find(Features.begin(), Features.end(), "+soft-float"); 5064 if (it != Features.end()) 5065 Features.erase(it); 5066 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5067 if (it != Features.end()) 5068 Features.erase(it); 5069 5070 setDescriptionString(); 5071 5072 return true; 5073 } 5074 5075 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5076 if (RegNo == 0) return 4; 5077 if (RegNo == 1) return 5; 5078 return -1; 5079 } 5080}; 5081 5082const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5083#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5084#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5085 ALL_LANGUAGES }, 5086#include "clang/Basic/BuiltinsMips.def" 5087}; 5088 5089class Mips32TargetInfoBase : public MipsTargetInfoBase { 5090public: 5091 Mips32TargetInfoBase(const llvm::Triple &Triple) 5092 : MipsTargetInfoBase(Triple, "o32", "mips32") { 5093 SizeType = UnsignedInt; 5094 PtrDiffType = SignedInt; 5095 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5096 } 5097 virtual bool setABI(const std::string &Name) { 5098 if ((Name == "o32") || (Name == "eabi")) { 5099 ABI = Name; 5100 return true; 5101 } else if (Name == "32") { 5102 ABI = "o32"; 5103 return true; 5104 } else 5105 return false; 5106 } 5107 virtual void getTargetDefines(const LangOptions &Opts, 5108 MacroBuilder &Builder) const { 5109 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5110 5111 if (ABI == "o32") { 5112 Builder.defineMacro("__mips_o32"); 5113 Builder.defineMacro("_ABIO32", "1"); 5114 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5115 } 5116 else if (ABI == "eabi") 5117 Builder.defineMacro("__mips_eabi"); 5118 else 5119 llvm_unreachable("Invalid ABI for Mips32."); 5120 } 5121 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5122 unsigned &NumAliases) const { 5123 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5124 { { "at" }, "$1" }, 5125 { { "v0" }, "$2" }, 5126 { { "v1" }, "$3" }, 5127 { { "a0" }, "$4" }, 5128 { { "a1" }, "$5" }, 5129 { { "a2" }, "$6" }, 5130 { { "a3" }, "$7" }, 5131 { { "t0" }, "$8" }, 5132 { { "t1" }, "$9" }, 5133 { { "t2" }, "$10" }, 5134 { { "t3" }, "$11" }, 5135 { { "t4" }, "$12" }, 5136 { { "t5" }, "$13" }, 5137 { { "t6" }, "$14" }, 5138 { { "t7" }, "$15" }, 5139 { { "s0" }, "$16" }, 5140 { { "s1" }, "$17" }, 5141 { { "s2" }, "$18" }, 5142 { { "s3" }, "$19" }, 5143 { { "s4" }, "$20" }, 5144 { { "s5" }, "$21" }, 5145 { { "s6" }, "$22" }, 5146 { { "s7" }, "$23" }, 5147 { { "t8" }, "$24" }, 5148 { { "t9" }, "$25" }, 5149 { { "k0" }, "$26" }, 5150 { { "k1" }, "$27" }, 5151 { { "gp" }, "$28" }, 5152 { { "sp","$sp" }, "$29" }, 5153 { { "fp","$fp" }, "$30" }, 5154 { { "ra" }, "$31" } 5155 }; 5156 Aliases = GCCRegAliases; 5157 NumAliases = llvm::array_lengthof(GCCRegAliases); 5158 } 5159}; 5160 5161class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5162 virtual void setDescriptionString() { 5163 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5164 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 5165 } 5166 5167public: 5168 Mips32EBTargetInfo(const llvm::Triple &Triple) 5169 : Mips32TargetInfoBase(Triple) { 5170 } 5171 virtual void getTargetDefines(const LangOptions &Opts, 5172 MacroBuilder &Builder) const { 5173 DefineStd(Builder, "MIPSEB", Opts); 5174 Builder.defineMacro("_MIPSEB"); 5175 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5176 } 5177}; 5178 5179class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5180 virtual void setDescriptionString() { 5181 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5182 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 5183 } 5184 5185public: 5186 Mips32ELTargetInfo(const llvm::Triple &Triple) 5187 : Mips32TargetInfoBase(Triple) { 5188 BigEndian = false; 5189 } 5190 virtual void getTargetDefines(const LangOptions &Opts, 5191 MacroBuilder &Builder) const { 5192 DefineStd(Builder, "MIPSEL", Opts); 5193 Builder.defineMacro("_MIPSEL"); 5194 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5195 } 5196}; 5197 5198class Mips64TargetInfoBase : public MipsTargetInfoBase { 5199public: 5200 Mips64TargetInfoBase(const llvm::Triple &Triple) 5201 : MipsTargetInfoBase(Triple, "n64", "mips64") { 5202 LongWidth = LongAlign = 64; 5203 PointerWidth = PointerAlign = 64; 5204 LongDoubleWidth = LongDoubleAlign = 128; 5205 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5206 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5207 LongDoubleWidth = LongDoubleAlign = 64; 5208 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5209 } 5210 SuitableAlign = 128; 5211 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5212 } 5213 virtual bool setABI(const std::string &Name) { 5214 if (Name == "n32") { 5215 LongWidth = LongAlign = 32; 5216 PointerWidth = PointerAlign = 32; 5217 ABI = Name; 5218 return true; 5219 } else if (Name == "n64") { 5220 ABI = Name; 5221 return true; 5222 } else if (Name == "64") { 5223 ABI = "n64"; 5224 return true; 5225 } else 5226 return false; 5227 } 5228 virtual void getTargetDefines(const LangOptions &Opts, 5229 MacroBuilder &Builder) const { 5230 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5231 5232 Builder.defineMacro("__mips64"); 5233 Builder.defineMacro("__mips64__"); 5234 5235 if (ABI == "n32") { 5236 Builder.defineMacro("__mips_n32"); 5237 Builder.defineMacro("_ABIN32", "2"); 5238 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5239 } 5240 else if (ABI == "n64") { 5241 Builder.defineMacro("__mips_n64"); 5242 Builder.defineMacro("_ABI64", "3"); 5243 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5244 } 5245 else 5246 llvm_unreachable("Invalid ABI for Mips64."); 5247 } 5248 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5249 unsigned &NumAliases) const { 5250 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5251 { { "at" }, "$1" }, 5252 { { "v0" }, "$2" }, 5253 { { "v1" }, "$3" }, 5254 { { "a0" }, "$4" }, 5255 { { "a1" }, "$5" }, 5256 { { "a2" }, "$6" }, 5257 { { "a3" }, "$7" }, 5258 { { "a4" }, "$8" }, 5259 { { "a5" }, "$9" }, 5260 { { "a6" }, "$10" }, 5261 { { "a7" }, "$11" }, 5262 { { "t0" }, "$12" }, 5263 { { "t1" }, "$13" }, 5264 { { "t2" }, "$14" }, 5265 { { "t3" }, "$15" }, 5266 { { "s0" }, "$16" }, 5267 { { "s1" }, "$17" }, 5268 { { "s2" }, "$18" }, 5269 { { "s3" }, "$19" }, 5270 { { "s4" }, "$20" }, 5271 { { "s5" }, "$21" }, 5272 { { "s6" }, "$22" }, 5273 { { "s7" }, "$23" }, 5274 { { "t8" }, "$24" }, 5275 { { "t9" }, "$25" }, 5276 { { "k0" }, "$26" }, 5277 { { "k1" }, "$27" }, 5278 { { "gp" }, "$28" }, 5279 { { "sp","$sp" }, "$29" }, 5280 { { "fp","$fp" }, "$30" }, 5281 { { "ra" }, "$31" } 5282 }; 5283 Aliases = GCCRegAliases; 5284 NumAliases = llvm::array_lengthof(GCCRegAliases); 5285 } 5286}; 5287 5288class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5289 virtual void setDescriptionString() { 5290 if (ABI == "n32") 5291 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5292 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5293 "v64:64:64-n32:64-S128"; 5294 else 5295 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5296 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5297 "v64:64:64-n32:64-S128"; 5298 5299 } 5300 5301public: 5302 Mips64EBTargetInfo(const llvm::Triple &Triple) 5303 : Mips64TargetInfoBase(Triple) {} 5304 virtual void getTargetDefines(const LangOptions &Opts, 5305 MacroBuilder &Builder) const { 5306 DefineStd(Builder, "MIPSEB", Opts); 5307 Builder.defineMacro("_MIPSEB"); 5308 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5309 } 5310}; 5311 5312class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5313 virtual void setDescriptionString() { 5314 if (ABI == "n32") 5315 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5316 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 5317 "-v64:64:64-n32:64-S128"; 5318 else 5319 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5320 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5321 "v64:64:64-n32:64-S128"; 5322 } 5323public: 5324 Mips64ELTargetInfo(const llvm::Triple &Triple) 5325 : Mips64TargetInfoBase(Triple) { 5326 // Default ABI is n64. 5327 BigEndian = false; 5328 } 5329 virtual void getTargetDefines(const LangOptions &Opts, 5330 MacroBuilder &Builder) const { 5331 DefineStd(Builder, "MIPSEL", Opts); 5332 Builder.defineMacro("_MIPSEL"); 5333 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5334 } 5335}; 5336} // end anonymous namespace. 5337 5338namespace { 5339class PNaClTargetInfo : public TargetInfo { 5340public: 5341 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5342 BigEndian = false; 5343 this->UserLabelPrefix = ""; 5344 this->LongAlign = 32; 5345 this->LongWidth = 32; 5346 this->PointerAlign = 32; 5347 this->PointerWidth = 32; 5348 this->IntMaxType = TargetInfo::SignedLongLong; 5349 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5350 this->Int64Type = TargetInfo::SignedLongLong; 5351 this->DoubleAlign = 64; 5352 this->LongDoubleWidth = 64; 5353 this->LongDoubleAlign = 64; 5354 this->SizeType = TargetInfo::UnsignedInt; 5355 this->PtrDiffType = TargetInfo::SignedInt; 5356 this->IntPtrType = TargetInfo::SignedInt; 5357 this->RegParmMax = 0; // Disallow regparm 5358 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5359 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 5360 } 5361 5362 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5363 } 5364 virtual void getArchDefines(const LangOptions &Opts, 5365 MacroBuilder &Builder) const { 5366 Builder.defineMacro("__le32__"); 5367 Builder.defineMacro("__pnacl__"); 5368 } 5369 virtual void getTargetDefines(const LangOptions &Opts, 5370 MacroBuilder &Builder) const { 5371 Builder.defineMacro("__LITTLE_ENDIAN__"); 5372 getArchDefines(Opts, Builder); 5373 } 5374 virtual bool hasFeature(StringRef Feature) const { 5375 return Feature == "pnacl"; 5376 } 5377 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5378 unsigned &NumRecords) const { 5379 } 5380 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5381 return TargetInfo::PNaClABIBuiltinVaList; 5382 } 5383 virtual void getGCCRegNames(const char * const *&Names, 5384 unsigned &NumNames) const; 5385 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5386 unsigned &NumAliases) const; 5387 virtual bool validateAsmConstraint(const char *&Name, 5388 TargetInfo::ConstraintInfo &Info) const { 5389 return false; 5390 } 5391 5392 virtual const char *getClobbers() const { 5393 return ""; 5394 } 5395}; 5396 5397void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5398 unsigned &NumNames) const { 5399 Names = NULL; 5400 NumNames = 0; 5401} 5402 5403void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5404 unsigned &NumAliases) const { 5405 Aliases = NULL; 5406 NumAliases = 0; 5407} 5408} // end anonymous namespace. 5409 5410namespace { 5411 static const unsigned SPIRAddrSpaceMap[] = { 5412 1, // opencl_global 5413 3, // opencl_local 5414 2, // opencl_constant 5415 0, // cuda_device 5416 0, // cuda_constant 5417 0 // cuda_shared 5418 }; 5419 class SPIRTargetInfo : public TargetInfo { 5420 public: 5421 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5422 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5423 "SPIR target must use unknown OS"); 5424 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5425 "SPIR target must use unknown environment type"); 5426 BigEndian = false; 5427 TLSSupported = false; 5428 LongWidth = LongAlign = 64; 5429 AddrSpaceMap = &SPIRAddrSpaceMap; 5430 UseAddrSpaceMapMangling = true; 5431 // Define available target features 5432 // These must be defined in sorted order! 5433 NoAsmVariants = true; 5434 } 5435 virtual void getTargetDefines(const LangOptions &Opts, 5436 MacroBuilder &Builder) const { 5437 DefineStd(Builder, "SPIR", Opts); 5438 } 5439 virtual bool hasFeature(StringRef Feature) const { 5440 return Feature == "spir"; 5441 } 5442 5443 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5444 unsigned &NumRecords) const {} 5445 virtual const char *getClobbers() const { 5446 return ""; 5447 } 5448 virtual void getGCCRegNames(const char * const *&Names, 5449 unsigned &NumNames) const {} 5450 virtual bool validateAsmConstraint(const char *&Name, 5451 TargetInfo::ConstraintInfo &info) const { 5452 return true; 5453 } 5454 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5455 unsigned &NumAliases) const {} 5456 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5457 return TargetInfo::VoidPtrBuiltinVaList; 5458 } 5459 }; 5460 5461 5462 class SPIR32TargetInfo : public SPIRTargetInfo { 5463 public: 5464 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5465 PointerWidth = PointerAlign = 32; 5466 SizeType = TargetInfo::UnsignedInt; 5467 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5468 DescriptionString 5469 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5470 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5471 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5472 "v512:512:512-v1024:1024:1024"; 5473 } 5474 virtual void getTargetDefines(const LangOptions &Opts, 5475 MacroBuilder &Builder) const { 5476 DefineStd(Builder, "SPIR32", Opts); 5477 } 5478 }; 5479 5480 class SPIR64TargetInfo : public SPIRTargetInfo { 5481 public: 5482 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5483 PointerWidth = PointerAlign = 64; 5484 SizeType = TargetInfo::UnsignedLong; 5485 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5486 DescriptionString 5487 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5488 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5489 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5490 "v512:512:512-v1024:1024:1024"; 5491 } 5492 virtual void getTargetDefines(const LangOptions &Opts, 5493 MacroBuilder &Builder) const { 5494 DefineStd(Builder, "SPIR64", Opts); 5495 } 5496 }; 5497} 5498 5499namespace { 5500class XCoreTargetInfo : public TargetInfo { 5501 static const Builtin::Info BuiltinInfo[]; 5502public: 5503 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5504 BigEndian = false; 5505 NoAsmVariants = true; 5506 LongLongAlign = 32; 5507 SuitableAlign = 32; 5508 DoubleAlign = LongDoubleAlign = 32; 5509 SizeType = UnsignedInt; 5510 PtrDiffType = SignedInt; 5511 IntPtrType = SignedInt; 5512 WCharType = UnsignedChar; 5513 WIntType = UnsignedInt; 5514 UseZeroLengthBitfieldAlignment = true; 5515 DescriptionString = "e-p:32:32:32-a0:0:32-n32" 5516 "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32" 5517 "-f16:16:32-f32:32:32-f64:32:32"; 5518 } 5519 virtual void getTargetDefines(const LangOptions &Opts, 5520 MacroBuilder &Builder) const { 5521 Builder.defineMacro("__XS1B__"); 5522 } 5523 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5524 unsigned &NumRecords) const { 5525 Records = BuiltinInfo; 5526 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5527 } 5528 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5529 return TargetInfo::VoidPtrBuiltinVaList; 5530 } 5531 virtual const char *getClobbers() const { 5532 return ""; 5533 } 5534 virtual void getGCCRegNames(const char * const *&Names, 5535 unsigned &NumNames) const { 5536 static const char * const GCCRegNames[] = { 5537 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5538 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5539 }; 5540 Names = GCCRegNames; 5541 NumNames = llvm::array_lengthof(GCCRegNames); 5542 } 5543 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5544 unsigned &NumAliases) const { 5545 Aliases = NULL; 5546 NumAliases = 0; 5547 } 5548 virtual bool validateAsmConstraint(const char *&Name, 5549 TargetInfo::ConstraintInfo &Info) const { 5550 return false; 5551 } 5552}; 5553 5554const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5555#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5556#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5557 ALL_LANGUAGES }, 5558#include "clang/Basic/BuiltinsXCore.def" 5559}; 5560} // end anonymous namespace. 5561 5562 5563//===----------------------------------------------------------------------===// 5564// Driver code 5565//===----------------------------------------------------------------------===// 5566 5567static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5568 llvm::Triple::OSType os = Triple.getOS(); 5569 5570 switch (Triple.getArch()) { 5571 default: 5572 return NULL; 5573 5574 case llvm::Triple::xcore: 5575 return new XCoreTargetInfo(Triple); 5576 5577 case llvm::Triple::hexagon: 5578 return new HexagonTargetInfo(Triple); 5579 5580 case llvm::Triple::aarch64: 5581 switch (os) { 5582 case llvm::Triple::Linux: 5583 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5584 default: 5585 return new AArch64TargetInfo(Triple); 5586 } 5587 5588 case llvm::Triple::arm: 5589 case llvm::Triple::thumb: 5590 if (Triple.isOSDarwin()) 5591 return new DarwinARMTargetInfo(Triple); 5592 5593 switch (os) { 5594 case llvm::Triple::Linux: 5595 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5596 case llvm::Triple::FreeBSD: 5597 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5598 case llvm::Triple::NetBSD: 5599 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5600 case llvm::Triple::OpenBSD: 5601 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5602 case llvm::Triple::Bitrig: 5603 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5604 case llvm::Triple::RTEMS: 5605 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5606 case llvm::Triple::NaCl: 5607 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5608 default: 5609 return new ARMTargetInfo(Triple); 5610 } 5611 5612 case llvm::Triple::msp430: 5613 return new MSP430TargetInfo(Triple); 5614 5615 case llvm::Triple::mips: 5616 switch (os) { 5617 case llvm::Triple::Linux: 5618 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5619 case llvm::Triple::RTEMS: 5620 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5621 case llvm::Triple::FreeBSD: 5622 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5623 case llvm::Triple::NetBSD: 5624 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5625 default: 5626 return new Mips32EBTargetInfo(Triple); 5627 } 5628 5629 case llvm::Triple::mipsel: 5630 switch (os) { 5631 case llvm::Triple::Linux: 5632 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5633 case llvm::Triple::RTEMS: 5634 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5635 case llvm::Triple::FreeBSD: 5636 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5637 case llvm::Triple::NetBSD: 5638 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5639 case llvm::Triple::NaCl: 5640 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5641 default: 5642 return new Mips32ELTargetInfo(Triple); 5643 } 5644 5645 case llvm::Triple::mips64: 5646 switch (os) { 5647 case llvm::Triple::Linux: 5648 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5649 case llvm::Triple::RTEMS: 5650 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5651 case llvm::Triple::FreeBSD: 5652 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5653 case llvm::Triple::NetBSD: 5654 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5655 case llvm::Triple::OpenBSD: 5656 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5657 default: 5658 return new Mips64EBTargetInfo(Triple); 5659 } 5660 5661 case llvm::Triple::mips64el: 5662 switch (os) { 5663 case llvm::Triple::Linux: 5664 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5665 case llvm::Triple::RTEMS: 5666 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5667 case llvm::Triple::FreeBSD: 5668 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5669 case llvm::Triple::NetBSD: 5670 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5671 case llvm::Triple::OpenBSD: 5672 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5673 default: 5674 return new Mips64ELTargetInfo(Triple); 5675 } 5676 5677 case llvm::Triple::le32: 5678 switch (os) { 5679 case llvm::Triple::NaCl: 5680 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5681 default: 5682 return NULL; 5683 } 5684 5685 case llvm::Triple::ppc: 5686 if (Triple.isOSDarwin()) 5687 return new DarwinPPC32TargetInfo(Triple); 5688 switch (os) { 5689 case llvm::Triple::Linux: 5690 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5691 case llvm::Triple::FreeBSD: 5692 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5693 case llvm::Triple::NetBSD: 5694 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5695 case llvm::Triple::OpenBSD: 5696 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5697 case llvm::Triple::RTEMS: 5698 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5699 default: 5700 return new PPC32TargetInfo(Triple); 5701 } 5702 5703 case llvm::Triple::ppc64: 5704 if (Triple.isOSDarwin()) 5705 return new DarwinPPC64TargetInfo(Triple); 5706 switch (os) { 5707 case llvm::Triple::Linux: 5708 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5709 case llvm::Triple::Lv2: 5710 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5711 case llvm::Triple::FreeBSD: 5712 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5713 case llvm::Triple::NetBSD: 5714 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5715 default: 5716 return new PPC64TargetInfo(Triple); 5717 } 5718 5719 case llvm::Triple::ppc64le: 5720 switch (os) { 5721 case llvm::Triple::Linux: 5722 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5723 default: 5724 return new PPC64TargetInfo(Triple); 5725 } 5726 5727 case llvm::Triple::nvptx: 5728 return new NVPTX32TargetInfo(Triple); 5729 case llvm::Triple::nvptx64: 5730 return new NVPTX64TargetInfo(Triple); 5731 5732 case llvm::Triple::r600: 5733 return new R600TargetInfo(Triple); 5734 5735 case llvm::Triple::sparc: 5736 switch (os) { 5737 case llvm::Triple::Linux: 5738 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5739 case llvm::Triple::AuroraUX: 5740 return new AuroraUXSparcV8TargetInfo(Triple); 5741 case llvm::Triple::Solaris: 5742 return new SolarisSparcV8TargetInfo(Triple); 5743 case llvm::Triple::NetBSD: 5744 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5745 case llvm::Triple::OpenBSD: 5746 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5747 case llvm::Triple::RTEMS: 5748 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5749 default: 5750 return new SparcV8TargetInfo(Triple); 5751 } 5752 5753 case llvm::Triple::sparcv9: 5754 switch (os) { 5755 case llvm::Triple::Linux: 5756 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5757 case llvm::Triple::AuroraUX: 5758 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5759 case llvm::Triple::Solaris: 5760 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5761 case llvm::Triple::NetBSD: 5762 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5763 case llvm::Triple::OpenBSD: 5764 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5765 case llvm::Triple::FreeBSD: 5766 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5767 default: 5768 return new SparcV9TargetInfo(Triple); 5769 } 5770 5771 case llvm::Triple::systemz: 5772 switch (os) { 5773 case llvm::Triple::Linux: 5774 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5775 default: 5776 return new SystemZTargetInfo(Triple); 5777 } 5778 5779 case llvm::Triple::tce: 5780 return new TCETargetInfo(Triple); 5781 5782 case llvm::Triple::x86: 5783 if (Triple.isOSDarwin()) 5784 return new DarwinI386TargetInfo(Triple); 5785 5786 switch (os) { 5787 case llvm::Triple::AuroraUX: 5788 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5789 case llvm::Triple::Linux: 5790 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5791 case llvm::Triple::DragonFly: 5792 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5793 case llvm::Triple::NetBSD: 5794 return new NetBSDI386TargetInfo(Triple); 5795 case llvm::Triple::OpenBSD: 5796 return new OpenBSDI386TargetInfo(Triple); 5797 case llvm::Triple::Bitrig: 5798 return new BitrigI386TargetInfo(Triple); 5799 case llvm::Triple::FreeBSD: 5800 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5801 case llvm::Triple::KFreeBSD: 5802 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5803 case llvm::Triple::Minix: 5804 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5805 case llvm::Triple::Solaris: 5806 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5807 case llvm::Triple::Cygwin: 5808 return new CygwinX86_32TargetInfo(Triple); 5809 case llvm::Triple::MinGW32: 5810 return new MinGWX86_32TargetInfo(Triple); 5811 case llvm::Triple::Win32: 5812 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5813 case llvm::Triple::Haiku: 5814 return new HaikuX86_32TargetInfo(Triple); 5815 case llvm::Triple::RTEMS: 5816 return new RTEMSX86_32TargetInfo(Triple); 5817 case llvm::Triple::NaCl: 5818 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5819 default: 5820 return new X86_32TargetInfo(Triple); 5821 } 5822 5823 case llvm::Triple::x86_64: 5824 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5825 return new DarwinX86_64TargetInfo(Triple); 5826 5827 switch (os) { 5828 case llvm::Triple::AuroraUX: 5829 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5830 case llvm::Triple::Linux: 5831 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5832 case llvm::Triple::DragonFly: 5833 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5834 case llvm::Triple::NetBSD: 5835 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5836 case llvm::Triple::OpenBSD: 5837 return new OpenBSDX86_64TargetInfo(Triple); 5838 case llvm::Triple::Bitrig: 5839 return new BitrigX86_64TargetInfo(Triple); 5840 case llvm::Triple::FreeBSD: 5841 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5842 case llvm::Triple::KFreeBSD: 5843 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5844 case llvm::Triple::Solaris: 5845 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5846 case llvm::Triple::MinGW32: 5847 return new MinGWX86_64TargetInfo(Triple); 5848 case llvm::Triple::Win32: // This is what Triple.h supports now. 5849 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5850 case llvm::Triple::NaCl: 5851 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5852 default: 5853 return new X86_64TargetInfo(Triple); 5854 } 5855 5856 case llvm::Triple::spir: { 5857 if (Triple.getOS() != llvm::Triple::UnknownOS || 5858 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5859 return NULL; 5860 return new SPIR32TargetInfo(Triple); 5861 } 5862 case llvm::Triple::spir64: { 5863 if (Triple.getOS() != llvm::Triple::UnknownOS || 5864 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5865 return NULL; 5866 return new SPIR64TargetInfo(Triple); 5867 } 5868 } 5869} 5870 5871/// CreateTargetInfo - Return the target info object for the specified target 5872/// triple. 5873TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5874 TargetOptions *Opts) { 5875 llvm::Triple Triple(Opts->Triple); 5876 5877 // Construct the target 5878 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5879 if (!Target) { 5880 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5881 return 0; 5882 } 5883 Target->setTargetOpts(Opts); 5884 5885 // Set the target CPU if specified. 5886 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5887 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5888 return 0; 5889 } 5890 5891 // Set the target ABI if specified. 5892 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5893 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5894 return 0; 5895 } 5896 5897 // Set the target C++ ABI. 5898 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 5899 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 5900 return 0; 5901 } 5902 5903 // Set the fp math unit. 5904 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5905 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5906 return 0; 5907 } 5908 5909 // Compute the default target features, we need the target to handle this 5910 // because features may have dependencies on one another. 5911 llvm::StringMap<bool> Features; 5912 Target->getDefaultFeatures(Features); 5913 5914 // Apply the user specified deltas. 5915 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5916 I < N; ++I) { 5917 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5918 // Apply the feature via the target. 5919 bool Enabled = Name[0] == '+'; 5920 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5921 } 5922 5923 // Add the features to the compile options. 5924 // 5925 // FIXME: If we are completely confident that we have the right set, we only 5926 // need to pass the minuses. 5927 Opts->Features.clear(); 5928 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5929 ie = Features.end(); it != ie; ++it) 5930 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5931 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 5932 return 0; 5933 5934 return Target.take(); 5935} 5936