1234285Sdim//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim// 10234285Sdim// This file contains the Hexagon implementation of the TargetRegisterInfo 11234285Sdim// class. 12234285Sdim// 13234285Sdim//===----------------------------------------------------------------------===// 14234285Sdim 15234285Sdim#ifndef HexagonREGISTERINFO_H 16234285Sdim#define HexagonREGISTERINFO_H 17234285Sdim 18252723Sdim#include "llvm/MC/MachineLocation.h" 19234285Sdim#include "llvm/Target/TargetRegisterInfo.h" 20234285Sdim 21234285Sdim#define GET_REGINFO_HEADER 22234285Sdim#include "HexagonGenRegisterInfo.inc" 23234285Sdim 24234285Sdim// 25234285Sdim// We try not to hard code the reserved registers in our code, 26234285Sdim// so the following two macros were defined. However, there 27234285Sdim// are still a few places that R11 and R10 are hard wired. 28234285Sdim// See below. If, in the future, we decided to change the reserved 29234285Sdim// register. Don't forget changing the following places. 30234285Sdim// 31234285Sdim// 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td 32234285Sdim// 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td 33234285Sdim// 3. the definition of "IntRegs" in HexagonRegisterInfo.td 34234285Sdim// 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td 35234285Sdim// 36234285Sdim#define HEXAGON_RESERVED_REG_1 Hexagon::R10 37234285Sdim#define HEXAGON_RESERVED_REG_2 Hexagon::R11 38234285Sdim 39234285Sdimnamespace llvm { 40234285Sdim 41234285Sdimclass HexagonSubtarget; 42234285Sdimclass HexagonInstrInfo; 43234285Sdimclass Type; 44234285Sdim 45234285Sdimstruct HexagonRegisterInfo : public HexagonGenRegisterInfo { 46234285Sdim HexagonSubtarget &Subtarget; 47234285Sdim 48263509Sdim HexagonRegisterInfo(HexagonSubtarget &st); 49234285Sdim 50234285Sdim /// Code Generation virtual methods... 51234285Sdim const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; 52234285Sdim 53234285Sdim const TargetRegisterClass* const* getCalleeSavedRegClasses( 54234285Sdim const MachineFunction *MF = 0) const; 55234285Sdim 56234285Sdim BitVector getReservedRegs(const MachineFunction &MF) const; 57234285Sdim 58234285Sdim void eliminateFrameIndex(MachineBasicBlock::iterator II, 59252723Sdim int SPAdj, unsigned FIOperandNum, 60252723Sdim RegScavenger *RS = NULL) const; 61234285Sdim 62234285Sdim /// determineFrameLayout - Determine the size of the frame and maximum call 63234285Sdim /// frame size. 64234285Sdim void determineFrameLayout(MachineFunction &MF) const; 65234285Sdim 66234285Sdim /// requiresRegisterScavenging - returns true since we may need scavenging for 67234285Sdim /// a temporary register when generating hardware loop instructions. 68234285Sdim bool requiresRegisterScavenging(const MachineFunction &MF) const { 69234285Sdim return true; 70234285Sdim } 71234285Sdim 72245431Sdim bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 73245431Sdim return true; 74245431Sdim } 75245431Sdim 76234285Sdim // Debug information queries. 77234285Sdim unsigned getRARegister() const; 78234285Sdim unsigned getFrameRegister(const MachineFunction &MF) const; 79234285Sdim unsigned getFrameRegister() const; 80234285Sdim unsigned getStackRegister() const; 81234285Sdim}; 82234285Sdim 83234285Sdim} // end namespace llvm 84234285Sdim 85234285Sdim#endif 86