1239310Sdim//===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===// 2239310Sdim// 3239310Sdim// The LLVM Compiler Infrastructure 4239310Sdim// 5239310Sdim// This file is distributed under the University of Illinois Open Source 6239310Sdim// License. See LICENSE.TXT for details. 7239310Sdim// 8239310Sdim//===----------------------------------------------------------------------===// 9239310Sdim// 10239310Sdim// This implements NewValueJump pass in Hexagon. 11239310Sdim// Ideally, we should merge this as a Peephole pass prior to register 12239310Sdim// allocation, but because we have a spill in between the feeder and new value 13239310Sdim// jump instructions, we are forced to write after register allocation. 14239310Sdim// Having said that, we should re-attempt to pull this earlier at some point 15239310Sdim// in future. 16239310Sdim 17239310Sdim// The basic approach looks for sequence of predicated jump, compare instruciton 18239310Sdim// that genereates the predicate and, the feeder to the predicate. Once it finds 19239310Sdim// all, it collapses compare and jump instruction into a new valu jump 20239310Sdim// intstructions. 21239310Sdim// 22239310Sdim// 23239310Sdim//===----------------------------------------------------------------------===// 24239310Sdim#define DEBUG_TYPE "hexagon-nvj" 25239310Sdim#include "llvm/PassSupport.h" 26239310Sdim#include "llvm/Support/Compiler.h" 27239310Sdim#include "llvm/Support/Debug.h" 28239310Sdim#include "llvm/ADT/DenseMap.h" 29239310Sdim#include "llvm/ADT/Statistic.h" 30239310Sdim#include "llvm/CodeGen/Passes.h" 31239310Sdim#include "llvm/CodeGen/ScheduleDAGInstrs.h" 32239310Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 33239310Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 34239310Sdim#include "llvm/CodeGen/LiveVariables.h" 35239310Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 36239310Sdim#include "llvm/CodeGen/MachineFunctionAnalysis.h" 37239310Sdim#include "llvm/Target/TargetMachine.h" 38239310Sdim#include "llvm/Target/TargetInstrInfo.h" 39239310Sdim#include "llvm/Target/TargetRegisterInfo.h" 40239310Sdim#include "Hexagon.h" 41239310Sdim#include "HexagonTargetMachine.h" 42239310Sdim#include "HexagonRegisterInfo.h" 43239310Sdim#include "HexagonSubtarget.h" 44239310Sdim#include "HexagonInstrInfo.h" 45239310Sdim#include "HexagonMachineFunctionInfo.h" 46239310Sdim 47239310Sdim#include <map> 48239310Sdim 49239310Sdim#include "llvm/Support/CommandLine.h" 50239310Sdimusing namespace llvm; 51239310Sdim 52239310SdimSTATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created"); 53239310Sdim 54239310Sdimstatic cl::opt<int> 55239310SdimDbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc( 56239310Sdim "Maximum number of predicated jumps to be converted to New Value Jump")); 57239310Sdim 58239310Sdimstatic cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden, 59239310Sdim cl::ZeroOrMore, cl::init(false), 60239310Sdim cl::desc("Disable New Value Jumps")); 61239310Sdim 62252723Sdimnamespace llvm { 63252723Sdim void initializeHexagonNewValueJumpPass(PassRegistry&); 64252723Sdim} 65252723Sdim 66252723Sdim 67239310Sdimnamespace { 68239310Sdim struct HexagonNewValueJump : public MachineFunctionPass { 69239310Sdim const HexagonInstrInfo *QII; 70239310Sdim const HexagonRegisterInfo *QRI; 71239310Sdim 72239310Sdim public: 73239310Sdim static char ID; 74239310Sdim 75252723Sdim HexagonNewValueJump() : MachineFunctionPass(ID) { 76252723Sdim initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry()); 77252723Sdim } 78239310Sdim 79239310Sdim virtual void getAnalysisUsage(AnalysisUsage &AU) const { 80252723Sdim AU.addRequired<MachineBranchProbabilityInfo>(); 81239310Sdim MachineFunctionPass::getAnalysisUsage(AU); 82239310Sdim } 83239310Sdim 84239310Sdim const char *getPassName() const { 85239310Sdim return "Hexagon NewValueJump"; 86239310Sdim } 87239310Sdim 88239310Sdim virtual bool runOnMachineFunction(MachineFunction &Fn); 89239310Sdim 90239310Sdim private: 91252723Sdim /// \brief A handle to the branch probability pass. 92252723Sdim const MachineBranchProbabilityInfo *MBPI; 93239310Sdim 94239310Sdim }; 95239310Sdim 96239310Sdim} // end of anonymous namespace 97239310Sdim 98239310Sdimchar HexagonNewValueJump::ID = 0; 99239310Sdim 100252723SdimINITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", 101252723Sdim "Hexagon NewValueJump", false, false) 102252723SdimINITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) 103252723SdimINITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", 104252723Sdim "Hexagon NewValueJump", false, false) 105252723Sdim 106252723Sdim 107239310Sdim// We have identified this II could be feeder to NVJ, 108239310Sdim// verify that it can be. 109239310Sdimstatic bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, 110239310Sdim const TargetRegisterInfo *TRI, 111239310Sdim MachineBasicBlock::iterator II, 112239310Sdim MachineBasicBlock::iterator end, 113239310Sdim MachineBasicBlock::iterator skip, 114239310Sdim MachineFunction &MF) { 115239310Sdim 116239310Sdim // Predicated instruction can not be feeder to NVJ. 117239310Sdim if (QII->isPredicated(II)) 118239310Sdim return false; 119239310Sdim 120239310Sdim // Bail out if feederReg is a paired register (double regs in 121239310Sdim // our case). One would think that we can check to see if a given 122239310Sdim // register cmpReg1 or cmpReg2 is a sub register of feederReg 123239310Sdim // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic 124239310Sdim // before the callsite of this function 125239310Sdim // But we can not as it comes in the following fashion. 126239310Sdim // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 127239310Sdim // %R0<def> = KILL %R0, %D0<imp-use,kill> 128239310Sdim // %P0<def> = CMPEQri %R0<kill>, 0 129239310Sdim // Hence, we need to check if it's a KILL instruction. 130239310Sdim if (II->getOpcode() == TargetOpcode::KILL) 131239310Sdim return false; 132239310Sdim 133239310Sdim 134239310Sdim // Make sure there there is no 'def' or 'use' of any of the uses of 135239310Sdim // feeder insn between it's definition, this MI and jump, jmpInst 136239310Sdim // skipping compare, cmpInst. 137239310Sdim // Here's the example. 138239310Sdim // r21=memub(r22+r24<<#0) 139239310Sdim // p0 = cmp.eq(r21, #0) 140239310Sdim // r4=memub(r3+r21<<#0) 141239310Sdim // if (p0.new) jump:t .LBB29_45 142239310Sdim // Without this check, it will be converted into 143239310Sdim // r4=memub(r3+r21<<#0) 144239310Sdim // r21=memub(r22+r24<<#0) 145239310Sdim // p0 = cmp.eq(r21, #0) 146239310Sdim // if (p0.new) jump:t .LBB29_45 147239310Sdim // and result WAR hazards if converted to New Value Jump. 148239310Sdim 149239310Sdim for (unsigned i = 0; i < II->getNumOperands(); ++i) { 150239310Sdim if (II->getOperand(i).isReg() && 151239310Sdim (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 152239310Sdim MachineBasicBlock::iterator localII = II; 153239310Sdim ++localII; 154239310Sdim unsigned Reg = II->getOperand(i).getReg(); 155239310Sdim for (MachineBasicBlock::iterator localBegin = localII; 156239310Sdim localBegin != end; ++localBegin) { 157239310Sdim if (localBegin == skip ) continue; 158239310Sdim // Check for Subregisters too. 159239310Sdim if (localBegin->modifiesRegister(Reg, TRI) || 160239310Sdim localBegin->readsRegister(Reg, TRI)) 161239310Sdim return false; 162239310Sdim } 163239310Sdim } 164239310Sdim } 165239310Sdim return true; 166239310Sdim} 167239310Sdim 168239310Sdim// These are the common checks that need to performed 169239310Sdim// to determine if 170239310Sdim// 1. compare instruction can be moved before jump. 171239310Sdim// 2. feeder to the compare instruction can be moved before jump. 172239310Sdimstatic bool commonChecksToProhibitNewValueJump(bool afterRA, 173239310Sdim MachineBasicBlock::iterator MII) { 174239310Sdim 175239310Sdim // If store in path, bail out. 176239310Sdim if (MII->getDesc().mayStore()) 177239310Sdim return false; 178239310Sdim 179239310Sdim // if call in path, bail out. 180239310Sdim if (MII->getOpcode() == Hexagon::CALLv3) 181239310Sdim return false; 182239310Sdim 183239310Sdim // if NVJ is running prior to RA, do the following checks. 184239310Sdim if (!afterRA) { 185239310Sdim // The following Target Opcode instructions are spurious 186239310Sdim // to new value jump. If they are in the path, bail out. 187239310Sdim // KILL sets kill flag on the opcode. It also sets up a 188239310Sdim // single register, out of pair. 189239310Sdim // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 190239310Sdim // %R0<def> = KILL %R0, %D0<imp-use,kill> 191239310Sdim // %P0<def> = CMPEQri %R0<kill>, 0 192239310Sdim // PHI can be anything after RA. 193239310Sdim // COPY can remateriaze things in between feeder, compare and nvj. 194239310Sdim if (MII->getOpcode() == TargetOpcode::KILL || 195239310Sdim MII->getOpcode() == TargetOpcode::PHI || 196239310Sdim MII->getOpcode() == TargetOpcode::COPY) 197239310Sdim return false; 198239310Sdim 199239310Sdim // The following pseudo Hexagon instructions sets "use" and "def" 200239310Sdim // of registers by individual passes in the backend. At this time, 201239310Sdim // we don't know the scope of usage and definitions of these 202239310Sdim // instructions. 203239310Sdim if (MII->getOpcode() == Hexagon::TFR_condset_rr || 204239310Sdim MII->getOpcode() == Hexagon::TFR_condset_ii || 205239310Sdim MII->getOpcode() == Hexagon::TFR_condset_ri || 206239310Sdim MII->getOpcode() == Hexagon::TFR_condset_ir || 207239310Sdim MII->getOpcode() == Hexagon::LDriw_pred || 208239310Sdim MII->getOpcode() == Hexagon::STriw_pred) 209239310Sdim return false; 210239310Sdim } 211239310Sdim 212239310Sdim return true; 213239310Sdim} 214239310Sdim 215239310Sdimstatic bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, 216239310Sdim const TargetRegisterInfo *TRI, 217239310Sdim MachineBasicBlock::iterator II, 218239310Sdim unsigned pReg, 219239310Sdim bool secondReg, 220239310Sdim bool optLocation, 221239310Sdim MachineBasicBlock::iterator end, 222239310Sdim MachineFunction &MF) { 223239310Sdim 224239310Sdim MachineInstr *MI = II; 225239310Sdim 226239310Sdim // If the second operand of the compare is an imm, make sure it's in the 227239310Sdim // range specified by the arch. 228239310Sdim if (!secondReg) { 229239310Sdim int64_t v = MI->getOperand(2).getImm(); 230239310Sdim 231239310Sdim if (!(isUInt<5>(v) || 232239310Sdim ((MI->getOpcode() == Hexagon::CMPEQri || 233252723Sdim MI->getOpcode() == Hexagon::CMPGTri) && 234239310Sdim (v == -1)))) 235239310Sdim return false; 236239310Sdim } 237239310Sdim 238239310Sdim unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning. 239239310Sdim cmpReg1 = MI->getOperand(1).getReg(); 240239310Sdim 241239310Sdim if (secondReg) { 242239310Sdim cmpOp2 = MI->getOperand(2).getReg(); 243239310Sdim 244239310Sdim // Make sure that that second register is not from COPY 245239310Sdim // At machine code level, we don't need this, but if we decide 246239310Sdim // to move new value jump prior to RA, we would be needing this. 247239310Sdim MachineRegisterInfo &MRI = MF.getRegInfo(); 248239310Sdim if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) { 249239310Sdim MachineInstr *def = MRI.getVRegDef(cmpOp2); 250239310Sdim if (def->getOpcode() == TargetOpcode::COPY) 251239310Sdim return false; 252239310Sdim } 253239310Sdim } 254239310Sdim 255239310Sdim // Walk the instructions after the compare (predicate def) to the jump, 256239310Sdim // and satisfy the following conditions. 257239310Sdim ++II ; 258239310Sdim for (MachineBasicBlock::iterator localII = II; localII != end; 259239310Sdim ++localII) { 260239310Sdim 261239310Sdim // Check 1. 262239310Sdim // If "common" checks fail, bail out. 263239310Sdim if (!commonChecksToProhibitNewValueJump(optLocation, localII)) 264239310Sdim return false; 265239310Sdim 266239310Sdim // Check 2. 267239310Sdim // If there is a def or use of predicate (result of compare), bail out. 268239310Sdim if (localII->modifiesRegister(pReg, TRI) || 269239310Sdim localII->readsRegister(pReg, TRI)) 270239310Sdim return false; 271239310Sdim 272239310Sdim // Check 3. 273239310Sdim // If there is a def of any of the use of the compare (operands of compare), 274239310Sdim // bail out. 275239310Sdim // Eg. 276239310Sdim // p0 = cmp.eq(r2, r0) 277239310Sdim // r2 = r4 278239310Sdim // if (p0.new) jump:t .LBB28_3 279239310Sdim if (localII->modifiesRegister(cmpReg1, TRI) || 280239310Sdim (secondReg && localII->modifiesRegister(cmpOp2, TRI))) 281239310Sdim return false; 282239310Sdim } 283239310Sdim return true; 284239310Sdim} 285239310Sdim 286239310Sdim// Given a compare operator, return a matching New Value Jump 287239310Sdim// compare operator. Make sure that MI here is included in 288239310Sdim// HexagonInstrInfo.cpp::isNewValueJumpCandidate 289252723Sdimstatic unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, 290252723Sdim bool secondRegNewified, 291252723Sdim MachineBasicBlock *jmpTarget, 292252723Sdim const MachineBranchProbabilityInfo 293252723Sdim *MBPI) { 294252723Sdim bool taken = false; 295252723Sdim MachineBasicBlock *Src = MI->getParent(); 296252723Sdim const BranchProbability Prediction = 297252723Sdim MBPI->getEdgeProbability(Src, jmpTarget); 298252723Sdim 299252723Sdim if (Prediction >= BranchProbability(1,2)) 300252723Sdim taken = true; 301252723Sdim 302239310Sdim switch (MI->getOpcode()) { 303239310Sdim case Hexagon::CMPEQrr: 304252723Sdim return taken ? Hexagon::CMPEQrr_t_Jumpnv_t_V4 305252723Sdim : Hexagon::CMPEQrr_t_Jumpnv_nt_V4; 306239310Sdim 307239310Sdim case Hexagon::CMPEQri: { 308239310Sdim if (reg >= 0) 309252723Sdim return taken ? Hexagon::CMPEQri_t_Jumpnv_t_V4 310252723Sdim : Hexagon::CMPEQri_t_Jumpnv_nt_V4; 311239310Sdim else 312252723Sdim return taken ? Hexagon::CMPEQn1_t_Jumpnv_t_V4 313252723Sdim : Hexagon::CMPEQn1_t_Jumpnv_nt_V4; 314239310Sdim } 315239310Sdim 316239310Sdim case Hexagon::CMPGTrr: { 317239310Sdim if (secondRegNewified) 318252723Sdim return taken ? Hexagon::CMPLTrr_t_Jumpnv_t_V4 319252723Sdim : Hexagon::CMPLTrr_t_Jumpnv_nt_V4; 320239310Sdim else 321252723Sdim return taken ? Hexagon::CMPGTrr_t_Jumpnv_t_V4 322252723Sdim : Hexagon::CMPGTrr_t_Jumpnv_nt_V4; 323239310Sdim } 324239310Sdim 325239310Sdim case Hexagon::CMPGTri: { 326239310Sdim if (reg >= 0) 327252723Sdim return taken ? Hexagon::CMPGTri_t_Jumpnv_t_V4 328252723Sdim : Hexagon::CMPGTri_t_Jumpnv_nt_V4; 329239310Sdim else 330252723Sdim return taken ? Hexagon::CMPGTn1_t_Jumpnv_t_V4 331252723Sdim : Hexagon::CMPGTn1_t_Jumpnv_nt_V4; 332239310Sdim } 333239310Sdim 334239310Sdim case Hexagon::CMPGTUrr: { 335239310Sdim if (secondRegNewified) 336252723Sdim return taken ? Hexagon::CMPLTUrr_t_Jumpnv_t_V4 337252723Sdim : Hexagon::CMPLTUrr_t_Jumpnv_nt_V4; 338239310Sdim else 339252723Sdim return taken ? Hexagon::CMPGTUrr_t_Jumpnv_t_V4 340252723Sdim : Hexagon::CMPGTUrr_t_Jumpnv_nt_V4; 341239310Sdim } 342239310Sdim 343239310Sdim case Hexagon::CMPGTUri: 344252723Sdim return taken ? Hexagon::CMPGTUri_t_Jumpnv_t_V4 345252723Sdim : Hexagon::CMPGTUri_t_Jumpnv_nt_V4; 346239310Sdim 347239310Sdim default: 348239310Sdim llvm_unreachable("Could not find matching New Value Jump instruction."); 349239310Sdim } 350239310Sdim // return *some value* to avoid compiler warning 351239310Sdim return 0; 352239310Sdim} 353239310Sdim 354239310Sdimbool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { 355239310Sdim 356239310Sdim DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" 357239310Sdim << "********** Function: " 358245431Sdim << MF.getName() << "\n"); 359239310Sdim 360239310Sdim#if 0 361239310Sdim // for now disable this, if we move NewValueJump before register 362239310Sdim // allocation we need this information. 363239310Sdim LiveVariables &LVs = getAnalysis<LiveVariables>(); 364239310Sdim#endif 365239310Sdim 366239310Sdim QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo()); 367239310Sdim QRI = 368239310Sdim static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo()); 369252723Sdim MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); 370239310Sdim 371239310Sdim if (!QRI->Subtarget.hasV4TOps() || 372239310Sdim DisableNewValueJumps) { 373239310Sdim return false; 374239310Sdim } 375239310Sdim 376239310Sdim int nvjCount = DbgNVJCount; 377239310Sdim int nvjGenerated = 0; 378239310Sdim 379239310Sdim // Loop through all the bb's of the function 380239310Sdim for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); 381239310Sdim MBBb != MBBe; ++MBBb) { 382239310Sdim MachineBasicBlock* MBB = MBBb; 383239310Sdim 384239310Sdim DEBUG(dbgs() << "** dumping bb ** " 385239310Sdim << MBB->getNumber() << "\n"); 386239310Sdim DEBUG(MBB->dump()); 387239310Sdim DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); 388239310Sdim bool foundJump = false; 389239310Sdim bool foundCompare = false; 390239310Sdim bool invertPredicate = false; 391239310Sdim unsigned predReg = 0; // predicate reg of the jump. 392239310Sdim unsigned cmpReg1 = 0; 393239310Sdim int cmpOp2 = 0; 394239310Sdim bool MO1IsKill = false; 395239310Sdim bool MO2IsKill = false; 396239310Sdim MachineBasicBlock::iterator jmpPos; 397239310Sdim MachineBasicBlock::iterator cmpPos; 398239310Sdim MachineInstr *cmpInstr = NULL, *jmpInstr = NULL; 399239310Sdim MachineBasicBlock *jmpTarget = NULL; 400239310Sdim bool afterRA = false; 401239310Sdim bool isSecondOpReg = false; 402239310Sdim bool isSecondOpNewified = false; 403239310Sdim // Traverse the basic block - bottom up 404239310Sdim for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); 405239310Sdim MII != E;) { 406239310Sdim MachineInstr *MI = --MII; 407239310Sdim if (MI->isDebugValue()) { 408239310Sdim continue; 409239310Sdim } 410239310Sdim 411239310Sdim if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) 412239310Sdim break; 413239310Sdim 414239310Sdim DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n"); 415239310Sdim 416239310Sdim if (!foundJump && 417252723Sdim (MI->getOpcode() == Hexagon::JMP_t || 418252723Sdim MI->getOpcode() == Hexagon::JMP_f || 419252723Sdim MI->getOpcode() == Hexagon::JMP_tnew_t || 420252723Sdim MI->getOpcode() == Hexagon::JMP_tnew_nt || 421252723Sdim MI->getOpcode() == Hexagon::JMP_fnew_t || 422252723Sdim MI->getOpcode() == Hexagon::JMP_fnew_nt)) { 423239310Sdim // This is where you would insert your compare and 424239310Sdim // instr that feeds compare 425239310Sdim jmpPos = MII; 426239310Sdim jmpInstr = MI; 427239310Sdim predReg = MI->getOperand(0).getReg(); 428239310Sdim afterRA = TargetRegisterInfo::isPhysicalRegister(predReg); 429239310Sdim 430239310Sdim // If ifconverter had not messed up with the kill flags of the 431239310Sdim // operands, the following check on the kill flag would suffice. 432239310Sdim // if(!jmpInstr->getOperand(0).isKill()) break; 433239310Sdim 434239310Sdim // This predicate register is live out out of BB 435239310Sdim // this would only work if we can actually use Live 436239310Sdim // variable analysis on phy regs - but LLVM does not 437239310Sdim // provide LV analysis on phys regs. 438239310Sdim //if(LVs.isLiveOut(predReg, *MBB)) break; 439239310Sdim 440239310Sdim // Get all the successors of this block - which will always 441239310Sdim // be 2. Check if the predicate register is live in in those 442239310Sdim // successor. If yes, we can not delete the predicate - 443239310Sdim // I am doing this only because LLVM does not provide LiveOut 444239310Sdim // at the BB level. 445239310Sdim bool predLive = false; 446239310Sdim for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), 447239310Sdim SIE = MBB->succ_end(); SI != SIE; ++SI) { 448239310Sdim MachineBasicBlock* succMBB = *SI; 449239310Sdim if (succMBB->isLiveIn(predReg)) { 450239310Sdim predLive = true; 451239310Sdim } 452239310Sdim } 453239310Sdim if (predLive) 454239310Sdim break; 455239310Sdim 456239310Sdim jmpTarget = MI->getOperand(1).getMBB(); 457239310Sdim foundJump = true; 458252723Sdim if (MI->getOpcode() == Hexagon::JMP_f || 459252723Sdim MI->getOpcode() == Hexagon::JMP_fnew_t || 460252723Sdim MI->getOpcode() == Hexagon::JMP_fnew_nt) { 461239310Sdim invertPredicate = true; 462239310Sdim } 463239310Sdim continue; 464239310Sdim } 465239310Sdim 466239310Sdim // No new value jump if there is a barrier. A barrier has to be in its 467239310Sdim // own packet. A barrier has zero operands. We conservatively bail out 468239310Sdim // here if we see any instruction with zero operands. 469239310Sdim if (foundJump && MI->getNumOperands() == 0) 470239310Sdim break; 471239310Sdim 472239310Sdim if (foundJump && 473239310Sdim !foundCompare && 474239310Sdim MI->getOperand(0).isReg() && 475239310Sdim MI->getOperand(0).getReg() == predReg) { 476239310Sdim 477239310Sdim // Not all compares can be new value compare. Arch Spec: 7.6.1.1 478239310Sdim if (QII->isNewValueJumpCandidate(MI)) { 479239310Sdim 480239310Sdim assert((MI->getDesc().isCompare()) && 481239310Sdim "Only compare instruction can be collapsed into New Value Jump"); 482239310Sdim isSecondOpReg = MI->getOperand(2).isReg(); 483239310Sdim 484239310Sdim if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, 485239310Sdim afterRA, jmpPos, MF)) 486239310Sdim break; 487239310Sdim 488239310Sdim cmpInstr = MI; 489239310Sdim cmpPos = MII; 490239310Sdim foundCompare = true; 491239310Sdim 492239310Sdim // We need cmpReg1 and cmpOp2(imm or reg) while building 493239310Sdim // new value jump instruction. 494239310Sdim cmpReg1 = MI->getOperand(1).getReg(); 495239310Sdim if (MI->getOperand(1).isKill()) 496239310Sdim MO1IsKill = true; 497239310Sdim 498239310Sdim if (isSecondOpReg) { 499239310Sdim cmpOp2 = MI->getOperand(2).getReg(); 500239310Sdim if (MI->getOperand(2).isKill()) 501239310Sdim MO2IsKill = true; 502239310Sdim } else 503239310Sdim cmpOp2 = MI->getOperand(2).getImm(); 504239310Sdim continue; 505239310Sdim } 506239310Sdim } 507239310Sdim 508239310Sdim if (foundCompare && foundJump) { 509239310Sdim 510239310Sdim // If "common" checks fail, bail out on this BB. 511239310Sdim if (!commonChecksToProhibitNewValueJump(afterRA, MII)) 512239310Sdim break; 513239310Sdim 514239310Sdim bool foundFeeder = false; 515239310Sdim MachineBasicBlock::iterator feederPos = MII; 516239310Sdim if (MI->getOperand(0).isReg() && 517239310Sdim MI->getOperand(0).isDef() && 518239310Sdim (MI->getOperand(0).getReg() == cmpReg1 || 519239310Sdim (isSecondOpReg && 520239310Sdim MI->getOperand(0).getReg() == (unsigned) cmpOp2))) { 521239310Sdim 522239310Sdim unsigned feederReg = MI->getOperand(0).getReg(); 523239310Sdim 524239310Sdim // First try to see if we can get the feeder from the first operand 525239310Sdim // of the compare. If we can not, and if secondOpReg is true 526239310Sdim // (second operand of the compare is also register), try that one. 527239310Sdim // TODO: Try to come up with some heuristic to figure out which 528239310Sdim // feeder would benefit. 529239310Sdim 530239310Sdim if (feederReg == cmpReg1) { 531239310Sdim if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { 532239310Sdim if (!isSecondOpReg) 533239310Sdim break; 534239310Sdim else 535239310Sdim continue; 536239310Sdim } else 537239310Sdim foundFeeder = true; 538239310Sdim } 539239310Sdim 540239310Sdim if (!foundFeeder && 541239310Sdim isSecondOpReg && 542239310Sdim feederReg == (unsigned) cmpOp2) 543239310Sdim if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) 544239310Sdim break; 545239310Sdim 546239310Sdim if (isSecondOpReg) { 547239310Sdim // In case of CMPLT, or CMPLTU, or EQ with the second register 548239310Sdim // to newify, swap the operands. 549252723Sdim if (cmpInstr->getOpcode() == Hexagon::CMPEQrr && 550252723Sdim feederReg == (unsigned) cmpOp2) { 551239310Sdim unsigned tmp = cmpReg1; 552239310Sdim bool tmpIsKill = MO1IsKill; 553239310Sdim cmpReg1 = cmpOp2; 554239310Sdim MO1IsKill = MO2IsKill; 555239310Sdim cmpOp2 = tmp; 556239310Sdim MO2IsKill = tmpIsKill; 557239310Sdim } 558239310Sdim 559239310Sdim // Now we have swapped the operands, all we need to check is, 560239310Sdim // if the second operand (after swap) is the feeder. 561239310Sdim // And if it is, make a note. 562239310Sdim if (feederReg == (unsigned)cmpOp2) 563239310Sdim isSecondOpNewified = true; 564239310Sdim } 565239310Sdim 566239310Sdim // Now that we are moving feeder close the jump, 567239310Sdim // make sure we are respecting the kill values of 568239310Sdim // the operands of the feeder. 569239310Sdim 570239310Sdim bool updatedIsKill = false; 571239310Sdim for (unsigned i = 0; i < MI->getNumOperands(); i++) { 572239310Sdim MachineOperand &MO = MI->getOperand(i); 573239310Sdim if (MO.isReg() && MO.isUse()) { 574239310Sdim unsigned feederReg = MO.getReg(); 575239310Sdim for (MachineBasicBlock::iterator localII = feederPos, 576239310Sdim end = jmpPos; localII != end; localII++) { 577239310Sdim MachineInstr *localMI = localII; 578239310Sdim for (unsigned j = 0; j < localMI->getNumOperands(); j++) { 579239310Sdim MachineOperand &localMO = localMI->getOperand(j); 580239310Sdim if (localMO.isReg() && localMO.isUse() && 581239310Sdim localMO.isKill() && feederReg == localMO.getReg()) { 582239310Sdim // We found that there is kill of a use register 583239310Sdim // Set up a kill flag on the register 584239310Sdim localMO.setIsKill(false); 585239310Sdim MO.setIsKill(); 586239310Sdim updatedIsKill = true; 587239310Sdim break; 588239310Sdim } 589239310Sdim } 590239310Sdim if (updatedIsKill) break; 591239310Sdim } 592239310Sdim } 593239310Sdim if (updatedIsKill) break; 594239310Sdim } 595239310Sdim 596239310Sdim MBB->splice(jmpPos, MI->getParent(), MI); 597239310Sdim MBB->splice(jmpPos, MI->getParent(), cmpInstr); 598239310Sdim DebugLoc dl = MI->getDebugLoc(); 599239310Sdim MachineInstr *NewMI; 600239310Sdim 601239310Sdim assert((QII->isNewValueJumpCandidate(cmpInstr)) && 602239310Sdim "This compare is not a New Value Jump candidate."); 603239310Sdim unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, 604252723Sdim isSecondOpNewified, 605252723Sdim jmpTarget, MBPI); 606239310Sdim if (invertPredicate) 607239310Sdim opc = QII->getInvertedPredicatedOpcode(opc); 608239310Sdim 609252723Sdim if (isSecondOpReg) 610239310Sdim NewMI = BuildMI(*MBB, jmpPos, dl, 611239310Sdim QII->get(opc)) 612239310Sdim .addReg(cmpReg1, getKillRegState(MO1IsKill)) 613239310Sdim .addReg(cmpOp2, getKillRegState(MO2IsKill)) 614239310Sdim .addMBB(jmpTarget); 615252723Sdim 616252723Sdim else if ((cmpInstr->getOpcode() == Hexagon::CMPEQri || 617252723Sdim cmpInstr->getOpcode() == Hexagon::CMPGTri) && 618252723Sdim cmpOp2 == -1 ) 619252723Sdim // Corresponding new-value compare jump instructions don't have the 620252723Sdim // operand for -1 immediate value. 621239310Sdim NewMI = BuildMI(*MBB, jmpPos, dl, 622239310Sdim QII->get(opc)) 623239310Sdim .addReg(cmpReg1, getKillRegState(MO1IsKill)) 624252723Sdim .addMBB(jmpTarget); 625252723Sdim 626252723Sdim else 627252723Sdim NewMI = BuildMI(*MBB, jmpPos, dl, 628252723Sdim QII->get(opc)) 629252723Sdim .addReg(cmpReg1, getKillRegState(MO1IsKill)) 630239310Sdim .addImm(cmpOp2) 631239310Sdim .addMBB(jmpTarget); 632239310Sdim 633239310Sdim assert(NewMI && "New Value Jump Instruction Not created!"); 634263509Sdim (void)NewMI; 635239310Sdim if (cmpInstr->getOperand(0).isReg() && 636239310Sdim cmpInstr->getOperand(0).isKill()) 637239310Sdim cmpInstr->getOperand(0).setIsKill(false); 638239310Sdim if (cmpInstr->getOperand(1).isReg() && 639239310Sdim cmpInstr->getOperand(1).isKill()) 640239310Sdim cmpInstr->getOperand(1).setIsKill(false); 641239310Sdim cmpInstr->eraseFromParent(); 642239310Sdim jmpInstr->eraseFromParent(); 643239310Sdim ++nvjGenerated; 644239310Sdim ++NumNVJGenerated; 645239310Sdim break; 646239310Sdim } 647239310Sdim } 648239310Sdim } 649239310Sdim } 650239310Sdim 651239310Sdim return true; 652239310Sdim 653239310Sdim} 654239310Sdim 655239310SdimFunctionPass *llvm::createHexagonNewValueJump() { 656239310Sdim return new HexagonNewValueJump(); 657239310Sdim} 658