1263509Sdim//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
2234285Sdim//
3234285Sdim//                     The LLVM Compiler Infrastructure
4234285Sdim//
5234285Sdim// This file is distributed under the University of Illinois Open Source
6234285Sdim// License. See LICENSE.TXT for details.
7234285Sdim//
8234285Sdim//===----------------------------------------------------------------------===//
9234285Sdim
10234285Sdim#ifndef HexagonMACHINEFUNCTIONINFO_H
11234285Sdim#define HexagonMACHINEFUNCTIONINFO_H
12234285Sdim
13263509Sdim#include <map>
14234285Sdim#include "llvm/CodeGen/MachineFunction.h"
15234285Sdim
16234285Sdimnamespace llvm {
17234285Sdim
18234285Sdim  namespace Hexagon {
19234285Sdim    const unsigned int StartPacket = 0x1;
20234285Sdim    const unsigned int EndPacket = 0x2;
21234285Sdim  }
22234285Sdim
23234285Sdim
24234285Sdim/// Hexagon target-specific information for each MachineFunction.
25234285Sdimclass HexagonMachineFunctionInfo : public MachineFunctionInfo {
26234285Sdim  // SRetReturnReg - Some subtargets require that sret lowering includes
27234285Sdim  // returning the value of the returned struct in a register. This field
28234285Sdim  // holds the virtual register into which the sret argument is passed.
29234285Sdim  unsigned SRetReturnReg;
30234285Sdim  std::vector<MachineInstr*> AllocaAdjustInsts;
31234285Sdim  int VarArgsFrameIndex;
32234285Sdim  bool HasClobberLR;
33252723Sdim  bool HasEHReturn;
34234285Sdim  std::map<const MachineInstr*, unsigned> PacketInfo;
35263509Sdim  virtual void anchor();
36234285Sdim
37234285Sdimpublic:
38252723Sdim  HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0),
39252723Sdim    HasEHReturn(false) {}
40234285Sdim
41234285Sdim  HexagonMachineFunctionInfo(MachineFunction &MF) : SRetReturnReg(0),
42252723Sdim                                                    HasClobberLR(0),
43252723Sdim                                                    HasEHReturn(false) {}
44234285Sdim
45234285Sdim  unsigned getSRetReturnReg() const { return SRetReturnReg; }
46234285Sdim  void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
47234285Sdim
48234285Sdim  void addAllocaAdjustInst(MachineInstr* MI) {
49234285Sdim    AllocaAdjustInsts.push_back(MI);
50234285Sdim  }
51234285Sdim  const std::vector<MachineInstr*>& getAllocaAdjustInsts() {
52234285Sdim    return AllocaAdjustInsts;
53234285Sdim  }
54234285Sdim
55234285Sdim  void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
56234285Sdim  int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
57234285Sdim
58234285Sdim  void setStartPacket(MachineInstr* MI) {
59234285Sdim    PacketInfo[MI] |= Hexagon::StartPacket;
60234285Sdim  }
61234285Sdim  void setEndPacket(MachineInstr* MI)   {
62234285Sdim    PacketInfo[MI] |= Hexagon::EndPacket;
63234285Sdim  }
64234285Sdim  bool isStartPacket(const MachineInstr* MI) const {
65234285Sdim    return (PacketInfo.count(MI) &&
66234285Sdim            (PacketInfo.find(MI)->second & Hexagon::StartPacket));
67234285Sdim  }
68234285Sdim  bool isEndPacket(const MachineInstr* MI) const {
69234285Sdim    return (PacketInfo.count(MI) &&
70234285Sdim            (PacketInfo.find(MI)->second & Hexagon::EndPacket));
71234285Sdim  }
72234285Sdim  void setHasClobberLR(bool v) { HasClobberLR = v;  }
73234285Sdim  bool hasClobberLR() const { return HasClobberLR; }
74234285Sdim
75252723Sdim  bool hasEHReturn() const { return HasEHReturn; };
76252723Sdim  void setHasEHReturn(bool H = true) { HasEHReturn = H; };
77234285Sdim};
78234285Sdim} // End llvm namespace
79234285Sdim
80234285Sdim#endif
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