1//===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements NewValueJump pass in Hexagon.
11// Ideally, we should merge this as a Peephole pass prior to register
12// allocation, but because we have a spill in between the feeder and new value
13// jump instructions, we are forced to write after register allocation.
14// Having said that, we should re-attempt to pull this earlier at some point
15// in future.
16
17// The basic approach looks for sequence of predicated jump, compare instruciton
18// that genereates the predicate and, the feeder to the predicate. Once it finds
19// all, it collapses compare and jump instruction into a new valu jump
20// intstructions.
21//
22//
23//===----------------------------------------------------------------------===//
24#define DEBUG_TYPE "hexagon-nvj"
25#include "llvm/PassSupport.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/Statistic.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/CodeGen/ScheduleDAGInstrs.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineFunctionPass.h"
34#include "llvm/CodeGen/LiveVariables.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/MachineFunctionAnalysis.h"
37#include "llvm/Target/TargetMachine.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetRegisterInfo.h"
40#include "Hexagon.h"
41#include "HexagonTargetMachine.h"
42#include "HexagonRegisterInfo.h"
43#include "HexagonSubtarget.h"
44#include "HexagonInstrInfo.h"
45#include "HexagonMachineFunctionInfo.h"
46
47#include <map>
48
49#include "llvm/Support/CommandLine.h"
50using namespace llvm;
51
52STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
53
54static cl::opt<int>
55DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
56  "Maximum number of predicated jumps to be converted to New Value Jump"));
57
58static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
59    cl::ZeroOrMore, cl::init(false),
60    cl::desc("Disable New Value Jumps"));
61
62namespace llvm {
63  void initializeHexagonNewValueJumpPass(PassRegistry&);
64}
65
66
67namespace {
68  struct HexagonNewValueJump : public MachineFunctionPass {
69    const HexagonInstrInfo    *QII;
70    const HexagonRegisterInfo *QRI;
71
72  public:
73    static char ID;
74
75    HexagonNewValueJump() : MachineFunctionPass(ID) {
76      initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
77    }
78
79    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
80      AU.addRequired<MachineBranchProbabilityInfo>();
81      MachineFunctionPass::getAnalysisUsage(AU);
82    }
83
84    const char *getPassName() const {
85      return "Hexagon NewValueJump";
86    }
87
88    virtual bool runOnMachineFunction(MachineFunction &Fn);
89
90  private:
91    /// \brief A handle to the branch probability pass.
92    const MachineBranchProbabilityInfo *MBPI;
93
94  };
95
96} // end of anonymous namespace
97
98char HexagonNewValueJump::ID = 0;
99
100INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
101                      "Hexagon NewValueJump", false, false)
102INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
103INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
104                    "Hexagon NewValueJump", false, false)
105
106
107// We have identified this II could be feeder to NVJ,
108// verify that it can be.
109static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
110                                      const TargetRegisterInfo *TRI,
111                                      MachineBasicBlock::iterator II,
112                                      MachineBasicBlock::iterator end,
113                                      MachineBasicBlock::iterator skip,
114                                      MachineFunction &MF) {
115
116  // Predicated instruction can not be feeder to NVJ.
117  if (QII->isPredicated(II))
118    return false;
119
120  // Bail out if feederReg is a paired register (double regs in
121  // our case). One would think that we can check to see if a given
122  // register cmpReg1 or cmpReg2 is a sub register of feederReg
123  // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
124  // before the callsite of this function
125  // But we can not as it comes in the following fashion.
126  //    %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
127  //    %R0<def> = KILL %R0, %D0<imp-use,kill>
128  //    %P0<def> = CMPEQri %R0<kill>, 0
129  // Hence, we need to check if it's a KILL instruction.
130  if (II->getOpcode() == TargetOpcode::KILL)
131    return false;
132
133
134  // Make sure there there is no 'def' or 'use' of any of the uses of
135  // feeder insn between it's definition, this MI and jump, jmpInst
136  // skipping compare, cmpInst.
137  // Here's the example.
138  //    r21=memub(r22+r24<<#0)
139  //    p0 = cmp.eq(r21, #0)
140  //    r4=memub(r3+r21<<#0)
141  //    if (p0.new) jump:t .LBB29_45
142  // Without this check, it will be converted into
143  //    r4=memub(r3+r21<<#0)
144  //    r21=memub(r22+r24<<#0)
145  //    p0 = cmp.eq(r21, #0)
146  //    if (p0.new) jump:t .LBB29_45
147  // and result WAR hazards if converted to New Value Jump.
148
149  for (unsigned i = 0; i < II->getNumOperands(); ++i) {
150    if (II->getOperand(i).isReg() &&
151        (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
152      MachineBasicBlock::iterator localII = II;
153      ++localII;
154      unsigned Reg = II->getOperand(i).getReg();
155      for (MachineBasicBlock::iterator localBegin = localII;
156                        localBegin != end; ++localBegin) {
157        if (localBegin == skip ) continue;
158        // Check for Subregisters too.
159        if (localBegin->modifiesRegister(Reg, TRI) ||
160            localBegin->readsRegister(Reg, TRI))
161          return false;
162      }
163    }
164  }
165  return true;
166}
167
168// These are the common checks that need to performed
169// to determine if
170// 1. compare instruction can be moved before jump.
171// 2. feeder to the compare instruction can be moved before jump.
172static bool commonChecksToProhibitNewValueJump(bool afterRA,
173                          MachineBasicBlock::iterator MII) {
174
175  // If store in path, bail out.
176  if (MII->getDesc().mayStore())
177    return false;
178
179  // if call in path, bail out.
180  if (MII->getOpcode() == Hexagon::CALLv3)
181    return false;
182
183  // if NVJ is running prior to RA, do the following checks.
184  if (!afterRA) {
185    // The following Target Opcode instructions are spurious
186    // to new value jump. If they are in the path, bail out.
187    // KILL sets kill flag on the opcode. It also sets up a
188    // single register, out of pair.
189    //    %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
190    //    %R0<def> = KILL %R0, %D0<imp-use,kill>
191    //    %P0<def> = CMPEQri %R0<kill>, 0
192    // PHI can be anything after RA.
193    // COPY can remateriaze things in between feeder, compare and nvj.
194    if (MII->getOpcode() == TargetOpcode::KILL ||
195        MII->getOpcode() == TargetOpcode::PHI  ||
196        MII->getOpcode() == TargetOpcode::COPY)
197      return false;
198
199    // The following pseudo Hexagon instructions sets "use" and "def"
200    // of registers by individual passes in the backend. At this time,
201    // we don't know the scope of usage and definitions of these
202    // instructions.
203    if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
204        MII->getOpcode() == Hexagon::TFR_condset_ii ||
205        MII->getOpcode() == Hexagon::TFR_condset_ri ||
206        MII->getOpcode() == Hexagon::TFR_condset_ir ||
207        MII->getOpcode() == Hexagon::LDriw_pred     ||
208        MII->getOpcode() == Hexagon::STriw_pred)
209      return false;
210  }
211
212  return true;
213}
214
215static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
216                                     const TargetRegisterInfo *TRI,
217                                     MachineBasicBlock::iterator II,
218                                     unsigned pReg,
219                                     bool secondReg,
220                                     bool optLocation,
221                                     MachineBasicBlock::iterator end,
222                                     MachineFunction &MF) {
223
224  MachineInstr *MI = II;
225
226  // If the second operand of the compare is an imm, make sure it's in the
227  // range specified by the arch.
228  if (!secondReg) {
229    int64_t v = MI->getOperand(2).getImm();
230
231    if (!(isUInt<5>(v) ||
232         ((MI->getOpcode() == Hexagon::CMPEQri ||
233           MI->getOpcode() == Hexagon::CMPGTri) &&
234          (v == -1))))
235      return false;
236  }
237
238  unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
239  cmpReg1 = MI->getOperand(1).getReg();
240
241  if (secondReg) {
242    cmpOp2 = MI->getOperand(2).getReg();
243
244    // Make sure that that second register is not from COPY
245    // At machine code level, we don't need this, but if we decide
246    // to move new value jump prior to RA, we would be needing this.
247    MachineRegisterInfo &MRI = MF.getRegInfo();
248    if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
249      MachineInstr *def = MRI.getVRegDef(cmpOp2);
250      if (def->getOpcode() == TargetOpcode::COPY)
251        return false;
252    }
253  }
254
255  // Walk the instructions after the compare (predicate def) to the jump,
256  // and satisfy the following conditions.
257  ++II ;
258  for (MachineBasicBlock::iterator localII = II; localII != end;
259       ++localII) {
260
261    // Check 1.
262    // If "common" checks fail, bail out.
263    if (!commonChecksToProhibitNewValueJump(optLocation, localII))
264      return false;
265
266    // Check 2.
267    // If there is a def or use of predicate (result of compare), bail out.
268    if (localII->modifiesRegister(pReg, TRI) ||
269        localII->readsRegister(pReg, TRI))
270      return false;
271
272    // Check 3.
273    // If there is a def of any of the use of the compare (operands of compare),
274    // bail out.
275    // Eg.
276    //    p0 = cmp.eq(r2, r0)
277    //    r2 = r4
278    //    if (p0.new) jump:t .LBB28_3
279    if (localII->modifiesRegister(cmpReg1, TRI) ||
280        (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
281      return false;
282  }
283  return true;
284}
285
286// Given a compare operator, return a matching New Value Jump
287// compare operator. Make sure that MI here is included in
288// HexagonInstrInfo.cpp::isNewValueJumpCandidate
289static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
290                                      bool secondRegNewified,
291                                      MachineBasicBlock *jmpTarget,
292                                      const MachineBranchProbabilityInfo
293                                      *MBPI) {
294  bool taken = false;
295  MachineBasicBlock *Src = MI->getParent();
296  const BranchProbability Prediction =
297    MBPI->getEdgeProbability(Src, jmpTarget);
298
299  if (Prediction >= BranchProbability(1,2))
300    taken = true;
301
302  switch (MI->getOpcode()) {
303    case Hexagon::CMPEQrr:
304      return taken ? Hexagon::CMPEQrr_t_Jumpnv_t_V4
305                   : Hexagon::CMPEQrr_t_Jumpnv_nt_V4;
306
307    case Hexagon::CMPEQri: {
308      if (reg >= 0)
309        return taken ? Hexagon::CMPEQri_t_Jumpnv_t_V4
310                     : Hexagon::CMPEQri_t_Jumpnv_nt_V4;
311      else
312        return taken ? Hexagon::CMPEQn1_t_Jumpnv_t_V4
313                     : Hexagon::CMPEQn1_t_Jumpnv_nt_V4;
314    }
315
316    case Hexagon::CMPGTrr: {
317      if (secondRegNewified)
318        return taken ? Hexagon::CMPLTrr_t_Jumpnv_t_V4
319                     : Hexagon::CMPLTrr_t_Jumpnv_nt_V4;
320      else
321        return taken ? Hexagon::CMPGTrr_t_Jumpnv_t_V4
322                     : Hexagon::CMPGTrr_t_Jumpnv_nt_V4;
323    }
324
325    case Hexagon::CMPGTri: {
326      if (reg >= 0)
327        return taken ? Hexagon::CMPGTri_t_Jumpnv_t_V4
328                     : Hexagon::CMPGTri_t_Jumpnv_nt_V4;
329      else
330        return taken ? Hexagon::CMPGTn1_t_Jumpnv_t_V4
331                     : Hexagon::CMPGTn1_t_Jumpnv_nt_V4;
332    }
333
334    case Hexagon::CMPGTUrr: {
335      if (secondRegNewified)
336        return taken ? Hexagon::CMPLTUrr_t_Jumpnv_t_V4
337                     : Hexagon::CMPLTUrr_t_Jumpnv_nt_V4;
338      else
339        return taken ? Hexagon::CMPGTUrr_t_Jumpnv_t_V4
340                     : Hexagon::CMPGTUrr_t_Jumpnv_nt_V4;
341    }
342
343    case Hexagon::CMPGTUri:
344      return taken ? Hexagon::CMPGTUri_t_Jumpnv_t_V4
345                   : Hexagon::CMPGTUri_t_Jumpnv_nt_V4;
346
347    default:
348       llvm_unreachable("Could not find matching New Value Jump instruction.");
349  }
350  // return *some value* to avoid compiler warning
351  return 0;
352}
353
354bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
355
356  DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
357               << "********** Function: "
358               << MF.getName() << "\n");
359
360#if 0
361  // for now disable this, if we move NewValueJump before register
362  // allocation we need this information.
363  LiveVariables &LVs = getAnalysis<LiveVariables>();
364#endif
365
366  QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
367  QRI =
368    static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
369  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
370
371  if (!QRI->Subtarget.hasV4TOps() ||
372      DisableNewValueJumps) {
373    return false;
374  }
375
376  int nvjCount = DbgNVJCount;
377  int nvjGenerated = 0;
378
379  // Loop through all the bb's of the function
380  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
381        MBBb != MBBe; ++MBBb) {
382    MachineBasicBlock* MBB = MBBb;
383
384    DEBUG(dbgs() << "** dumping bb ** "
385                 << MBB->getNumber() << "\n");
386    DEBUG(MBB->dump());
387    DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
388    bool foundJump    = false;
389    bool foundCompare = false;
390    bool invertPredicate = false;
391    unsigned predReg = 0; // predicate reg of the jump.
392    unsigned cmpReg1 = 0;
393    int cmpOp2 = 0;
394    bool MO1IsKill = false;
395    bool MO2IsKill = false;
396    MachineBasicBlock::iterator jmpPos;
397    MachineBasicBlock::iterator cmpPos;
398    MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
399    MachineBasicBlock *jmpTarget = NULL;
400    bool afterRA = false;
401    bool isSecondOpReg = false;
402    bool isSecondOpNewified = false;
403    // Traverse the basic block - bottom up
404    for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
405             MII != E;) {
406      MachineInstr *MI = --MII;
407      if (MI->isDebugValue()) {
408        continue;
409      }
410
411      if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
412        break;
413
414      DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
415
416      if (!foundJump &&
417         (MI->getOpcode() == Hexagon::JMP_t ||
418          MI->getOpcode() == Hexagon::JMP_f ||
419          MI->getOpcode() == Hexagon::JMP_tnew_t ||
420          MI->getOpcode() == Hexagon::JMP_tnew_nt ||
421          MI->getOpcode() == Hexagon::JMP_fnew_t ||
422          MI->getOpcode() == Hexagon::JMP_fnew_nt)) {
423        // This is where you would insert your compare and
424        // instr that feeds compare
425        jmpPos = MII;
426        jmpInstr = MI;
427        predReg = MI->getOperand(0).getReg();
428        afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
429
430        // If ifconverter had not messed up with the kill flags of the
431        // operands, the following check on the kill flag would suffice.
432        // if(!jmpInstr->getOperand(0).isKill()) break;
433
434        // This predicate register is live out out of BB
435        // this would only work if we can actually use Live
436        // variable analysis on phy regs - but LLVM does not
437        // provide LV analysis on phys regs.
438        //if(LVs.isLiveOut(predReg, *MBB)) break;
439
440        // Get all the successors of this block - which will always
441        // be 2. Check if the predicate register is live in in those
442        // successor. If yes, we can not delete the predicate -
443        // I am doing this only because LLVM does not provide LiveOut
444        // at the BB level.
445        bool predLive = false;
446        for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
447                            SIE = MBB->succ_end(); SI != SIE; ++SI) {
448          MachineBasicBlock* succMBB = *SI;
449         if (succMBB->isLiveIn(predReg)) {
450            predLive = true;
451          }
452        }
453        if (predLive)
454          break;
455
456        jmpTarget = MI->getOperand(1).getMBB();
457        foundJump = true;
458        if (MI->getOpcode() == Hexagon::JMP_f ||
459            MI->getOpcode() == Hexagon::JMP_fnew_t ||
460            MI->getOpcode() == Hexagon::JMP_fnew_nt) {
461          invertPredicate = true;
462        }
463        continue;
464      }
465
466      // No new value jump if there is a barrier. A barrier has to be in its
467      // own packet. A barrier has zero operands. We conservatively bail out
468      // here if we see any instruction with zero operands.
469      if (foundJump && MI->getNumOperands() == 0)
470        break;
471
472      if (foundJump &&
473         !foundCompare &&
474          MI->getOperand(0).isReg() &&
475          MI->getOperand(0).getReg() == predReg) {
476
477        // Not all compares can be new value compare. Arch Spec: 7.6.1.1
478        if (QII->isNewValueJumpCandidate(MI)) {
479
480          assert((MI->getDesc().isCompare()) &&
481              "Only compare instruction can be collapsed into New Value Jump");
482          isSecondOpReg = MI->getOperand(2).isReg();
483
484          if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
485                                        afterRA, jmpPos, MF))
486            break;
487
488          cmpInstr = MI;
489          cmpPos = MII;
490          foundCompare = true;
491
492          // We need cmpReg1 and cmpOp2(imm or reg) while building
493          // new value jump instruction.
494          cmpReg1 = MI->getOperand(1).getReg();
495          if (MI->getOperand(1).isKill())
496            MO1IsKill = true;
497
498          if (isSecondOpReg) {
499            cmpOp2 = MI->getOperand(2).getReg();
500            if (MI->getOperand(2).isKill())
501              MO2IsKill = true;
502          } else
503            cmpOp2 = MI->getOperand(2).getImm();
504          continue;
505        }
506      }
507
508      if (foundCompare && foundJump) {
509
510        // If "common" checks fail, bail out on this BB.
511        if (!commonChecksToProhibitNewValueJump(afterRA, MII))
512          break;
513
514        bool foundFeeder = false;
515        MachineBasicBlock::iterator feederPos = MII;
516        if (MI->getOperand(0).isReg() &&
517            MI->getOperand(0).isDef() &&
518           (MI->getOperand(0).getReg() == cmpReg1 ||
519            (isSecondOpReg &&
520             MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
521
522          unsigned feederReg = MI->getOperand(0).getReg();
523
524          // First try to see if we can get the feeder from the first operand
525          // of the compare. If we can not, and if secondOpReg is true
526          // (second operand of the compare is also register), try that one.
527          // TODO: Try to come up with some heuristic to figure out which
528          // feeder would benefit.
529
530          if (feederReg == cmpReg1) {
531            if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
532              if (!isSecondOpReg)
533                break;
534              else
535                continue;
536            } else
537              foundFeeder = true;
538          }
539
540          if (!foundFeeder &&
541               isSecondOpReg &&
542               feederReg == (unsigned) cmpOp2)
543            if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
544              break;
545
546          if (isSecondOpReg) {
547            // In case of CMPLT, or CMPLTU, or EQ with the second register
548            // to newify, swap the operands.
549            if (cmpInstr->getOpcode() == Hexagon::CMPEQrr &&
550                                     feederReg == (unsigned) cmpOp2) {
551              unsigned tmp = cmpReg1;
552              bool tmpIsKill = MO1IsKill;
553              cmpReg1 = cmpOp2;
554              MO1IsKill = MO2IsKill;
555              cmpOp2 = tmp;
556              MO2IsKill = tmpIsKill;
557            }
558
559            // Now we have swapped the operands, all we need to check is,
560            // if the second operand (after swap) is the feeder.
561            // And if it is, make a note.
562            if (feederReg == (unsigned)cmpOp2)
563              isSecondOpNewified = true;
564          }
565
566          // Now that we are moving feeder close the jump,
567          // make sure we are respecting the kill values of
568          // the operands of the feeder.
569
570          bool updatedIsKill = false;
571          for (unsigned i = 0; i < MI->getNumOperands(); i++) {
572            MachineOperand &MO = MI->getOperand(i);
573            if (MO.isReg() && MO.isUse()) {
574              unsigned feederReg = MO.getReg();
575              for (MachineBasicBlock::iterator localII = feederPos,
576                   end = jmpPos; localII != end; localII++) {
577                MachineInstr *localMI = localII;
578                for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
579                  MachineOperand &localMO = localMI->getOperand(j);
580                  if (localMO.isReg() && localMO.isUse() &&
581                      localMO.isKill() && feederReg == localMO.getReg()) {
582                    // We found that there is kill of a use register
583                    // Set up a kill flag on the register
584                    localMO.setIsKill(false);
585                    MO.setIsKill();
586                    updatedIsKill = true;
587                    break;
588                  }
589                }
590                if (updatedIsKill) break;
591              }
592            }
593            if (updatedIsKill) break;
594          }
595
596          MBB->splice(jmpPos, MI->getParent(), MI);
597          MBB->splice(jmpPos, MI->getParent(), cmpInstr);
598          DebugLoc dl = MI->getDebugLoc();
599          MachineInstr *NewMI;
600
601           assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
602                      "This compare is not a New Value Jump candidate.");
603          unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
604                                               isSecondOpNewified,
605                                               jmpTarget, MBPI);
606          if (invertPredicate)
607            opc = QII->getInvertedPredicatedOpcode(opc);
608
609          if (isSecondOpReg)
610            NewMI = BuildMI(*MBB, jmpPos, dl,
611                                  QII->get(opc))
612                                    .addReg(cmpReg1, getKillRegState(MO1IsKill))
613                                    .addReg(cmpOp2, getKillRegState(MO2IsKill))
614                                    .addMBB(jmpTarget);
615
616          else if ((cmpInstr->getOpcode() == Hexagon::CMPEQri ||
617                    cmpInstr->getOpcode() == Hexagon::CMPGTri) &&
618                    cmpOp2 == -1 )
619            // Corresponding new-value compare jump instructions don't have the
620            // operand for -1 immediate value.
621            NewMI = BuildMI(*MBB, jmpPos, dl,
622                                  QII->get(opc))
623                                    .addReg(cmpReg1, getKillRegState(MO1IsKill))
624                                    .addMBB(jmpTarget);
625
626          else
627            NewMI = BuildMI(*MBB, jmpPos, dl,
628                                  QII->get(opc))
629                                    .addReg(cmpReg1, getKillRegState(MO1IsKill))
630                                    .addImm(cmpOp2)
631                                    .addMBB(jmpTarget);
632
633          assert(NewMI && "New Value Jump Instruction Not created!");
634          (void)NewMI;
635          if (cmpInstr->getOperand(0).isReg() &&
636              cmpInstr->getOperand(0).isKill())
637            cmpInstr->getOperand(0).setIsKill(false);
638          if (cmpInstr->getOperand(1).isReg() &&
639              cmpInstr->getOperand(1).isKill())
640            cmpInstr->getOperand(1).setIsKill(false);
641          cmpInstr->eraseFromParent();
642          jmpInstr->eraseFromParent();
643          ++nvjGenerated;
644          ++NumNVJGenerated;
645          break;
646        }
647      }
648    }
649  }
650
651  return true;
652
653}
654
655FunctionPass *llvm::createHexagonNewValueJump() {
656  return new HexagonNewValueJump();
657}
658