Searched refs:v4i32 (Results 1 - 25 of 31) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp211 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0},
212 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0},
213 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0},
214 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0},
250 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i16, 0},
251 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i8, 0},
281 { ISD::ADD, MVT::v4i32, MVT::v4i16, 0 },
284 { ISD::SUB, MVT::v4i32, MVT::v4i16, 0 },
287 { ISD::MUL, MVT::v4i32, MVT::v4i16, 0 },
290 { ISD::SHL, MVT::v4i32, MV
[all...]
H A DARMISelLowering.cpp232 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
256 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
400 // It is legal to extload from v4i8 to v4i16 or v4i32.
402 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
403 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
405 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
413 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
414 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
796 addQRTypeForNEON(MVT::v4i32);
[all...]
H A DARMISelDAGToDAG.cpp1794 (CanChangeType || LoadedVT == MVT::v4i32 ||
2092 case MVT::v4i32: OpcodeIndex = 2; break;
2237 case MVT::v4i32: OpcodeIndex = 2; break;
2405 case MVT::v4i32: OpcodeIndex = 1; break;
2938 case MVT::v4i32: OpcodeIndex = 2; break;
3933 case MVT::v4i32: Opc = ARM::VZIPq32; break;
3956 case MVT::v4i32: Opc = ARM::VUZPq32; break;
3978 case MVT::v4i32: Opc = ARM::VTRNq32; break;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp204 { ISD::MUL, MVT::v4i32, 11 }, // pmulld
228 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
449 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
450 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence
453 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
454 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence
465 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
467 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41())
513 { ISD::SHL, MVT::v4i32, 1 }, // pslld
517 { ISD::SRL, MVT::v4i32,
[all...]
H A DX86ISelLowering.cpp872 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass
890 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
892 setOperationAction(ISD::MULHU, MVT::v4i32, Custom);
893 setOperationAction(ISD::MULHS, MVT::v4i32, Custom);
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
918 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom);
919 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom);
924 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
927 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
940 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
[all...]
H A DX86ISelDAGToDAG.cpp4089 VPTESTM_CASE(v4i32, DZ128##SUFFIX) \
5441 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32)
5447 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64)
5449 else if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 64)
5468 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32)
5472 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64)
5474 else if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 64)
5535 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32)
5541 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64)
5543 else if (IndexVT == MVT::v4i32
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp313 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
314 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
321 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
322 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
338 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
341 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
379 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
382 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
1022 {ISD::ADD, MVT::v4i32, 1}, member in class:MVT
1043 { TTI::SK_Broadcast, MVT::v4i32,
[all...]
H A DAArch64ISelDAGToDAG.cpp667 case MVT::v4i32:
696 case MVT::v4i32:
707 case MVT::v4i32:
3520 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3547 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3574 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3601 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3628 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3655 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3682 } else if (VT == MVT::v4i32 || V
[all...]
H A DAArch64ISelLowering.cpp170 addQRTypeForNEON(MVT::v4i32);
800 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32);
801 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32);
811 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
812 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
813 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
823 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i16, MVT::v4i32);
824 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i16, MVT::v4i32);
836 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
840 MVT::v16i8, MVT::v8i16, MVT::v4i32, MV
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.cpp145 case MVT::v4i32:
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h96 v4i32 = 47, // 4 x i32
374 SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 ||
509 case v4i32:
682 case v4i32:
843 case v4i32:
1056 if (NumElements == 4) return MVT::v4i32;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp62 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
117 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
132 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
136 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
141 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
147 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
152 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
161 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
168 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
173 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
[all...]
H A DWebAssemblyAsmPrinter.cpp61 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
H A DWebAssemblyFastISel.cpp137 case MVT::v4i32:
691 case MVT::v4i32:
797 case MVT::v4i32:
1320 case MVT::v4i32:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp624 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
677 // We promote all non-typed operations to v4i32.
679 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
681 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
683 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
685 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
687 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
690 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
692 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
740 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expan
[all...]
H A DPPCTargetTransformInfo.cpp916 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp64 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass);
74 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
97 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
98 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
104 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
111 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom);
116 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
123 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand);
147 setOperationAction(ISD::SETCC, MVT::v4i32, Expan
[all...]
H A DAMDGPUISelLowering.cpp84 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
102 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
108 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
204 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
222 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
228 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
272 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Expand);
331 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
342 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
419 MVT::v2i32, MVT::v3i32, MVT::v4i32, MV
[all...]
H A DSIISelLowering.cpp144 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
191 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
200 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
209 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
214 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
251 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Expand);
323 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
326 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
329 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
332 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp1046 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
1085 ViaVecTy = MVT::v4i32;
1153 CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1254 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1258 Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
H A DMipsSEInstrInfo.cpp277 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
355 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
H A DMipsSEISelLowering.cpp120 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
355 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
1397 ViaVecTy = MVT::v4i32;
1435 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1436 ViaVecTy = MVT::v4i32;
1485 DAG.getBuildVector(MVT::v4i32, DL,
1886 // an equivalent v4i32.
2497 ViaVecTy = MVT::v4i32;
/freebsd-13-stable/contrib/llvm-project/clang/lib/Headers/
H A Dmsa.h22 typedef int v4i32 __attribute__((vector_size(16), aligned(16))); typedef
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp261 case MVT::v4i32:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp112 case MVT::v4i32: return "MVT::v4i32";

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